JP2008004971A - Semiconductor device, and its manufacturing method - Google Patents

Semiconductor device, and its manufacturing method Download PDF

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JP2008004971A
JP2008004971A JP2007249579A JP2007249579A JP2008004971A JP 2008004971 A JP2008004971 A JP 2008004971A JP 2007249579 A JP2007249579 A JP 2007249579A JP 2007249579 A JP2007249579 A JP 2007249579A JP 2008004971 A JP2008004971 A JP 2008004971A
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resin
mold
resin sheet
semiconductor device
die pad
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JP2008004971A5 (en
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Kenichi Hayashi
建一 林
Hisashi Kawato
寿 川藤
Tatsuyuki Takeshita
竜征 竹下
Nobuhito Funakoshi
信仁 船越
Hiroyuki Ozaki
弘幸 尾崎
Kazuhiro Tada
和弘 多田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device in which the heat radiation characteristic is superior, insulating properties are high, and further a miniaturization is possible. <P>SOLUTION: The power semiconductor device composed of a resin-molded chip includes: a frame with a top surface and a rear surface, containing a die pad; a power chip mounted on the top surface of the die pad; an insulating resin sheet with a first surface and a second surface facing to each other, which is arranged so that the rear surface of the die pad is brought into contact with the first surface thereof, has a size containing the die pad, and has thermal conductivity higher than that of the mold resin; a metal foil disposed on the second surface of the resin sheet; and a mixture layer of the resin sheet and the mold resin in which both of them are mixed in a liquefied state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、パワーチップを含む電力用の半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a power semiconductor device including a power chip.

従来の電力用の半導体装置では、パワーチップやＩＣチップが、それぞれフレーム上にダイボンドされ、更に、これらのチップは樹脂により封止されている。パワーチップは放熱量が大きいため、例えば、半導体装置の裏面に冷却フィンを取り付けて、放熱効率を高めている。パワーチップを載置するフレームは樹脂に覆われて、裏面に取り付けられる冷却フィンから絶縁される（例えば、特許文献１）。   In a conventional power semiconductor device, a power chip and an IC chip are each die-bonded on a frame, and these chips are sealed with a resin. Since the power chip has a large heat dissipation amount, for example, a cooling fin is attached to the back surface of the semiconductor device to increase the heat dissipation efficiency. The frame on which the power chip is placed is covered with resin and insulated from cooling fins attached to the back surface (for example, Patent Document 1).

また、半導体装置の放熱特性を向上させるために、半導体装置の裏面にアルミナ等からなる薄板の絶縁体を取り付けた半導体装置も提案されている（例えば、特許文献２）。
特開２０００−１３８３４３号公報 特開２００１−１５６２５３号公報 In addition, in order to improve the heat dissipation characteristics of the semiconductor device, a semiconductor device in which a thin plate insulator made of alumina or the like is attached to the back surface of the semiconductor device has also been proposed (for example, Patent Document 2).
JP 2000-138343 A JP 2001-156253 A

しかしながら、前者の半導体装置では、放熱特性を向上させるには、パワーチップを載置したフレームを覆う樹脂、具体的には、パワーチップを載置したフレームの裏面と半導体装置の裏面との間の樹脂を薄くする必要があるが、この部分の樹脂を薄くすると絶縁特性が逆に低下するという問題があった。   However, in the former semiconductor device, in order to improve the heat dissipation characteristics, the resin covering the frame on which the power chip is placed, specifically, the gap between the back surface of the frame on which the power chip is placed and the back surface of the semiconductor device. Although it is necessary to make the resin thinner, there is a problem that if this portion of the resin is made thinner, the insulating properties are lowered.

一方、後者の半導体装置では、絶縁体と樹脂との熱膨張係数が大きく異なるため、パワーチップの発熱により樹脂から絶縁体が剥離するという問題があった。また、絶縁体と樹脂との間に界面ができるため、かかる界面での沿面絶縁を確保するためには沿面絶縁距離を確保しなければならず、半導体装置が大型化するという問題もあった。   On the other hand, in the latter semiconductor device, since the thermal expansion coefficients of the insulator and the resin are greatly different, there is a problem that the insulator is separated from the resin due to heat generated by the power chip. In addition, since an interface is formed between the insulator and the resin, it is necessary to ensure a creeping insulation distance in order to ensure creeping insulation at the interface, and there is a problem that the semiconductor device is enlarged.

そこで、本発明は、放熱特性に優れ、かつ絶縁性が高く、更に小型化が可能な半導体装置の提供を目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that has excellent heat dissipation characteristics, high insulating properties, and can be further miniaturized.

本発明は、チップが樹脂モールドされた半導体装置において、表面と裏面を備えダイパッドを含むフレームと、ダイパッドの表面に載置されたパワーチップと、対向する第１面と第２面とを備えダイパッドの裏面がその第１面と接するように配置された絶縁性の樹脂シートと、樹脂シートの第１面上にパワーチップを封止するように設けられたモールド樹脂とを含むものである。かかる半導体装置において、樹脂シートの熱伝導率は、モールド樹脂の熱伝導率より大きい。   The present invention relates to a semiconductor device in which a chip is resin-molded, and includes a frame including a die pad including a front surface and a back surface, a power chip mounted on the surface of the die pad, and a first surface and a second surface facing each other. Insulating resin sheet disposed so that its back surface is in contact with the first surface, and a mold resin provided so as to seal the power chip on the first surface of the resin sheet. In such a semiconductor device, the thermal conductivity of the resin sheet is larger than the thermal conductivity of the mold resin.

また、本発明は、チップを樹脂モールドした半導体装置の製造方法であって、表面と裏面を備えダイパッドを有するフレームを準備するフレーム準備工程と、第１面と第２面を有する絶縁性の樹脂シートを準備する工程と、ダイパッドの表面上にパワーチップを載置する工程と、ダイパッドの裏面が樹脂シートの第１面に接するように樹脂シートの第１面上にフレームを配置する工程と、樹脂シートの第１面上に、パワーチップを埋め込むように封止用樹脂を充填する樹脂モールド工程とを含む。樹脂シートには、封止用樹脂より熱伝導率の大きな樹脂を用いる。   The present invention also relates to a method of manufacturing a semiconductor device in which a chip is resin-molded, a frame preparation step of preparing a frame having a front surface and a back surface and having a die pad, and an insulating resin having a first surface and a second surface A step of preparing a sheet, a step of placing a power chip on the surface of the die pad, a step of arranging a frame on the first surface of the resin sheet so that the back surface of the die pad is in contact with the first surface of the resin sheet, And a resin molding step of filling a sealing resin so as to embed the power chip on the first surface of the resin sheet. As the resin sheet, a resin having a higher thermal conductivity than the sealing resin is used.

本発明にかかる半導体装置では、樹脂シートを用いることにより、放熱特性に優れ、かつ、絶縁性を高くすることができる。更には、半導体装置の小型化も可能となる。   In the semiconductor device according to the present invention, by using the resin sheet, the heat dissipation characteristics are excellent and the insulating property can be increased. Furthermore, the semiconductor device can be downsized.

実施の形態１．
図１は、全体が１００で表される、本実施の形態にかかる半導体装置の斜視図である。また、図２は、図１の半導体装置１００の裏面図、図３は、図１の半導体装置１００の、Ｉ−Ｉ方向に見た断面図である。更に、図４は、図１の半導体装置１００の内部の一部分を示す斜視図である。 Embodiment 1 FIG.
FIG. 1 is a perspective view of the semiconductor device according to the present embodiment, indicated as a whole by 100. 2 is a back view of the semiconductor device 100 of FIG. 1, and FIG. 3 is a cross-sectional view of the semiconductor device 100 of FIG. FIG. 4 is a perspective view showing a part of the inside of the semiconductor device 100 of FIG.

図１に示すように、半導体装置１００は、樹脂モールド型パッケージ構造からなり、複数の金属製のフレーム１が両側に設けられたモールド樹脂２を含む。モールド樹脂２は、好適にはエポキシ樹脂からなる。   As shown in FIG. 1, a semiconductor device 100 has a resin mold type package structure and includes a mold resin 2 in which a plurality of metal frames 1 are provided on both sides. The mold resin 2 is preferably made of an epoxy resin.

図２に示すように、モールド樹脂２の裏面には、例えば銅からなる金属箔４が裏面に取り付けられた絶縁性の樹脂シート３が設けられている。樹脂シート３は、好適には、フィラーを含むエポキシ樹脂からなる。フィラーは、好適には、ＳｉＯ２、Ａｌ２Ｏ３、ＡｌＮ、Ｓｉ３Ｎ４、及びＢＮから選択される１又は複数の材料からなる。樹脂シート３の熱伝導率は、モールド樹脂２の熱伝導率より大きくなっている。 As shown in FIG. 2, an insulating resin sheet 3 in which a metal foil 4 made of, for example, copper is attached to the back surface is provided on the back surface of the mold resin 2. The resin sheet 3 is preferably made of an epoxy resin containing a filler. Filler is preferably composed of one or more materials selected from SiO 2, Al 2 O 3, AlN, Si 3 N 4, and BN. The thermal conductivity of the resin sheet 3 is larger than the thermal conductivity of the mold resin 2.

図３に示すように、半導体装置１００は、複数のフレーム１を含む。図４に、更に詳しく示すように、一のフレーム１には、ロジックチップのようなＩＣチップ７が載置されている。また、他方のフレーム１は、ダイパッド部１ａと段差部１ｂとを含み、ダイパッド部１ａの上に、ＩＧＢＴ５ａやＦＷDiode５ｂのようなパワーチップ５が載置されている。パワーチップ５、ＩＣチップ７、及びフレーム１の間は、例えば金やアルミニウムからなるボンディボンディングワイヤ６、８で接続され、ＩＣチップ７により、パワーチップ５の動作が制御される。
一般に、パワーチップ５やＩＣチップ７は、はんだや銀ペーストを用いてフレーム１に固定される。また、パワーチップ５の接続にはアルミニウムのボンディングワイヤ８が用いられ、ＩＣチップ７の接続には、これより直径の小さな金のボンディングワイヤ６が用いられる。
なお、パワーチップ５やＩＣチップ７は、半導体装置１００の機能に応じて複数個設けても構わない。 As shown in FIG. 3, the semiconductor device 100 includes a plurality of frames 1. As shown in more detail in FIG. 4, an IC chip 7 such as a logic chip is placed on one frame 1. The other frame 1 includes a die pad portion 1a and a step portion 1b, and a power chip 5 such as an IGBT 5a or an FWDiode 5b is placed on the die pad portion 1a. The power chip 5, the IC chip 7, and the frame 1 are connected by bond bonding wires 6 and 8 made of, for example, gold or aluminum, and the operation of the power chip 5 is controlled by the IC chip 7.
In general, the power chip 5 and the IC chip 7 are fixed to the frame 1 using solder or silver paste. Further, an aluminum bonding wire 8 is used for connecting the power chip 5, and a gold bonding wire 6 having a smaller diameter is used for connecting the IC chip 7.
A plurality of power chips 5 and IC chips 7 may be provided according to the function of the semiconductor device 100.

上述のように、モールド樹脂２は、金属箔４が取り付けられた絶縁性の樹脂シート３を含み、モールド樹脂２の裏面から金属箔４が露出している。かかる金属箔４は、樹脂シート３をダメージから保護するため、樹脂シート３は高い絶縁性を維持できる。かかるダメージとしては、例えば、半導体装置１００を外部ヒートシンク（図示せず）に、ねじ止めする際に、半導体装置１００と外部ヒートシンクとの間に異物を噛み込んだままでねじ止めを行なった場合に発生するダメージが考えられる。なお、ダメージが発生しにくい場合は、金属箔４を設けない構造を採用してもよい。この場合、モールド樹脂２の裏面からは、樹脂シート３が露出することとなる。   As described above, the mold resin 2 includes the insulating resin sheet 3 to which the metal foil 4 is attached, and the metal foil 4 is exposed from the back surface of the mold resin 2. Since the metal foil 4 protects the resin sheet 3 from damage, the resin sheet 3 can maintain high insulation. Such damage occurs, for example, when the semiconductor device 100 is screwed to an external heat sink (not shown) and the foreign material is caught between the semiconductor device 100 and the external heat sink. Damage to be considered. If damage is unlikely to occur, a structure in which the metal foil 4 is not provided may be employed. In this case, the resin sheet 3 is exposed from the back surface of the mold resin 2.

樹脂シート３の上には、ダイパッド部１ａの裏面が直接接するように、フレーム１が載置されている。樹脂シート３の面積は、ダイパッド部１ａの面積よりも大きくなっている。更に、パワーチップ５、ＩＣチップ７等は、モールド樹脂２で封止されている。   On the resin sheet 3, the frame 1 is placed so that the back surface of the die pad portion 1a is in direct contact. The area of the resin sheet 3 is larger than the area of the die pad portion 1a. Further, the power chip 5, the IC chip 7, etc. are sealed with the mold resin 2.

樹脂シート３とモールド樹脂２とが接触する領域には、両方の樹脂が混合した混合層９が形成されている。このように、混合層９を介して樹脂シート３とモールド樹脂２とが接続されるため、混合層９のない場合に比較して、樹脂シート３とモールド樹脂２との間の熱伝導性が高くなり、放熱特性が向上する。混合層９の形成方法については後述する。   A mixed layer 9 in which both resins are mixed is formed in a region where the resin sheet 3 and the mold resin 2 are in contact with each other. As described above, since the resin sheet 3 and the mold resin 2 are connected via the mixed layer 9, the thermal conductivity between the resin sheet 3 and the mold resin 2 is lower than when the mixed layer 9 is not provided. Increases heat dissipation characteristics. A method for forming the mixed layer 9 will be described later.

樹脂シート３の熱伝導率は、モールド樹脂２の熱伝導率より大きく、特に、２倍以上であることが好ましい。これにより、放熱特性に優れた半導体装置１００を得ることができる。   The thermal conductivity of the resin sheet 3 is larger than the thermal conductivity of the mold resin 2, and is particularly preferably twice or more. Thereby, the semiconductor device 100 excellent in heat dissipation characteristics can be obtained.

次に、図５、６を参照しながら、半導体装置１００の製造方法について説明する。かかる製造方法は、以下の工程１〜８を含む。なお、図５、６は、図１のＩ−Ｉと同じ方向に見た断面図である。   Next, a method for manufacturing the semiconductor device 100 will be described with reference to FIGS. Such a manufacturing method includes the following steps 1 to 8. 5 and 6 are cross-sectional views seen in the same direction as II in FIG.

工程１：図５（ａ）に示すように、例えば銅からなるフレーム１を準備する。続いて、一のフレーム１の上にＩＣチップ７を、他方のフレーム１のダイパッド部１ａの上にパワーチップ６を、それぞれ、はんだや銀ペースト等を用いて固定する。   Step 1: As shown in FIG. 5A, a frame 1 made of, for example, copper is prepared. Subsequently, the IC chip 7 is fixed on one frame 1 and the power chip 6 is fixed on the die pad portion 1a of the other frame 1 using solder, silver paste, or the like.

工程２：図５（ｂ）に示すように、アルミニウムのボンディングワイヤ６を用いて、パワーチップ５同士、パワーチップ５とフレーム１、フレーム１同士を接続する（アルミワイヤボンド工程）。なお、ボンディングワイヤ６には、アルミニウムを主成分とする合金や、他の金属を用いても構わない。   Step 2: As shown in FIG. 5B, the power chips 5 and the power chips 5 and the frames 1 and 1 are connected to each other using an aluminum bonding wire 6 (aluminum wire bonding step). The bonding wire 6 may be made of an alloy mainly composed of aluminum or other metal.

工程３：図５（ｃ）に示すように、金のボンディングワイヤ７を用いて、ＩＣチップ７とフレーム１を接続する（金ワイヤボンド工程）。なお、ボンディングワイヤ７には、金を主成分とする合金や、他の金属を用いても構わない。   Step 3: As shown in FIG. 5C, the IC chip 7 and the frame 1 are connected using a gold bonding wire 7 (gold wire bonding step). The bonding wire 7 may be made of an alloy mainly composed of gold or other metal.

工程４：図５（ｄ）に示すように、樹脂封止用金型２０を準備する。樹脂封止用金型２０は、上部金型２１と下部金型２２に分かれるようになっている。続いて、裏面に金属箔４を取り付けた絶縁性の樹脂シート３を準備し、樹脂封止用金型２０の内部の所定の位置に配置する。この場合、金属箔４の裏面が下部金型２２の内部底面に接するように、樹脂シート３が配置される。ここで、樹脂シート３には、半硬化状態の樹脂が用いられる。樹脂シート３は、例えばエポキシ樹脂からなり、上述のように、フィラーを含むことが好ましい。
なお、半硬化状態の樹脂とは、常温では固体であるが、高温では一旦溶融した後に完全硬化に向かう、硬化が未完全状態な熱硬化樹脂をいう。 Step 4: As shown in FIG. 5D, a resin sealing mold 20 is prepared. The resin sealing mold 20 is divided into an upper mold 21 and a lower mold 22. Subsequently, the insulating resin sheet 3 having the metal foil 4 attached to the back surface is prepared and disposed at a predetermined position inside the resin sealing mold 20. In this case, the resin sheet 3 is disposed so that the back surface of the metal foil 4 is in contact with the inner bottom surface of the lower mold 22. Here, a semi-cured resin is used for the resin sheet 3. The resin sheet 3 is made of, for example, an epoxy resin, and preferably includes a filler as described above.
The semi-cured resin refers to a thermosetting resin that is solid at normal temperature but is once melted at high temperature and then proceeds to complete curing and is not completely cured.

工程５：図６（ｅ）に示すように、パワーチップ５等を実装したフレーム１を、樹脂封止用金型２０中の所定の位置に配置する。この場合、フレーム１のダイパッド部の裏面が樹脂シート３の上面に接するように、フレーム１を配置する。   Step 5: As shown in FIG. 6E, the frame 1 on which the power chip 5 and the like are mounted is disposed at a predetermined position in the resin sealing mold 20. In this case, the frame 1 is arranged so that the back surface of the die pad portion of the frame 1 is in contact with the upper surface of the resin sheet 3.

工程６：図６（ｆ）に示すように、下部金型２２に上部金型２１を取り付けて固定する。続いて、トランスファモールド成形法により、例えばエポキシ樹脂からなる封止用樹脂１２を樹脂封止用金型２０内に充填する。図６（ｆ）では、左方から充填する。
かかる工程で、樹脂封止用金型２０内に設置された半硬化状態の樹脂シート３は、まず、高温の樹脂封止用金型２０から熱をもらい、一旦溶融する。更に、溶融した樹脂シート３と、ダイパッド１ａとが、加圧状態で注入される封止用樹脂１２により加圧され、固着される。 Step 6: As shown in FIG. 6F, the upper mold 21 is attached and fixed to the lower mold 22. Subsequently, a sealing resin 12 made of, for example, an epoxy resin is filled in the resin sealing mold 20 by a transfer mold molding method. In FIG. 6F, the filling is performed from the left side.
In this process, the semi-cured resin sheet 3 installed in the resin sealing mold 20 is first melted by receiving heat from the high temperature resin sealing mold 20. Further, the molten resin sheet 3 and the die pad 1a are pressed and fixed by the sealing resin 12 injected in a pressurized state.

工程７：図６（ｇ）に示すように、封止用樹脂２、樹脂シート３を加熱硬化させる。かかる工程で、樹脂シート３と封止用樹脂１２とは、共に溶融した状態で接触するため、混合し、その接触部分に混合層９が形成される。
工程４〜７は、いわゆるトランスファモールド工程となる。かかる工程では、樹脂シート３が溶融時に加圧されるが、樹脂封止用金型２０内全体が封止用樹脂１２により加圧されているため、樹脂シート３の厚さはほとんど変化しない。一方、樹脂封止用金型２０内の各部が封止用樹脂１２により同時に充填されるわけではなく、各部に圧力が均等にかかるまでの時間には、僅かであるが時間のずれが生じる。従って、樹脂シート３の特性としては、溶融時の流動性が小さい方が望ましい。 Step 7: As shown in FIG. 6G, the sealing resin 2 and the resin sheet 3 are heat-cured. In this process, since the resin sheet 3 and the sealing resin 12 are in contact with each other in a molten state, they are mixed and a mixed layer 9 is formed at the contact portion.
Steps 4 to 7 are so-called transfer molding steps. In such a process, the resin sheet 3 is pressurized when it is melted, but since the entire inside of the resin sealing mold 20 is pressurized by the sealing resin 12, the thickness of the resin sheet 3 hardly changes. On the other hand, each part in the resin sealing mold 20 is not filled with the sealing resin 12 at the same time, and there is a slight time shift until the pressure is uniformly applied to each part. Therefore, as a characteristic of the resin sheet 3, it is desirable that the fluidity at the time of melting is small.

工程８：樹脂封止用金型２０から取り出した後、モールド樹脂を完全硬化させるためのポストキュア、タイバーなどのフレーム余分部の切断等を行なう。更に、フレーム（外部端子）１の成形を行なうことにより、図１に示すような半導体装置１００が完成する。   Step 8: After taking out from the mold 20 for resin sealing, cutting of extra frame parts such as post-cure and tie bar for completely curing the mold resin is performed. Further, by forming the frame (external terminal) 1, the semiconductor device 100 as shown in FIG. 1 is completed.

なお、樹脂シート３は、エポキシ樹脂を主成分とし、主に熱伝導性を高める目的から、上述のようにＳｉＯ２等の絶縁性フィラーが充填されていることが好ましい。これらのフィラーは、また、絶縁シート３の線膨張係数を小さくする効果を持つため、ダイパッド１ａや金属箔４との熱膨張係数の差が小さくなる。このため、温度変化に起因する剥離が発生しにくい、信頼性に優れたものとすることができる。 In addition, it is preferable that the resin sheet 3 is mainly filled with an insulating filler such as SiO 2 as described above for the purpose of mainly increasing the thermal conductivity with an epoxy resin as a main component. Since these fillers also have the effect of reducing the linear expansion coefficient of the insulating sheet 3, the difference in thermal expansion coefficient between the die pad 1a and the metal foil 4 is reduced. For this reason, peeling due to temperature change hardly occurs, and excellent reliability can be achieved.

また、封止用樹脂１２も、樹脂シート３と同様に、エポキシ樹脂を主成分とする材料とすると、混合層９を安定して形成できる。かかる場合、封止用樹脂１２と樹脂シート３との明確な界面が無くなり、その間での沿面絶縁を考慮する必要がなくなり、結果として半導体装置の小型化が可能となる。   Moreover, if the sealing resin 12 is also made of a material mainly composed of an epoxy resin, like the resin sheet 3, the mixed layer 9 can be stably formed. In such a case, there is no clear interface between the sealing resin 12 and the resin sheet 3, and it is not necessary to consider creeping insulation therebetween, and as a result, the semiconductor device can be miniaturized.

更に、樹脂シート３では、フィラーの形状を鱗片状にすることで、粒状とする場合に比べ、絶縁性を安定的に確保できることが、後述のように実験により明らかになっている。
かかる実験では、鱗片状フィラーを充填した樹脂シートと、同量の粒状フィラーを充填した樹脂シートを用いて、半導体装置１００を製作し、絶縁試験を行った。絶縁試験の結果を表１に示す。 Furthermore, in the resin sheet 3, it has been clarified by experiments as will be described later that the insulating property can be stably ensured by making the shape of the filler scaly as compared with the case where the filler is granular.
In this experiment, the semiconductor device 100 was manufactured by using a resin sheet filled with scaly filler and a resin sheet filled with the same amount of granular filler, and an insulation test was performed. The results of the insulation test are shown in Table 1.

（表１）
鱗片状 ｒ／Ｎ ＝ ０／１０
粒状 ｒ／Ｎ ＝ ３／１０
ここで、ｒは不合格となったサンプルの数量、Ｎは試験に投入したサンプルの数量を示す。 (Table 1)
Scaly r / N = 0/10
Granular r / N = 3/10
Here, r represents the number of rejected samples, and N represents the number of samples put into the test.

更に、鱗片状フィラーでは、粒状フィラーに比べ、フィラーの比表面積が大きいため、シート樹脂との接触面積も大きくなり、溶融時の流動性を小さくすることができる。   Furthermore, in the scale-like filler, since the specific surface area of the filler is larger than that of the granular filler, the contact area with the sheet resin is also increased, and the fluidity at the time of melting can be reduced.

また、フィラーのサイズについては、大きいサイズの（最大直径の大きな）フィラーと、小さいサイズの（最大直径の小さな）フィラーとを、混ぜて用いても良い。図７は、２種のサイズのフィラーを含む樹脂シート３の断面の拡大図である。樹脂シート３は、大きいサイズのフィラー３１と、小さいサイズのフィラー３２とが、エポキシ樹脂等の樹脂層３３に含まれた構造となっている。
図７のように、大きいサイズのフィラー３１間の間隙に、小さなサイズのフィラー３２を充填することが出来るため、樹脂シート３の熱伝導性を更に向上できる。 Moreover, about the size of a filler, you may mix and use a filler with a large size (large largest diameter) and a filler with a small size (small maximum diameter). FIG. 7 is an enlarged view of a cross section of the resin sheet 3 including fillers of two sizes. The resin sheet 3 has a structure in which a filler 31 having a large size and a filler 32 having a small size are included in a resin layer 33 such as an epoxy resin.
As shown in FIG. 7, the gap between the large-sized fillers 31 can be filled with the small-sized fillers 32, so that the thermal conductivity of the resin sheet 3 can be further improved.

以上のように、本実施の形態にかかる半導体装置１００では、絶縁層の厚みを予め規定できる絶縁性の樹脂シート３を用いる。このため、樹脂シート３の膜厚を調整することにより、絶縁特性と放熱特性が両立するように制御できる。   As described above, in the semiconductor device 100 according to the present embodiment, the insulating resin sheet 3 capable of predefining the thickness of the insulating layer is used. For this reason, it is controllable by adjusting the film thickness of the resin sheet 3 so that an insulation characteristic and a thermal radiation characteristic may be compatible.

また、必要な領域にのみ樹脂シート３を設けるため、無駄なコストの削減が可能となる。   Moreover, since the resin sheet 3 is provided only in a necessary area, it is possible to reduce useless cost.

更に、半導体装置１００では、樹脂シート３とモールド樹脂２との界面に混合層９が形成されるため、沿面絶縁を考慮する必要がなくなり、結果として半導体装置の小型化が可能となる。
なお、本実施の形態１では、ＩＣチップ７等をボンディングワイヤにて接続しているが、例えば、金属薄板等の他の部材を用いても良い。更には、ＩＣチップ７とパワーチップ５の間の接続は、一旦中継フレームを介して接続する例を示したが、直接接続してもかまわない。 Furthermore, in the semiconductor device 100, since the mixed layer 9 is formed at the interface between the resin sheet 3 and the mold resin 2, it is not necessary to consider creeping insulation, and as a result, the semiconductor device can be miniaturized.
In the first embodiment, the IC chip 7 and the like are connected by bonding wires, but other members such as a metal thin plate may be used. Furthermore, although the example in which the connection between the IC chip 7 and the power chip 5 is once connected via a relay frame is shown, it may be directly connected.

実施の形態２．
図８は、全体が２００で表される、本実施の形態にかかる半導体装置の断面図である。図８は、図１のＩ−Ｉと同じ方向に見た断面図である。図８中、図１〜３と同一符号は、同一又は相当箇所を示す。 Embodiment 2. FIG.
FIG. 8 is a cross-sectional view of the semiconductor device according to the present embodiment, indicated as a whole by 200. 8 is a cross-sectional view seen in the same direction as II in FIG. In FIG. 8, the same reference numerals as those in FIGS.

本実施の形態２にかかる半導体装置２００では、金属箔４が取り付けられた樹脂シート３が、モールド樹脂２の裏面全面を覆う大きさとなっている。他の構造は、上述の半導体装置１００と同じである。   In the semiconductor device 200 according to the second embodiment, the resin sheet 3 to which the metal foil 4 is attached is large enough to cover the entire back surface of the mold resin 2. Other structures are the same as those of the semiconductor device 100 described above.

半導体装置２００では、放熱特性が向上するとともに、製造工程（上述の工程４）において、樹脂シート３の配置決めが不要となる。即ち、樹脂シート３は、樹脂封止用金型２０の内部底面の大きさに等しいため、配置位置を正確に制御する必要が無くなる。これにより、製造工程が簡略化される。   In the semiconductor device 200, the heat dissipation characteristics are improved and the arrangement of the resin sheet 3 is not required in the manufacturing process (the above-described process 4). That is, since the resin sheet 3 is equal to the size of the inner bottom surface of the resin sealing mold 20, it is not necessary to accurately control the arrangement position. Thereby, a manufacturing process is simplified.

実施の形態３．
図９は、全体が３００で表される、本実施の形態にかかる半導体装置の裏面図である。また、図１０は、図９をIIIV―IIIV方向に見た断面図である。図９、１０中、図１〜３と同一符号は、同一又は相当箇所を示す。 Embodiment 3 FIG.
FIG. 9 is a rear view of the semiconductor device according to the present embodiment, the whole being represented by 300. FIG. FIG. 10 is a cross-sectional view of FIG. 9 viewed in the IIIV-IIIV direction. 9 and 10, the same reference numerals as those in FIGS. 1 to 3 denote the same or corresponding parts.

半導体装置３００は、シート樹脂３の周囲に沿って、複数の凹部４０を有する。また、冷却用フィン（図示せず）を取り付けるためのねじ穴３５を備える。   The semiconductor device 300 has a plurality of recesses 40 along the periphery of the sheet resin 3. Further, a screw hole 35 for attaching a cooling fin (not shown) is provided.

かかる凹部４０は、上述の工程４（図５（ｄ））において、樹脂シート３に位置合わせを容易にするために、樹脂封止用金型２０の内部底面に、複数の突起部（図示せず）を設けたために形成されたものである。樹脂封止用金型２０の内部底面には、樹脂シート３の配置領域に沿って突起部が設けられている。   The recess 40 has a plurality of protrusions (not shown) on the inner bottom surface of the resin sealing mold 20 in order to facilitate alignment with the resin sheet 3 in the above-described step 4 (FIG. 5D). Z)). On the inner bottom surface of the resin sealing mold 20, a protrusion is provided along the arrangement region of the resin sheet 3.

このように、樹脂封止用金型２０の内部底面に突起部を設けることにより、樹脂シート３の位置合わせが容易になり、製造工程の簡略化が可能となる。   In this manner, by providing the protrusion on the inner bottom surface of the resin sealing mold 20, the alignment of the resin sheet 3 is facilitated, and the manufacturing process can be simplified.

なお、図９、１０では、凹部４０の形状を略円柱形状としたが、かかる機能を有する形状であれば、他の形状であっても構わない。また、凹部４０の数も、かかる機能を有する限り、いくつであってもかまわない。
更に、凹部４０の深さは、金属箔４の厚さよりも薄いことが望ましい。これは、凹部４０が誤って金属箔４に重なっても、その先端は樹脂シート３には到達せず、樹脂シート３が損傷を受けないためである。 9 and 10, the shape of the recess 40 is a substantially cylindrical shape, but other shapes may be used as long as the shape has such a function. Further, the number of the recesses 40 is not limited as long as it has such a function.
Further, it is desirable that the depth of the recess 40 is thinner than the thickness of the metal foil 4. This is because even if the concave portion 40 mistakenly overlaps the metal foil 4, the tip does not reach the resin sheet 3 and the resin sheet 3 is not damaged.

本発明の実施の形態１にかかる半導体装置の斜視図である。1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１にかかる半導体装置の裏面図である。It is a rear view of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態にかかる半導体装置の内部の一部分を示す斜視図である。It is a perspective view which shows a part of inside of the semiconductor device concerning embodiment of this invention. 本発明の実施の形態１にかかる半導体装置の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 樹脂シートの拡大断面図である。It is an expanded sectional view of a resin sheet. 本発明の実施の形態２にかかる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態３にかかる半導体装置の裏面図である。It is a back view of the semiconductor device concerning Embodiment 3 of this invention. 本発明の実施の形態３にかかる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning Embodiment 3 of this invention.

符号の説明Explanation of symbols

１ フレーム、２ モールド樹脂、３ 樹脂シート、４ 金属箔、５ パワーチップ、６、８ ボンディングワイヤ、７ ＩＣチップ、９ 混合層、１００ 半導体装置。   1 frame, 2 mold resin, 3 resin sheet, 4 metal foil, 5 power chip, 6, 8 bonding wire, 7 IC chip, 9 mixed layer, 100 semiconductor device.

Claims (2)

チップが樹脂モールドされた半導体装置であって、
表面と裏面を備え、ダイパッドを含むフレームと、
該ダイパッドの表面に載置されたパワーチップと、
該パワーチップを封止するように設けられたモールド樹脂と、
対向する第１面と第２面とを備え、該ダイパッドの裏面がその第１面と接するように配置され、該ダイパッドを包含するサイズで、かつ該モールド樹脂よりも熱伝導率が大きい絶縁性の樹脂シートと、
該樹脂シートの第２面上に設けられた金属箔と、
該樹脂シートと該モールド樹脂とが共に液状化された状態で混合した混合層と、を含むことを特徴とする半導体装置。 A semiconductor device in which a chip is resin-molded,
A frame having a front surface and a back surface, including a die pad;
A power chip placed on the surface of the die pad;
A mold resin provided to seal the power chip;
Insulating property that has a first surface and a second surface facing each other, is disposed so that the back surface of the die pad is in contact with the first surface, has a size including the die pad, and has a higher thermal conductivity than the mold resin. Resin sheet,
A metal foil provided on the second surface of the resin sheet;
A semiconductor device comprising: a mixed layer in which the resin sheet and the mold resin are mixed in a liquefied state. チップを樹脂モールドした半導体装置の製造方法であって、
ａ）第１面と第２面とを有し、絶縁性でかつ樹脂モールドに用いるモールド樹脂よりも熱伝導率が大きい樹脂シートであって、
該樹脂シートは第２面を金属箔で覆われており、
更には常温では固体であるが高温では一旦溶融した後に完全硬化に向かう特徴を有する半硬化状態の樹脂からなる該樹脂シートを準備する工程と、
ｂ）表面と裏面を備え、ダイパッドを有するフレームを準備するフレーム準備工程と、
ｃ）該ダイパッドの表面上にパワーチップを載置する工程と、
ｄ）該樹脂シートの溶融温度より高温の樹脂封止樹脂用金型を準備する工程と、
ｅ）該樹脂封止用金型の内部底面に該金属箔が接するように、該樹脂封止用金型内に該樹脂シートを載置する工程と、
ｆ）該ダイパッドの裏面が該樹脂シートの第１面に接するように、該樹脂シートの第１面上に該フレームを載置する工程と、
ｇ）該樹脂封止用金型内に液状化した該モールド樹脂を加熱加圧注入し、該金型内を充填するとともに、該金型内で該モールド樹脂と該樹脂シートとを加熱硬化させるモールド工程と、を含み、
上記ｇ）モールド工程が、
該ダイパッドの裏面と該樹脂シートの第１面とを固着するとともに、
溶融し液状化した該樹脂シートと、液状化した該モールド樹脂との間で、これらを構成する樹脂を混合させて混合層を形成する工程であることを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device in which a chip is resin-molded,
a) a resin sheet having a first surface and a second surface, which is insulative and has a higher thermal conductivity than a mold resin used for a resin mold,
The resin sheet has a second surface covered with a metal foil,
Further, a step of preparing the resin sheet made of a resin in a semi-cured state having a characteristic of being solid at room temperature but once melted at a high temperature and then proceeding to complete curing;
b) a frame preparation step of preparing a frame having a front surface and a back surface and having a die pad;
c) placing a power chip on the surface of the die pad;
d) preparing a mold for resin-encapsulating resin having a temperature higher than the melting temperature of the resin sheet;
e) placing the resin sheet in the resin sealing mold such that the metal foil contacts the inner bottom surface of the resin sealing mold;
f) placing the frame on the first surface of the resin sheet such that the back surface of the die pad is in contact with the first surface of the resin sheet;
g) The mold resin liquefied in the mold for resin sealing is heated and pressurized to fill the mold, and the mold resin and the resin sheet are heated and cured in the mold. A molding process,
G) the molding step
While fixing the back surface of the die pad and the first surface of the resin sheet,
A method of manufacturing a semiconductor device, comprising a step of forming a mixed layer by mixing a resin constituting these between the molten and liquefied resin sheet and the liquefied mold resin.
JP2007249579A 2007-09-26 2007-09-26 Semiconductor device, and its manufacturing method Pending JP2008004971A (en)

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DE102010061011A1 (en) 2009-12-04 2011-06-09 Denso Corporation, Kariya-City Semiconductor package and method of making the same

Citations (1)

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Publication number Priority date Publication date Assignee Title
JPH10125826A (en) * 1996-10-24 1998-05-15 Hitachi Ltd Semiconductor device and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10125826A (en) * 1996-10-24 1998-05-15 Hitachi Ltd Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010061011A1 (en) 2009-12-04 2011-06-09 Denso Corporation, Kariya-City Semiconductor package and method of making the same
US8368203B2 (en) 2009-12-04 2013-02-05 Denso Corporation Heat radiation member for a semiconductor package with a power element and a control circuit

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