JP2007503659A - 回路設計およびリタイミングの方法および装置 - Google Patents

回路設計およびリタイミングの方法および装置 Download PDF

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JP2007503659A
JP2007503659A JP2006532839A JP2006532839A JP2007503659A JP 2007503659 A JP2007503659 A JP 2007503659A JP 2006532839 A JP2006532839 A JP 2006532839A JP 2006532839 A JP2006532839 A JP 2006532839A JP 2007503659 A JP2007503659 A JP 2007503659A
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オクテム，レベント
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シンプリシティ・インコーポレーテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/35—Delay-insensitive circuit design, e.g. asynchronous or self-timed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2006532839A 2003-05-09 2004-05-06 回路設計およびリタイミングの方法および装置 Pending JP2007503659A (ja)

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US10/435,061 US7162704B2 (en) 2003-05-09 2003-05-09 Method and apparatus for circuit design and retiming
PCT/US2004/014225 WO2004102429A2 (en) 2003-05-09 2004-05-06 Method and apparatus for circuit design and retiming

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US20040225970A1 (en) 2004-11-11
WO2004102429A3 (en) 2005-11-17
US7802213B2 (en) 2010-09-21
EP1623350A2 (en) 2006-02-08
US8429583B2 (en) 2013-04-23
US8949757B2 (en) 2015-02-03
US7162704B2 (en) 2007-01-09
US20070074139A1 (en) 2007-03-29
US20090293032A1 (en) 2009-11-26
US20130239081A1 (en) 2013-09-12
JP4923128B2 (ja) 2012-04-25
JP2010191988A (ja) 2010-09-02
WO2004102429A2 (en) 2004-11-25

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