JP2007335429A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress increase in k value of a low permeability insulating film or oxidation of interconnection in an element region, by preventing the low permeability insulating film from being damaged in a pad region, or preventing a moisture absorption state based on the damage from being transmitted to the low permeability insulating film or the interconnection in the element region. <P>SOLUTION: The semiconductor device 10 comprises a semiconductor substrate 13 having a pad region 11 and an element region 12. On the semiconductor substrate 13, an interconnection layer 16 is provided having a low permeability insulating film 14 and a Cu interconnection 15. A moisture absorption prevention wall 19 separating the pad region 11 and the element region 12 is provided in the interconnection layer 16. The interconnection layer 16 is covered with a passivation film 18 excepting the exposure of an electrode pad 17. On the interconnection layer 16 in the pad region 11, the electrode pad 17 is provided as connected electrically with the Cu interconnection 15 in the element region 12 by a lead-out wire 20 insulated with the passivation film 18. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a low dielectric constant insulating film is applied to a wiring layer.

  2. Description of the Related Art In semiconductor devices, application of a Cu wiring that realizes a reduction in wiring resistance and a low dielectric constant insulating film that reduces the capacitance between wirings has been promoted for higher performance. For example, Patent Document 1 describes a semiconductor device including an interlayer insulating film having a relative dielectric constant of 3 or less. Here, a seal ring is provided in the interlayer insulating film in the vicinity of the edge portion of the semiconductor chip so as to surround the circuit formation region of the semiconductor chip. The seal ring (chip ring) serves to protect the entire circuit formation region of the semiconductor chip from moisture and ions entering from the atmosphere of the outside world.

  Furthermore, in semiconductor devices, in order to increase the density of wiring layers, etc., miniaturization of electrode pads such as Al pads connected to Cu wiring is also being promoted. As the electrode pad becomes smaller, the pressure applied to the electrode pad during wire bonding in the assembly process increases. The pressure applied to the electrode pad mainly passes through the interface between the Al pad and the passivation film as a crack and is transmitted to the lower dielectric constant insulating film on the lower layer side. Since the low dielectric constant insulating film has a property of easily absorbing moisture, it tends to absorb moisture due to damage received from the upper layer.

  When the low dielectric constant insulating film is in a hygroscopic state, the relative dielectric constant (k value) increases, and the oxidation of the Cu wiring that is interlayer-insulated by the low dielectric constant insulating film also proceeds. For example, in a semiconductor device having a pad region and an element region, damage or moisture absorption generated in the pad region gradually propagates to the element region through the low dielectric constant insulating film. As a result, not only the k value of the low dielectric constant insulating film in the element region increases, but also the Cu wiring in the element region is oxidized, leading to an increase in wiring resistance or disconnection. As described above, damage and moisture absorption generated in the low dielectric constant insulating film are factors that reduce the characteristics and reliability of the semiconductor device.

As described in Patent Document 1, a semiconductor chip is usually surrounded by a seal ring (chip ring), which is provided so as to surround the entire chip. For example, even when a pad region and an element region are provided, a chip ring is provided so as to surround the whole. Therefore, the chip ring that is generally used functions to protect the element area and the like against moisture entering from the atmosphere of the outside world, but prevents the penetration of moisture due to damage caused inside the chip. I can't.
Japanese Unexamined Patent Publication No. 2006-5288

  An object of the present invention is to prevent a low dielectric constant insulating film generated in a pad region from being transmitted to a low dielectric constant insulating film or a wiring in the element region by damaging the low dielectric constant insulating film or a moisture absorption state based on the damage. It is an object of the present invention to provide a semiconductor device that can suppress an increase in k value and oxidation of wiring.

  A semiconductor device according to an aspect of the present invention includes an element region, a semiconductor substrate having a pad region arranged in parallel with the element region, a wiring layer provided on the semiconductor substrate and having a low dielectric constant insulating film, A moisture absorption prevention wall provided so as to divide the wiring layer into the element region and the pad region, a passivation film provided so as to cover the wiring layer, and the wiring layer in the pad region And an electrode pad electrically connected to a wiring in the wiring layer in the element region by a lead wiring formed and insulated by the passivation film.

  In the semiconductor device according to the aspect of the present invention, since the moisture absorption preventing wall for separating the element region and the pad region is provided in the wiring layer, the damage of the low dielectric constant insulating film generated in the pad region and the moisture absorption state based on the damage are reduced. Propagation to the element region is prevented. As a result, an increase in the k value of the low dielectric constant insulating film and the oxidation of the wiring in the element region are suppressed, so that the characteristics and reliability of the semiconductor device can be improved.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a sectional view showing a part thereof. A semiconductor device 10 shown in these drawings includes a semiconductor substrate (Si substrate or the like) 13 having a pad region 11 and an element region 12. The pad region 11 and the element region 12 are arranged in parallel in the plane of the semiconductor substrate 13. An element structure such as a transistor (not shown) is formed in the element region 12 of the semiconductor substrate 13.

  A wiring layer 16 having a low dielectric constant insulating film 14 and a metal wiring such as a Cu wiring 15 is formed on the semiconductor substrate 13. The wiring layer 16 is provided across the pad region 11 and the element region 12 of the semiconductor substrate 13. For the low dielectric constant insulating film 14, for example, a material having a relative dielectric constant (k value) of 3.0 or less is used. As such a low dielectric constant insulating film 14, a carbon-doped silicon oxide film (SiOC film), an MSQ film (methyl silsesquioxane film), an HSQ (hydrogen silsesquioxane) film, a PAE (poly-arylene-ether) film, These porous films and porous silica films are exemplified.

  The wiring layer 16 provided on the surface side of the semiconductor substrate 13 has a plurality of low dielectric constant insulating films 14, 14... And a Cu wiring 15 that is interlayer-insulated by the low dielectric constant insulating films 14, 14. is doing. The Cu wiring 15 is embedded, for example, in a wiring groove provided in the low dielectric constant insulating film 14 and is further electrically connected by a via formed in the low dielectric constant insulating film 14. As a result, the wiring layer 16 forms a multilayer wiring structure.

An electrode pad 17 made of, for example, an Al pad is formed on the wiring layer 16 in the pad region 11. The electrode pad 17 functions as a bonding pad. The surface of the wiring layer 16 excluding the exposed portion of the electrode pad (bonding pad) 17 is covered with a passivation film made of, for example, a silicon oxide (SiO _x ) film or a silicon nitride (SiN _x ) film. The electrode pad 17 is provided on the Cu wiring 15 in the pad region 11.

  The Cu wiring 15 in the wiring layer 16 in the pad region 11 is bonded when, for example, a bonding wire is connected to the electrode pad 17 for bonding or when a probe needle is pressed against the electrode pad 17 to test the semiconductor device. It functions only as a support portion that supports pressure, and may be omitted depending on circumstances. On the other hand, the Cu wiring 15 in the wiring layer 16 in the element region 12 forms a wiring network for an element structure (not shown) such as a transistor provided in the element region 12 of the semiconductor substrate 13.

  Here, as the electrode pad 17 is miniaturized as described above, the pressure applied to the electrode pad 17 during bonding or the like increases. The pressure applied to the electrode pad 17 mainly passes through the interface between the electrode pad (Al pad) 17 and the passivation film 18 as a crack or the like, and further to the interface between the Cu wiring 15 and the low dielectric constant insulating film 14 in the pad region 11. It is transmitted. Thus, the low dielectric constant insulating film 14 in the pad region 11 is easily damaged by the bonding pressure. Specifically, the low dielectric constant insulating film 14 in the pad region 11 is likely to be in a moisture absorbing state through a crack generated at each interface by the bonding pressure.

  When damage or moisture absorption (moisture) generated in the pad region 11 propagates through the low dielectric constant insulating film 14 to the element region 12, the k value of the low dielectric constant insulating film 14 in the element region 12 increases as described above. At the same time, the Cu wiring 15 in the element region 12 is oxidized to cause an increase in wiring resistance or disconnection. Therefore, in this embodiment, a moisture absorption preventing wall 19 that divides the pad region 11 and the element region 12 is provided in the wiring layer 16. In other words, the inside of the wiring layer 16 is divided into the pad region 11 and the element region 12 by the moisture absorption preventing wall 19.

  The moisture absorption preventing wall 19 is made of Cu, for example. The moisture absorption preventing wall 19 made of Cu can be formed simultaneously with the Cu wiring 15. For example, the moisture absorption preventing wall 19 that divides the wiring layer 16 can be obtained by embedding Cu in the grooves formed in the low dielectric constant insulating films 14 and stacking them in the thickness direction of the wiring layer 16. The constituent material of the moisture absorption preventing wall 19 is not limited to Cu, but the moisture absorption preventing wall 19 is preferably formed of Cu since it can be formed simultaneously with the Cu wiring 15 to suppress an increase in manufacturing cost.

  As described above, even if moisture that has entered the pad region 11 is diffused through the low dielectric constant insulating film 14, the moisture absorption preventing wall 19 provided between the pad region 11 and the element region 12 is merely oxidized, No further transmission to the element region 12 side. Therefore, damage due to bonding or the like can be suppressed only directly below the electrode pad 17, and an increase in the k value of the low dielectric constant insulating film 14 and the oxidation of the Cu wiring 15 in the element region 12 can be suppressed. As a result, the characteristics and reliability of the semiconductor device 10 can be kept good. Even when a metal wiring other than the Cu wiring 15 is applied, the oxidation suppression by the moisture absorption preventing wall 19 functions effectively.

  The moisture absorption prevention wall 19 is not limited to a single layer as shown in FIGS. 1 and 2, but may be provided in a multiple manner between the pad region 11 and the element region 12 as shown in FIG. 3, for example, as shown in FIG. . As shown in FIG. 3, by forming multiple moisture absorption prevention walls 19 in parallel between the pad region 11 and the element region 12, the moisture absorption state due to bonding damage is transmitted from the pad region 11 to the element region 12. Can be prevented more effectively.

  In the semiconductor device 10 of this embodiment, since the inside of the wiring layer 16 is divided into the pad region 11 and the element region 12 by the moisture absorption prevention wall 19 as described above, the wiring layer 16 extends from the electrode pad 17 to the element region 12. It cannot be connected by the internal Cu wiring 15. Therefore, a lead-out wiring 20 that connects the electrode pad 17 and the Cu wiring 15 in the element region 12 is provided in the passivation film 18. For example, an Al wiring is applied to the lead-out wiring 20 and is insulated by a moisture absorption prevention wall 19 made of, for example, Cu and a passivation film 18. Since the lead-out wiring 20 made of Al wiring can be formed at the same time as the electrode pad 17 made of Al pad, it is possible to suppress an increase in manufacturing cost and the like.

  Since the lead-out wiring 20 made of Al wiring or the like is surrounded by a passivation film 18 that is not easily damaged, damage due to pressure during bonding or the like is small. Even if the Al wiring is in contact with oxygen, the oxidation does not proceed after the formation of the Al oxide only on the Al surface, so the increase in wiring resistance does not proceed beyond a certain value, and disconnection may occur. Absent. Therefore, by combining the formation of the moisture absorption preventing wall 19 and the formation of the lead-out wiring 20 in the passivation film 18, the low dielectric constant insulating film 14 and the Cu film can be formed without impairing the original functions of the pad region 11 and the element region 12. It is possible to suppress the deterioration of the characteristics of the wiring layer 16 having the multilayer wiring structure constituted by the wiring 15 and the deterioration of the characteristics of the semiconductor device 10.

  A chip ring (seal ring) 21 is provided on the outer peripheral side of the semiconductor device 10 of this embodiment. Although the chip ring 21 is not shown in FIG. 2, Cu is embedded in a groove formed in each low dielectric constant insulating film 14, and these are stacked in the thickness direction of the wiring layer 16 and the passivation film 18. An Al ring is formed by embedding Al in the formed groove. The chip ring 21 is provided so as to surround the entire chip including the pad region 11 and the element region 12 as in the conventional semiconductor device.

  Here, when the moisture absorption preventing wall 19 is linearly provided between the pad region 11 and the element region 12 as shown in FIG. 1, the moisture absorption state generated in the low dielectric constant insulating film 14 in the pad region 11 is sufficient. It is preferable that both ends of the moisture absorption preventing wall 19 are in contact with the tip ring 21. As a result, the pad region 11 is isolated from the element region 12 without a gap. According to such a moisture absorption preventing wall 19, it is possible to effectively suppress the moisture absorption state generated in the pad region 11 based on bonding damage or the like from being transmitted to the element region 12.

  Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a plan view showing the configuration of the semiconductor device 30 according to the second embodiment of the present invention. Although the illustration of the cross-sectional structure of the semiconductor device 30 is omitted, the basic structure is as shown in FIG. The same parts as those of the first embodiment described above are denoted by the same reference numerals, and a part of the description is omitted.

  In the semiconductor device 30 shown in FIG. 4, the moisture absorption preventing wall 19 is formed so as to surround the pad region 11. In addition, the specific structure, forming material, and the like of the moisture absorption preventing wall 19 are as shown in the first embodiment. Thus, by surrounding the pad region 11 with the moisture absorption preventing wall 19, it is possible to obtain a more sufficient blocking state of the pad region 11 (partitioned state with the element region 12). The structure in which the pad region 11 is surrounded by the moisture absorption preventing wall 19 is effective when the pad region 11 and the element region 12 have one or more sides in contact with each other.

  Similar to the first embodiment, the semiconductor device 30 shown in FIG. 4 has a chip ring 21 provided so as to surround the entire chip including the pad region 11 and the element region 12. In other words, the pad region 11 is surrounded by the moisture absorption preventing wall 19, and the outside thereof is surrounded by the tip ring 21 together with the element region 12. Therefore, the entire semiconductor device 30 is protected against moisture entering from the external atmosphere or the like by the chip ring 21, and the element region 12 is protected from moisture entering the pad region 11 due to bonding damage or the like.

  Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a plan view showing a configuration of a semiconductor device 40 according to the third embodiment of the present invention, and FIG. 6 is a sectional view showing a part thereof. In addition, the same code | symbol is attached | subjected to the same part as 1st and 2nd embodiment mentioned above, and the description is partially omitted.

  In the semiconductor device 40 shown in FIGS. 5 and 6, the pad region 11 is formed outside the chip ring 21, and the pad region 11 itself is surrounded by a moisture absorption preventing wall 19. In addition, the specific structure, forming material, and the like of the moisture absorption preventing wall 19 are as shown in the first embodiment. The chip ring 21 has a Cu ring 21a and an Al ring 21b, but only the Cu ring 21a is formed on the side close to the pad region 11 in forming the Al lead wiring 20. As a result, the electrode pad 17 and the Cu wiring 15 in the element region 12 can be satisfactorily connected by the Al lead wiring 20.

  As described above, the pad region 11 is surrounded by the moisture absorption prevention wall 19 and the element region 12 is surrounded by the chip ring 21, so that the pad region 11 and the element region 12 are shielded from the external atmosphere and the pad region of the element region 12. 11 can be made compatible. In such a structure, for example, as shown in FIG. 7, the pad region 11 surrounded by the moisture absorption preventing wall 19 and the element region 12 surrounded by the first tip ring 21 are further surrounded by the second tip ring 22. But you can. By combining the moisture absorption preventing wall 19 and the multiple tip rings 21 and 22, the pad region 11 and the element region 12 can be protected to a higher degree.

  When the pad region 11 is formed outside the chip ring 21, in other words, when the chip ring 21 is formed so as to surround only the element region 12, the chip ring 21 also serves as a moisture absorption preventing wall as shown in FIG. be able to. That is, the tip ring 21 surrounding the element region 12 also serves as a moisture absorption preventing wall that divides the pad region 11 and the element region 12. Such a moisture absorption preventing wall can also protect the element region 12 from the moisture absorption state generated in the pad region 11 due to bonding damage. In this case, it is preferable to apply the second tip ring 22 that surrounds the entire semiconductor device 40 as shown in FIG.

  The semiconductor device of the present invention is not limited to the above-described embodiments, and can be applied to various semiconductor devices in which a wiring layer having a low dielectric constant insulating film is provided on the pad region and the element region. The specific structure of the semiconductor device can be variously modified as long as it satisfies the basic configuration of the present invention. Furthermore, the embodiments can be expanded or modified within the scope of the technical idea of the present invention, and the expanded and modified embodiments are also included in the technical scope of the present invention.

1 is a plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a part of the semiconductor device shown in FIG. 1. It is sectional drawing which shows the modification of the semiconductor device by 1st Embodiment. It is a top view which shows the structure of the semiconductor device by the 2nd Embodiment of this invention. It is a top view which shows the structure of the semiconductor device by the 3rd Embodiment of this invention. FIG. 6 is a cross-sectional view showing a part of the semiconductor device shown in FIG. 5. It is a top view which shows the modification of the semiconductor device by 3rd Embodiment. It is sectional drawing which shows the other modification of the semiconductor device by 3rd Embodiment. It is a top view which shows the other modification of the semiconductor device by 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10, 30, 40 ... Semiconductor device, 11 ... Pad area | region, 12 ... Element area | region, 13 ... Semiconductor substrate, 14 ... Low dielectric constant insulating film, 15 ... Cu wiring, 16 ... Wiring layer, 17 ... Electrode pad, 18 ... Passivation Membrane, 19 ... moisture absorption prevention wall, 20 ... lead-out wiring, 21, 22 ... tip ring.

Claims (5)

A semiconductor substrate having an element region and a pad region arranged in parallel with the element region;
A wiring layer provided on the semiconductor substrate and having a low dielectric constant insulating film;
A moisture absorption preventing wall provided to divide the wiring layer into the element region and the pad region;
A passivation film provided to cover the wiring layer;
An electrode pad formed on the wiring layer in the pad region and electrically connected to the wiring in the wiring layer in the element region by a lead wiring insulated by the passivation film. A semiconductor device. The semiconductor device according to claim 1,
The wiring in the wiring layer and the moisture absorption preventing wall are made of Cu. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the electrode pad and the lead-out wiring are made of Al. 4. The semiconductor device according to claim 1, wherein:
The moisture absorption preventing wall is provided between the element region and the pad region, and both ends thereof are in contact with a chip ring provided so as to surround the element region and the pad region. Semiconductor device. 4. The semiconductor device according to claim 1, wherein:
The moisture absorption preventing wall is provided so as to surround the pad region, and a chip ring is provided so as to surround only the element region and at least one of the element region and the entire pad region. Semiconductor device.

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