JP2007334299A - Display driver, electrooptical device, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display driver and the like with which the lower electric power consumption is achieved by reusing charges, wherein the lower electric power consumption is made preferential or a lower cost is made preferential with simple configuration. <P>SOLUTION: The display driver includes: a switch for accummulating counter electrode charge disposed between a first capacitive element connection node and a counter electrode voltage output node; a switch for accummulating source charge disposed between a second capacitive element connection node and a source voltage output node; a node short-circuiting switch disposed between the counter electrode voltage output node and the source voltage output node; a common line electrically connected at one end to the switch for accumulating source charge while electrically connected to the source voltage output node; a first and second source short-circuiting switches disposed between each of the source output nodes and the common line; and a transistor for discharge connected to the common line. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display driver, an electro-optical device, and an electronic apparatus.

  Conventionally, as a liquid crystal display (LCD) panel (display panel in a broad sense, an electro-optical device in a broad sense) used for an electronic device such as a cellular phone, a simple matrix type LCD panel and a thin film transistor ( 2. Description of the Related Art An active matrix type LCD panel using a switching element such as a thin film transistor (hereinafter abbreviated as TFT) is known.

  The simple matrix method is easier to reduce power consumption than the active matrix method, but it is difficult to increase the number of colors and display a moving image. On the other hand, the active matrix method is suitable for multicolor and moving image display, but it is difficult to reduce power consumption.

  In a simple matrix type LCD panel and an active matrix type LCD panel, driving is performed so that an applied voltage to liquid crystal (electro-optical material in a broad sense) constituting a pixel is an alternating current. As such AC driving methods, line inversion driving and field inversion driving (frame inversion driving) are known. In line inversion driving, driving is performed so that the polarity of the voltage applied to the liquid crystal is inverted every one or more scanning lines. In the field inversion driving, driving is performed so that the polarity of the voltage applied to the liquid crystal is inverted for each field (each frame).

  At that time, the voltage level applied to the pixel electrode is lowered by changing the counter electrode voltage (common voltage) supplied to the counter electrode (common electrode) facing the pixel electrode constituting the pixel in accordance with the inversion drive timing. Can be made.

When such AC driving is performed, an increase in power consumption accompanying charging / discharging of the liquid crystal is caused. Therefore, for example, in Patent Document 1, during inversion driving, the electric charge accumulated in the liquid crystal is initialized by short-circuiting the two electrodes sandwiching the liquid crystal, and the transition is made to the intermediate voltage of the voltage before the short-circuiting of the electrode, thereby reducing the consumption. A technique for achieving the above is disclosed. In Patent Document 2, a counter electrode is provided by applying a precharge potential to a source line in a first precharge period before writing to a pixel electrode and a second precharge period before switching of the counter electrode voltage. A technique for reducing power consumption by suppressing potential fluctuation of a source line at the time of voltage switching is disclosed.
JP 2002-244622 A JP 2004-354758 A

  However, the techniques disclosed in Patent Document 1 and Patent Document 2 have a problem that the power consumption reduction effect depends on the voltage applied to the source line. Therefore, there may be a case where the effect of reducing the charge amount for charging and discharging the counter electrode whose polarity is reversed cannot be expected so much. Further, in the technique disclosed in Patent Document 1, depending on the relationship between the voltage applied to the source line and the polarity of the counter electrode voltage, the amount of charge to be charged / discharged can be reduced by short-circuiting the two electrodes sandwiching the liquid crystal. There is a problem that the effect of lowering power consumption may be diminished.

  Therefore, when reusing the charge once supplied, it is desirable that the source line and the counter electrode can be driven while reliably reducing power consumption with a simple configuration.

  On the other hand, depending on the application field of the display driver, there is a case where priority should be given to reducing the chip size and mounting area of the display driver, etc. at the expense of a certain power consumption reduction effect. For example, this is a case where a customer (electronic device manufacturer) applies the display driver or the like to a product that places top priority on cost reduction of the display driver and the LCD panel including the display driver.

  Thus, it is desirable to provide a display driver or the like that can prioritize low power consumption or prioritize cost reduction according to the customer. In other words, with a simple configuration, we pursue low power consumption at the expense of a certain cost reduction effect (priority for low power consumption), or pursue cost reduction at the expense of a certain power consumption reduction effect. It is desirable to be able to (prioritize cost reduction). If such a display driver or the like can be provided, it means that one type of display driver satisfies various user requirements, and as a result, the manufacturing cost can be further reduced.

  The present invention has been made in view of the technical problems as described above. The object of the present invention is to reduce power consumption by reusing electric charges while reducing power consumption with a simple configuration. It is an object of the present invention to provide a display driver, an electro-optical device, and an electronic apparatus that can give priority to cost reduction.

In order to solve the above problems, the present invention
A display driver for driving an electro-optical device,
A first capacitor element connection node to which one end of the first capacitor element can be connected and a counter electrode voltage output node to which a voltage of a counter electrode facing the pixel electrode of the electro-optical device is supplied via an electro-optical material A counter electrode charge storage switch provided therebetween;
A source charge storage switch provided between a second capacitor element connection node to which one end of the second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied;
The present invention relates to a display driver including a node short-circuit switch provided between the common electrode voltage output node and the source voltage output node.

In the display driver according to the present invention,
In the first mode of operation,
With the common electrode charge storage switch and the source charge storage switch set in a non-conductive state, the node short circuit switch is once set in a conductive state, and then the common electrode voltage is supplied to the common electrode voltage output node. Then, the counter electrode can be driven, and a voltage corresponding to display data can be supplied to the source line to drive the source line.

In the display driver according to the present invention,
In the second mode of operation,
With the node short-circuit switch set to a non-conductive state,
After the common electrode voltage output node and the first capacitor element connection node are electrically connected once by the common electrode charge storage switch, the common electrode voltage output node and the first capacitor node are electrically connected by the common electrode charge storage switch. Driving the counter electrode by supplying the counter electrode voltage to the counter electrode voltage output node in a state where the capacitor element connection node is electrically cut off,
After the source voltage output node and the second capacitor element connection node are electrically connected once by the source charge storage switch, the source voltage output node and the second capacitor element are connected by the source charge storage switch. In a state where the connection node is electrically disconnected, the source line can be driven by supplying a voltage corresponding to display data to the source line.

  In any one of the above inventions, a configuration is provided in which one end of the first capacitive element and the common electrode voltage output node can be set to the same potential via the common electrode charge storage switch. In the present invention, a configuration in which one end of the second capacitor element and the source voltage output node can be set to the same potential via the source charge storage switch is provided. Furthermore, in the present invention, a configuration is provided in which the common electrode voltage output node and the source voltage output node can be set to the same potential. In other words, it is not necessary to charge / discharge from the power supply circuit when setting the same potential, and it is only necessary to charge / discharge the charge from the power supply circuit again and set the desired potential after setting the same potential. Can be reduced.

  Thus, any of charge reuse control of the counter electrode and the source line using the first and second capacitive elements and charge reuse control for setting the counter electrode voltage output node and the source voltage output node to the same potential. Can be realized with a simple configuration. Accordingly, it is possible to provide a display driver that can reduce power consumption by reusing charges while giving priority to lower power consumption or lowering cost with a simple configuration.

In the display driver according to the present invention,
A period for electrically connecting the source voltage output node and the second capacitor element connection node, and a period for electrically connecting the counter electrode voltage output node and the first capacitor element connection node, It may be duplicated.

  According to the present invention, the amount of charge to be supplied from the outside can be reduced when the source output is changed and when the counter electrode voltage is changed, so that further reduction in power consumption can be achieved.

In the display driver according to the present invention,
An operation mode setting register in which control data corresponding to the first or second operation mode is set;
An operation mode corresponding to the control data may be designated.

In the display driver according to the present invention,
Including external setting terminals,
An operation mode corresponding to a signal state supplied to the external setting terminal may be designated.

  According to any one of the above-described inventions, it is possible to provide a display driver that can switch either one of the first and second operation modes with an even simpler configuration.

In the display driver according to the present invention,
A common line electrically connected to the source voltage output node and having one end electrically connected to the source charge storage switch;
A first source short-circuit switch provided between a first source output node to which an output voltage to the first source line of the electro-optical device is supplied and the shared line;
A second source short-circuit switch provided between the second source output node to which an output voltage to the second source line of the electro-optical device is supplied and the shared line;
A discharge transistor connected to the common line,
The discharging transistor is
It may be shared by the discharge of the first and second source lines.

  According to the present invention, it is possible to discharge a plurality of source lines with a simple configuration and prevent deterioration of a pixel.

In the display driver according to the present invention,
In the selection period of the pixel electrode of the electro-optical device, the first and second source lines can be discharged by the discharge transistor in a state where the first and second source short-circuit switches are set in a conductive state. .

  According to the present invention, display off control can be performed with a simple configuration without applying a predetermined off voltage.

In the display driver according to the present invention,
A counter electrode voltage generating circuit for generating the counter electrode voltage;
A source line driving circuit for driving the first or second source line of the electro-optical device based on display data,
In the first operation mode,
After setting the outputs of the source line driving circuit and the common electrode voltage generation circuit to a high impedance state and electrically connecting the source voltage output node and the common electrode voltage output node, the source voltage output node and In a state where the counter electrode voltage output node is electrically disconnected,
The source line driving circuit can supply a voltage corresponding to display data to the first or second source line, and the counter electrode voltage generation circuit can supply the counter electrode voltage to the counter electrode. .

In the display driver according to the present invention,
In the second operation mode,
The first or second source output node and the second capacitor element connection node are electrically connected in a state where the output of the source line driving circuit is set to a high impedance state, and then the first or second source output node is electrically connected. The source line driving circuit supplies a voltage corresponding to display data to the first or second source line in a state where the two source output nodes and the second capacitor element connection node are electrically cut off. ,
With the output of the common electrode voltage generation circuit set to a high impedance state, the common electrode voltage output node and the first capacitor element connection node are electrically connected by the common electrode charge storage switch, The counter electrode voltage generation circuit can supply the counter electrode voltage to the counter electrode in a state where the counter electrode voltage output node and the first capacitor element connection node are electrically cut off.

In the display driver according to the present invention,
A demultiplexer for separating the time-divided voltage at each source output node into a plurality of output voltages;
Each output voltage of the plurality of output voltages can be supplied to each source line of the electro-optical device.

  The present invention can be applied to driving an electro-optical device of a type in which data signals are time-division multiplexed.

The present invention also provides
Multiple source lines,
Multiple gate lines,
A plurality of pixel electrodes in which each pixel electrode is specified by each gate line and each source line;
A counter electrode facing the plurality of pixel electrodes;
A common electrode charge storage switch provided between a first capacitive element connection node to which one end of the first capacitive element can be connected and a common electrode voltage output node to which a common electrode voltage applied to the common electrode is supplied When,
A common line electrically connected to a second capacitor element connection node to which one end of the second capacitor element can be connected;
A node short-circuit switch provided between the common electrode voltage output node and the shared line;
A first source short circuit switch provided between a first source output node to which an output voltage to the first source line of the plurality of source lines is supplied and the shared line;
A second source short-circuit switch provided between a second source output node to which an output voltage to a second source line of the plurality of source lines is supplied and the shared line;
The present invention relates to an electro-optical device including a source charge storage switch provided between the shared line and the second capacitor element connection node.

In the electro-optical device according to the invention,
In the first mode of operation,
With the common electrode charge storage switch and the source charge storage switch set in a non-conductive state, the node short circuit switch is once set in a conductive state, and then the common electrode voltage is supplied to the common electrode voltage output node. Then, the counter electrode can be driven, and a voltage corresponding to display data can be supplied to the first or second source line to drive the first or second source line.

In the electro-optical device according to the invention,
In the second mode of operation,
With the node short-circuit switch set to a non-conductive state,
After the common electrode voltage output node and the first capacitor element connection node are electrically connected once by the common electrode charge storage switch, the common electrode voltage output node and the first capacitor node are electrically connected by the common electrode charge storage switch. Driving the counter electrode by supplying the counter electrode voltage to the counter electrode voltage output node in a state where the capacitor element connection node is electrically cut off,
After the source charge storage switch electrically connects the shared line and the second capacitor element connection node, the source charge storage switch connects the shared line and the second capacitor element connection node. The first or second source line can be driven by supplying a voltage corresponding to display data to the first or second source line in an electrically cut-off state.

In the display driver according to the present invention,
A period in which the common electrode voltage output node and the first capacitor element connection node are electrically connected, and the first or second source output node and the second capacitor element connection node are electrically connected. The period to make may overlap.

In the display driver according to the present invention,
A discharge transistor connected to the common line,
The discharging transistor is
It may be shared by the discharge of the first and second source lines.

In the display driver according to the present invention,
In the selection period of the pixel electrode, the first and second source lines may be discharged by the discharging transistor in a state where the first and second source short-circuit switches are set in a conductive state.

In the display driver according to the present invention,
A demultiplexer for separating the time-divided voltage at each source output node into a plurality of output voltages;
Each output voltage of the plurality of output voltages may be supplied to each source line.

The present invention also provides
The present invention relates to an electro-optical device including any one of the display drivers described above.

  According to any one of the above-described inventions, it is possible to provide an electro-optical device that can reduce power consumption by reusing electric charges, and can prioritize lower power consumption or lower cost with a simple configuration. .

The present invention also provides
The present invention relates to an electronic apparatus including any of the electro-optical devices described above.

  According to the present invention, it is possible to provide an electronic device that can reduce electric power consumption by reusing electric charges and can prioritize lower electric power consumption or lower cost with a simple configuration. Become.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Device FIG. 1 shows an example of a block diagram of a liquid crystal device of this embodiment.

  The liquid crystal device 10 (liquid crystal display device; display device in a broad sense) includes a display panel 12 (LCD (Liquid Crystal Display) panel in a narrow sense), a source line drive circuit 20 (a source driver in a narrow sense), and a gate line drive circuit 30. (Gate driver in a narrow sense), a display controller 40, and a power supply circuit 50 are included. Note that it is not necessary to include all these circuit blocks in the liquid crystal device 10, and some of the circuit blocks may be omitted.

  Here, in the display panel 12 (electro-optical device in a broad sense), a plurality of gate lines (scanning lines), a plurality of source lines (data lines), and each pixel electrode are specified by each gate line and each source line. A plurality of pixel electrodes are included. In this case, an active matrix liquid crystal device can be configured by connecting a thin film transistor TFT (Thin Film Transistor, switching element in a broad sense) to a source line and connecting a pixel electrode to the TFT.

More specifically, the display panel 12 is formed on an active matrix substrate (for example, a glass substrate). In this active matrix substrate, a plurality of gate lines G _{1 to} G _M (M is a natural number of 2 or more) arranged in the Y direction and extending in the X direction, and a plurality of sources arranged in the X direction and extending in the Y direction, respectively. Lines S _{1 to} S _N (N is a natural number of 2 or more) are arranged. The thin film transistor TFT _KL (switching in a broad sense) is provided at a position corresponding to the intersection of the gate line G _K (1 ≦ K ≦ M, K is a natural number) and the source line S _L (1 ≦ L ≦ N, L is a natural number). Element).

The gate electrode of the thin film transistor TFT _KL is connected with the gate line _{G K,} a source electrode of the _{thin film transistor TFT KL} is connected with the source line _{S L,} the drain electrode of the _{thin film transistor TFT KL} is connected with a pixel electrode _{PE KL.} A liquid crystal capacitor CL _KL (liquid crystal element) is _disposed between the pixel electrode PE _KL and the counter electrode CE (common electrode, common electrode) opposed to the pixel electrode PE _KL with the liquid crystal (electro-optical material in a broad sense) interposed therebetween. In addition, an auxiliary capacitor CS _KL is formed. Then, liquid crystal is formed between the active matrix substrate on which the TFT _KL , the pixel electrode PE _{KL, and the} like are formed and the counter substrate on which the counter electrode CE is formed, and the pixel electrode PE _KL , the counter electrode CE, The transmittance of the pixel is changed in accordance with the applied voltage between.

  Note that the voltage level (high potential side voltage VCOMH, low potential side voltage VCOML) of the counter electrode voltage VCOM applied to the counter electrode CE is generated by a counter electrode voltage generation circuit included in the power supply circuit 50. Further, the counter electrode CE may be formed in a strip shape so as to correspond to each gate line without being formed on the entire surface of the counter substrate.

The source line drive circuit 20 drives the source lines S _{1 to} S _N of the display panel 12 based on the display data. On the other hand, the gate line driver circuit 30 scans the gate lines _G 1 ~G _M of the display panel 12 (sequential drive).

  The display controller 40 controls the source line driving circuit 20, the gate line driving circuit 30, and the power supply circuit 50 according to the contents set by a host such as a central processing unit (CPU) (not shown). More specifically, the display controller 40 sets, for example, an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source line drive circuit 20 and the gate line drive circuit 30 to supply power. For the circuit 50, the polarity inversion timing of the voltage level of the common electrode voltage VCOM applied to the common electrode CE is controlled.

  The power supply circuit 50 generates various voltage levels (gradation voltages) necessary for driving the display panel 12 and the voltage level of the counter electrode voltage VCOM of the counter electrode CE based on a reference voltage supplied from the outside.

  In the liquid crystal device 10 having such a configuration, the source line driving circuit 20, the gate line driving circuit 30, and the power supply circuit 50 cooperate with each other based on display data supplied from outside under the control of the display controller 40. 12 is driven.

  In FIG. 1, the display driver 60 can be configured as a semiconductor device (integrated circuit, IC) by integrating the source line driver circuit 20, the gate line driver circuit 30, and the power supply circuit 50. The display driver 60 in FIG. 1 may have a configuration in which the gate line driving circuit 30 is omitted. In FIG. 1, the display driver 60 in the present embodiment may be configured to include the source line driving circuit 20 and the common electrode voltage generation circuit of the power supply circuit 50.

Such a display driver 60 further includes a plurality of source output switching circuits SSW _{1 to} SSW _{N in} which each source output switching circuit is provided between the source line and an output buffer that drives the source line. The output of each output buffer is connected to the first terminal of each source output switching circuit. Each source line is connected to the second terminal of each source output switching circuit. One end of the shared line COL is connected to the third terminal of each source output switching circuit. The plurality of source output switching circuits SSW _{1 to} SSW _N are simultaneously turned on and off by a common control signal (not shown).

  The display driver 60 can include a first capacitor element connection terminal TL1 and a counter electrode charge storage switch VSW. The common electrode charge storage switch VSW is connected between the output of the common electrode voltage generation circuit of the power supply circuit 50 (the common electrode voltage output node to which the common electrode voltage VCOM is supplied) and the first capacitor element connection terminal TL1. Provided. One end of the first capacitor element CCV is electrically connected to the first capacitor element connection terminal TL1. A predetermined power supply voltage (for example, the system ground power supply voltage VSS) is supplied to the other end of the first capacitor element CCV. In FIG. 1, the first capacitor element CCV is provided outside the display driver 60, but the first capacitor element CCV may be built in the display driver 60.

Further, the display driver 60 can include a second capacitor element connection terminal TL2 for storing source charge and a source charge storing switch CSW. The source charge storage switch CSW is provided between the other end of the shared line COL and the second capacitor element connection terminal TL2. When the source charge storage switch CSW is set to the conductive state, each of the source output switching circuits SSW _{1 to} SSW _N electrically connects the source lines S _{1 to} S _N and the shared line COL.

  It can be said that the shared line COL includes a second capacitor element connection node. One end of the second capacitor element CCS is electrically connected to the second capacitor element connection terminal TL2. A predetermined power supply voltage (for example, the system ground power supply voltage VSS) is supplied to the other end of the second capacitor element CCS. In FIG. 1, the second capacitor element CCS is provided outside the display driver 60, but the second capacitor element CCS may be built in the display driver 60.

  When the common electrode charge storage switch VSW is set to the conductive state, the output of the common electrode voltage generation circuit of the power supply circuit 50 is set to the high impedance state.

  Further, the display driver 60 can include a node short-circuit switch HSW. The node short-circuit switch HSW is provided between the common line COL and the common electrode voltage output node.

The display driver 60 recycles the charge from the counter electrode CE or the source lines S _{1 to} S _N using the counter electrode charge storage switch VSW, the source charge storage switch CSW, and the node short circuit switch HSW according to the operation mode. Use. More specifically, in an operation mode in which charge reuse is performed by on / off control of the node short-circuit switch HSW, the display driver 60 performs control while keeping the common electrode charge storage switch VSW in a non-conductive state. In the operation mode in which charge reuse is performed by on / off control of the common electrode charge storage switch VSW and the source charge storage switch CSW, the display driver 60 controls the node short-circuit switch HSW while being in a non-conductive state.

  In FIG. 1, the liquid crystal device 10 includes the display controller 40, but the display controller 40 may be provided outside the liquid crystal device 10. Alternatively, the host may be included in the liquid crystal device 10 together with the display controller 40. Further, part or all of the source line driver circuit 20, the gate line driver circuit 30, the display controller 40, and the power supply circuit 50 may be formed on the display panel 12.

  FIG. 2 is a block diagram showing another configuration example of the liquid crystal device according to this embodiment.

  In FIG. 2, a display driver 60 including a source line driving circuit 20, a gate line driving circuit 30, and a power supply circuit 50 is formed on the display panel 12 (panel substrate). As described above, the display panel 12 includes a plurality of gate lines, a plurality of source lines, a plurality of pixels (pixel electrodes) specified by the gate lines of the plurality of gate lines and the source lines of the plurality of source lines. A source line driving circuit for driving a plurality of source lines and a gate line driving circuit for scanning the plurality of gate lines can be included. A plurality of pixels are formed in the pixel formation region 44 of the display panel 12. Each pixel can include a TFT having a source connected to the source and a gate line connected to the gate, and a pixel electrode connected to the drain of the TFT.

  In FIG. 2, at least one of the gate line driving circuit 30 and the power supply circuit 50 may be omitted on the display panel 12.

  In FIG. 1 or FIG. 2, the display driver 60 may incorporate the display controller 40. Alternatively, in FIG. 1 or FIG. 2, the display driver 60 may be a semiconductor device in which one of the source line driver circuit 20 and the gate line driver circuit 30 and the power supply circuit 50 are integrated.

2. Display Driver Next, the main components of the display driver 60 shown in FIG. 1 or 2 will be described.

  FIG. 3 is a block diagram showing a configuration example of the source line driver circuit 20 shown in FIG.

  The source line driving circuit 20 includes a shift register 22, line latches 24 and 26, a DAC 28 (Digital-to-Analog Converter) (data voltage generation circuit in a broad sense), and an output buffer 29.

  The shift register 22 includes a plurality of flip-flops provided corresponding to each source line and sequentially connected. When the shift register 22 holds the enable input / output signal EIO in synchronization with the clock signal CLK, the shift register 22 sequentially shifts the enable input / output signal EIO to the adjacent flip-flops in synchronization with the clock signal CLK.

  For example, display data (DIO) is input to the line latch 24 in units of 18 bits (6 bits (display data) × 3 (RGB colors)). The line latch 24 latches the display data (DIO) in synchronization with the enable input / output signal EIO that is sequentially shifted by each flip-flop of the shift register 22.

  The line latch 26 latches the display data of one horizontal scanning unit latched by the line latch 24 in synchronization with the horizontal synchronization signal LP supplied from the display controller 40.

  The reference voltage generation circuit 27 generates 64 types of reference voltages. The 64 types of reference voltages generated by the reference voltage generation circuit 27 are supplied to the DAC 28.

  A DAC (data voltage generation circuit) 28 generates an analog data voltage to be supplied to each source line. Specifically, the DAC 28 selects one of the reference voltages from the reference voltage generation circuit 27 based on the digital display data from the line latch 26, and outputs an analog data voltage corresponding to the digital display data. .

The output buffer 29 buffers the data voltage from the DAC 28 and outputs it to the source line to drive the source line. Specifically, the output buffer 29 includes operational amplifier circuit blocks OPC _{1 to} OPC _N each including a voltage follower-connected operational amplifier circuit provided for each source line, and these operational amplifier circuit blocks are connected to the DAC 28. Is converted to impedance and output to each source line.

  In FIG. 3, a configuration is adopted in which digital display data is converted from digital to analog and output to the source line via the output buffer 29. However, an analog video signal is sampled and held, and output buffer is provided. A configuration of outputting to the source line via 29 can also be adopted.

  FIG. 4 shows a configuration example of the reference voltage generation circuit 27, the DAC 28, and the output buffer 29 of FIG. In FIG. 4, the display data is 6-bit data D0 to D5, and the inverted data of the data of each bit is indicated as XD0 to XD5. In FIG. 4, the same parts as those in FIG.

The reference voltage generation circuit 27 divides the voltages VDDH and VSSH generated by the power supply circuit 50 by resistance and generates 64 types of reference voltages. Each reference voltage corresponds to each gradation value represented by 6-bit display data. Each reference voltage is commonly supplied to the source lines S _{1 to} S _N.

The DAC 28 includes a decoder provided for each source line, and each decoder outputs a reference voltage corresponding to display data to the operational amplifier circuit blocks OPC _{1 to} OPC _N.

  3 and 4 show the configuration example in the case where the display data is supplied line by line, the display driver 60 may incorporate a display memory for storing display data for at least one screen.

  FIG. 5 shows a configuration example of the gate line driving circuit 30 of FIG. 1 or FIG.

  The gate line driving circuit 30 includes a shift register 32, a level shifter 34, and an output buffer 36.

  The shift register 32 includes a plurality of flip-flops provided corresponding to the gate lines and sequentially connected. When the shift register 32 holds the enable input / output signal EIO in the flip-flop in synchronization with the clock signal CLK, the shift register 32 sequentially shifts the enable input / output signal EIO to the adjacent flip-flop in synchronization with the clock signal CLK. The enable input / output signal EIO input here is a vertical synchronization signal supplied from the display controller 40.

  The level shifter 34 shifts the voltage level from the shift register 32 to a voltage level corresponding to the liquid crystal element of the display panel 12 and the transistor capability of the TFT. Since this voltage level requires a high voltage level, a high breakdown voltage process different from other logic circuit units is used.

  The output buffer 36 buffers the scanning voltage shifted by the level shifter 34 and outputs it to the gate line to drive the gate line.

  FIG. 6 shows a configuration example of the power supply circuit 50 of FIG. 1 or FIG.

  The power supply circuit 50 includes a positive direction double boosting circuit 52, a scanning voltage generation circuit 54, and a counter electrode voltage generation circuit 56. The power supply circuit 50 is supplied with a system ground power supply voltage VSS and a system power supply voltage VDD.

  The system ground power supply voltage VSS and the system power supply voltage VDD are supplied to the positive direction double booster circuit 52. Then, the positive direction double boosting circuit 52 generates a power supply voltage VDDHS obtained by boosting the system power supply voltage VDD twice in the positive direction on the basis of the system ground power supply voltage VSS. That is, the positive direction double boosting circuit 52 boosts the voltage difference between the system ground power supply voltage VSS and the system power supply voltage VDD twice. Such a positive direction double boosting circuit 52 can be constituted by a known charge pump circuit. The power supply voltage VDDHS is supplied to the source line drive circuit 20, the scan voltage generation circuit 54, and the counter electrode voltage generation circuit 56. It is desirable that the positive direction double booster circuit 52 outputs a power supply voltage VDDHS obtained by boosting the system power supply voltage VDD twice in the positive direction by adjusting the voltage level with a regulator after boosting at a boosting factor of 2 or more. .

  The scan voltage generation circuit 54 is supplied with the system ground power supply voltage VSS and the power supply voltage VDDHS. The scan voltage generation circuit 54 generates a scan voltage. The scanning voltage is a voltage applied to the gate line selected by the gate line driving circuit 30. The high potential side voltage of this scanning voltage is VDDHG, and the low potential side voltage is VEE.

  The counter electrode voltage generation circuit 56 generates a counter electrode voltage VCOM. The common electrode voltage generation circuit 56 outputs the high potential side voltage VCOMH or the low potential side voltage VCOML as the common electrode voltage VCOM based on the polarity inversion signal POL. The polarity inversion signal POL is generated by the display controller 40 in accordance with the polarity inversion timing.

  FIG. 7 shows an example of the drive waveform of the display panel 12 shown in FIG.

  A gradation voltage DLV corresponding to the gradation value of the display data is applied to the source line. In FIG. 7, a gradation voltage DLV having an amplitude of 5 V is applied with respect to the system ground power supply voltage VSS (= 0 V).

  A scanning voltage GLV of a low potential side voltage VEE (= −10 V) when not selected and a high potential side voltage VDDHG (= 15 V) when selected is applied to the gate line.

  The counter electrode CE is applied with the counter electrode voltage VCOM of the high potential side voltage VCOMH (= 3 V) and the low potential side voltage VCOML (= −2 V). The polarity of the voltage level of the counter electrode voltage VCOM with respect to a given voltage is inverted in accordance with the polarity inversion timing. FIG. 7 shows the waveform of the counter electrode voltage VCOM during so-called scanning line inversion driving. In accordance with the polarity inversion timing, the polarity of the grayscale voltage DLV of the source line is also inverted with reference to a given voltage.

  By the way, the liquid crystal element has a property that it deteriorates when a DC voltage is applied for a long time. For this reason, a driving method is required in which the polarity of the voltage applied to the liquid crystal element is inverted every predetermined period. Such driving methods include frame inversion driving, scanning (gate) line inversion driving, data (source) line inversion driving, dot inversion driving, and the like.

  Among these, the frame inversion drive has a disadvantage that the image quality is not so good although the power consumption is low. Data line inversion driving and dot inversion driving have good image quality, but have the disadvantage that a high voltage is required to drive the display panel.

  In this embodiment, for example, scanning line inversion driving is employed. In this scanning line inversion drive, the polarity of the voltage applied to the liquid crystal element is inverted every scanning period (every gate line). For example, a positive voltage is applied to the liquid crystal element in the first scanning period (gate line), a negative voltage is applied in the second scanning period, and a positive voltage is applied in the third scanning period. The On the other hand, in the next frame, a negative voltage is applied to the liquid crystal element in the first scanning period, a positive voltage is applied in the second scanning period, and a negative voltage is applied in the third scanning period. Voltage is applied.

  In this scan line inversion drive, the voltage level of the counter electrode voltage VCOM of the counter electrode CE is inverted every scan period.

  More specifically, as shown in FIG. 8, the voltage level of the common electrode voltage VCOM becomes the low potential side voltage VCOML in the positive period T1 (first period), and in the negative period T2 (second period). The high potential side voltage VCOMH is obtained. The polarity of the gradation voltage applied to the source line in accordance with this timing is also reversed. The low potential side voltage VCOML is a voltage level obtained by inverting the polarity of the high potential side voltage VCOMH with reference to a given voltage level.

  Here, the positive period T1 is a period in which the voltage level of the pixel electrode to which the grayscale voltage of the source line is supplied is higher than the voltage level of the counter electrode CE. In this period T1, a positive voltage is applied to the liquid crystal element. On the other hand, the negative period T2 is a period in which the voltage level of the pixel electrode to which the grayscale voltage of the source line is supplied is lower than the voltage level of the counter electrode CE. In this period T2, a negative voltage is applied to the liquid crystal element.

  Thus, by reversing the polarity of the counter electrode voltage VCOM, the voltage necessary for driving the display panel can be lowered. As a result, the withstand voltage of the drive circuit can be lowered, and the manufacturing process of the drive circuit can be simplified and the cost can be reduced.

3. Principle Configuration In this embodiment, the display driver 60 or the LCD panel 12 includes an operation mode register (not shown), and controls charge reuse in an operation mode corresponding to control data of the operation mode register. Alternatively, the display driver 60 or the LCD panel 12 includes an operation mode setting terminal (external setting terminal) (not shown), and controls charge reuse in an operation mode corresponding to a signal state given to the operation mode setting terminal from the outside. .

3.1 First Operation Mode FIG. 9 shows a principle configuration diagram in the first operation mode of the liquid crystal device 10 of the present embodiment.

In FIG. 9, the same parts as those in FIG. 1 or FIG. In Figure 9, the gate lines G _K and the electrical equivalent circuit of a pixel provided at the intersection of the source line S _L, the gate line G _{K + 1} and the source line S _{L + 1} of the electrical equivalent circuit of a pixel provided at the intersection The same applies to the electrical equivalent circuits of other pixels. FIG. 9 shows only the source output switching circuit of the source line driving circuit 20, the source charge storage switch CSW, and the counter electrode charge storage switch VSW.

  FIG. 10 shows a waveform diagram of an operation example of the liquid crystal device 10 of FIG.

FIG. 10 shows changes in the potentials of the gate lines G _K , G _{K + 1} , the source line _SL, and the counter electrode CE, but the same applies to other gate lines and source lines. 10, a selection period of the pixel that is connected with the gate line G _K within one horizontal scanning period (1H), the scan voltage is applied to the gate line G _K, the selection of pixels is connected with the gate line G _{K + 1} A scanning voltage is applied to the gate line _{GK + 1} within one horizontal scanning period. Each horizontal scanning period includes a charge recycling period provided in the first half part and a driving period provided in the second half part. When the transition from the charge recycle period to the drive period and the transition from the drive period to the charge recycle period, switching control of the source output switching circuits SSW _L and SSW _{L + 1} and the node short circuit switch HSW is performed.

In the charge recycle period (TT1), in the source output switching circuits SSW _L and SSW _{L + 1} , the source lines S _L and S _{L + 1} are electrically connected to the shared line COL including the second capacitor element connection node, respectively. Further, the node short circuit switch HSW is turned on while the source charge storage switch CSW and the common electrode charge storage switch VSW are in a non-conductive state, and the common line COL is supplied with the output of the common electrode voltage generation circuit (the common electrode voltage VCOM is supplied). The common electrode voltage output node). Therefore, in the charge recycling period, the shared line COL and the source lines S _L and S _{L + 1} are electrically connected, and the source lines S _L and S _{L + 1} and the counter electrode CE have the same potential, and follow the law of charge conservation. The charge accumulated in the parasitic capacitances of the source lines S _L and S _{L + 1} supplements the counter electrode CE, or the charges accumulated in the counter electrode CE supplements the parasitic capacitances of the source lines S _L and S _{L + 1.} Or That is, in the charge recycle period, the potentials of the source line and the counter electrode CE are changed without replenishing charges from the power supply circuit 50 at all.

Next, in the drive period (TT2) after the charge recycle period, in the source output switching circuits SSW _L and SSW _{L + 1} , the source lines S _L and S _{L + 1} are electrically connected to the output of the output buffer of the source line drive circuit 20, respectively. Connected to. Further, the source charge storage switch CSW and the counter electrode charge storage switch VSW remain set in a non-conductive state. Then, the node short-circuit switch HSW is set to a non-conductive state. Therefore, in the driving period, the source lines S _L and S _{L + 1} are driven by the output buffer of the source line driving circuit 20. At this time, the output buffer of the source line driver circuit 20 charges and discharges the charges of the source line until each source line becomes a potential corresponding to each display data with reference to the potential after the change in the charge reuse period TT1. . Therefore, in the driving period after the charge recycling period, the source line voltage to be changed by the output buffer of the source line driving circuit 20 is often low. That is, based on the potential of the source line in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection period of pixels connected to the gate line _GK) is used as it is. 10), it is necessary for the output buffer of the source line driver circuit 20 to charge / discharge the charge of the source line by ΔVs01 as shown in FIG. On the other hand, by providing the above-described charge recycling period, the output buffer of the source line driver circuit 20 may charge and discharge the source line charges by ΔVs02 (ΔVs02 <ΔVs01) as shown in FIG.

Similarly, in the driving period (TT2) after the charge recycling period, the counter electrode CE is electrically connected to the output of the counter electrode voltage generation circuit 56 of the power supply circuit 50. Therefore, in the driving period, the common electrode voltage VCOM is supplied to the common electrode CE and the common electrode voltage generation circuit 56. At this time, the common electrode voltage generation circuit 56 charges and discharges the common electrode CE until the high potential side voltage VCOMH is reached with reference to the potential after the change in the charge reuse period TT1. Therefore, in the driving period after the charge recycling period, the voltage of the counter electrode CE that should be changed by the counter electrode voltage generation circuit 56 may be low. That is, based on the potential of the counter electrode CE in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection of pixels connected to the gate line _GK) is used as it is. When the potential of the counter electrode CE during (period) is set, the counter electrode voltage generation circuit 56 needs to charge / discharge the charge of the counter electrode CE by ΔVc01 as shown in FIG. On the other hand, by providing the above-described charge recycle period, the counter electrode voltage generation circuit 56 may charge and discharge the charge of the counter electrode CE by ΔVc02 (ΔVc02 <ΔVc01) as shown in FIG.

3.2 Second Operation Mode FIG. 11 shows a principle configuration diagram in the second operation mode of the liquid crystal device 10 of the present embodiment.

In FIG. 11, the same parts as those in FIG. 1 or FIG. In Figure 11, the gate lines G _K and the electrical equivalent circuit of a pixel provided at the intersection of the source line S _L, the gate line G _{K + 1} and the source line S _{L + 1} of the electrical equivalent circuit of a pixel provided at the intersection The same applies to the electrical equivalent circuits of other pixels. FIG. 11 shows a source output switching circuit, a source charge storage switch CSW, a counter electrode charge storage switch VSW, and a node short circuit switch HSW of the source line driving circuit 20.

  FIG. 12 shows a waveform diagram of an operation example of the liquid crystal device 10 of FIG.

FIG. 12 shows changes in the potentials of the gate lines G _K , G _{K + 1} , the source line _SL, and the counter electrode CE, but the same applies to other gate lines and source lines. 12, a selection period of the pixel that is connected with the gate line G _K within one horizontal scanning period (1H), the scan voltage is applied to the gate line G _K, the selection of pixels is connected with the gate line G _{K + 1} A scanning voltage is applied to the gate line _{GK + 1} within one horizontal scanning period. Each horizontal scanning period includes a charge recycling period provided in the first half part and a driving period provided in the second half part. The source output switching circuits SSW _L , SSW _{L + 1} , the counter electrode charge storage switch VSW and the source charge storage switch CSW when transitioning from the charge recycle period to the drive period and when transitioning from the drive period to the charge recycle period Switching control is performed. In the second operation mode, the node short-circuit switch HSW is set to a non-conductive state.

In the charge recycle period (TT10), in the source output switching circuits SSW _L and SSW _{L + 1} , the source lines S _L and S _{L + 1} are electrically connected to the shared line COL including the second capacitor element connection node, respectively. Further, the source charge storage switch CSW becomes conductive, and the shared line COL is electrically connected to one end of the second capacitor element CCS via the second capacitor element connection terminal TL2. Therefore, in the charge recycle period, one end of the second capacitor element CCS and the source lines S _L and S _{L + 1} have the same potential, and the charge accumulated in the parasitic capacitance of the source line is in accordance with the law of charge conservation. The charge is replenished to one end of the capacitive element CCS, or the charge accumulated in the second capacitive element CCS is supplemented to the parasitic capacitances of the source lines S _L and S _{L + 1} . That is, in the charge recycle period, the potential of the source line is changed without replenishing charges from the power supply circuit 50 at all.

  Similarly, in the charge recycle period, the output of the counter electrode voltage generation circuit (not shown) is set to a high impedance state, and the counter electrode charge storage switch VSW is set to a conductive state. Is electrically connected to one end of the first capacitor element CCV via the capacitor element connection terminal TL1. Therefore, in the charge recycle period, one end of the first capacitive element CCV and the counter electrode CE have the same potential, and the charge accumulated in the parasitic capacitance of the counter electrode CE supplements one end of the first capacitor element CCV. Or charge accumulated in the first capacitor element CCV is supplemented to the parasitic capacitance of the counter electrode CE. That is, in the charge recycling period, the potential of the counter electrode CE is changed without replenishing charges from the power supply circuit 50 at all.

Next, in the drive period (TT20) after the charge recycle period, in the source output switching circuits SSW _L and SSW _{L + 1} , the source lines S _L and S _{L + 1} are electrically connected to the output of the output buffer of the source line drive circuit 20, respectively. Connected to. Further, the source charge storage switch CSW is set in a non-conductive state. Therefore, in the driving period, the source lines S _L and S _{L + 1} are driven by the output buffer of the source line driving circuit 20. At this time, the output buffer of the source line driver circuit 20 charges and discharges the source line charge until each source line becomes a potential corresponding to each display data with reference to the potential after the change in the charge reuse period TT10. . Therefore, in the driving period after the charge recycling period, the source line voltage to be changed by the output buffer of the source line driving circuit 20 is often low. That is, based on the potential of the source line in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection period of pixels connected to the gate line _GK) is used as it is. 12), it is necessary for the output buffer of the source line driver circuit 20 to charge / discharge the charge of the source line by ΔVs1 as shown in FIG. On the other hand, by providing the above-described charge recycling period, the output buffer of the source line driver circuit 20 only needs to charge / discharge the charge of the source line by ΔVs2 (ΔVs2 <ΔVs1) as shown in FIG.

Similarly, in the driving period (TT20) after the charge recycling period, the common electrode charge storage switch VSW is set in a non-conductive state, and the common electrode CE is electrically connected to the output of the common electrode voltage generation circuit 56 of the power supply circuit 50. Connected. Therefore, in the driving period, the common electrode voltage VCOM is supplied to the common electrode CE and the common electrode voltage generation circuit 56. At this time, the common electrode voltage generation circuit 56 charges and discharges the common electrode CE until the high potential side voltage VCOMH is reached with reference to the potential after the change in the charge recycle period TT10. Therefore, in the driving period after the charge recycling period, the voltage of the counter electrode CE that should be changed by the counter electrode voltage generation circuit 56 may be low. That is, based on the potential of the counter electrode CE in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection of pixels connected to the gate line _GK) is used as it is. When it is attempted to set the potential of the counter electrode CE during (period), the counter electrode voltage generation circuit 56 needs to charge / discharge the charge of the counter electrode CE by ΔVc1 as shown in FIG. On the other hand, by providing the above-described charge recycling period, the counter electrode voltage generation circuit 56 may charge / discharge the charge of the counter electrode CE by ΔVc2 (ΔVc2 <ΔVc1) as shown in FIG.

  In the next horizontal scanning period, a charge recycling period and a driving period are provided, and the same is performed in each period. Since the power consumption accompanying the drive of the source line in the charge reuse period depends on the voltage (that is, display data) to be set by the source line driver circuit 20 in the drive period, the effect of reducing the power consumption by the charge reuse Will fade. However, since the counter electrode CE is set to either the high potential side voltage VCOMH or the low potential side voltage VCOML, the power consumption can be reliably reduced with a simple configuration without depending on the display data. The effect of reducing power consumption by reusing charges is remarkable.

  As described above, in the first operation mode, charge reuse can be achieved without using the first and second capacitor elements CCS and CCV, so that the chip size and mounting area of the display driver 60 can be reduced. On the other hand, since a voltage corresponding to the display data is applied to the source line, the effect of charge reuse depends on the display data.

  On the other hand, in the second operation mode, since the counter electrode voltage is binary, the effect of reusing the charge of the counter electrode CE appears, so that the effect of low power consumption can be obtained with certainty. On the other hand, since the charge is reused without using the first or second capacitor elements CCS and CCV, the chip size and mounting area of the display driver 60 cannot be reduced.

  According to the present embodiment, since the charge reuse can be realized in any one of the above operation modes only by providing the node short-circuit switch HSW, various types of user requests can be satisfied by one type of display driver. As a result, the manufacturing cost can be further reduced.

3.3 Specific Configuration Example FIG. 13 shows a configuration example of the operational amplifier circuit blocks OPC _{1 to} OPC _N , the shared line COL, and various switches in FIG.

That is, FIG. 13 shows the connection relationship among the operational amplifier circuit blocks OPC _{1 to} OPC _N , the common line COL, the counter electrode charge storage switch VSW, the source charge storage switch CSW, and the node short circuit switch HSW. In FIG. 13, the same parts as those in FIG. 1, FIG. 2, FIG. 9 or FIG.

The configuration of each of the operational amplifier circuit blocks OPC _{1 to} OPC _N is the same, and the operational amplifier circuit block OPC ₁ will be described below.

The operational amplifier circuit block OPC ₁ includes a voltage follower-connected operational amplifier VOP ₁ and a source output switching circuit SSW ₁ . The source output switching circuit SSW ₁ includes a first source output switch SS ₁ and a first source short-circuit switch C ₂ SW ₁ . The first source output switch SS ₁ is on-off controlled by a control signal c1, xc1 (common control signal. Hereinafter the same). The control signal xc1 is an inverted signal of the control signal c1. The first source short circuit switch C2SW ₁ is ON / OFF controlled by control signals cc and xcc. The control signal xcc is an inverted signal of the control signal cc. The output of the operational amplifier VOP ₁ is connected to the _first source output node SND ₁ via the _first source output switch SS ₁ . The first source output node SND ₁ is connected to a given source voltage output node SVND via a _first source short circuit switch C2SW ₁ . The source voltage output node SVND is connected to the second capacitor element connection node C2ND via the source charge storage switch CSW. The source charge storage switch CSW is on / off controlled by control signals cs and xcs. The control signal xcs is an inverted signal of the control signal cs.

Thus, the first source short-circuit switch C2SW ₁ is provided between the source voltage output node SVND and the first source output node SND ₁ . The source charge storage switch CSW is provided between the source voltage output node SVND and the second capacitor element connection node C2ND to which one end of the second capacitor element CCS can be connected.

  The common electrode voltage output node VND, which is the output of the common electrode voltage generation circuit 56, is electrically connected to the common electrode voltage output pad CE_P as the common electrode voltage output terminal TL3 to which the common electrode CE of the display panel 12 is electrically connected. Connected. The common electrode voltage output node VND is connected to the first capacitor element connection node C1ND via the common electrode charge storage switch VSW. The common electrode charge storage switch VSW is on / off controlled by control signals cv and xcv. The control signal xcv is an inverted signal of the control signal cv. The first capacitor element connection node C1ND is electrically connected to a first capacitor element connection pad CP_P as the first capacitor element connection terminal TL1.

  The node short-circuit switch HSW is provided between the common electrode voltage output node VND and the source voltage output node SVND (shared line COL). The node short circuit switch HSW is ON / OFF controlled by the control signals ch and xch. The control signal xch is an inverted signal of the control signal ch.

Similarly, the common line COL including the source voltage output node SVND is connected to the source short circuit switch of each operational amplifier circuit block. That is, the display driver 60, a common line COL having one end electrically connected to the source charge storage switch CSW is connected a source voltage output node SVND electrically, the second to the source line S ₂ A second source short-circuit switch C2SW ₂ provided between the second source output node SND ₂ to which the output voltage is supplied and the common line COL may be included. A first source short-circuit switch C2SW ₁ is provided between the first source output node SND ₁ and the shared line COL. A second source short circuit switch C2SW ₂ is provided between the second source output node SND ₂ and the shared line COL.

  Further, the display driver 60 can include a discharge transistor DisTr. A control signal dis is supplied to the gate of the discharging transistor DisTr. A discharge voltage (for example, the system ground power supply voltage VSS) is supplied to the source of the discharge transistor DisTr, and the drain of the discharge transistor DisTr is electrically connected to the common line COL. Then, the voltage of the shared line COL is set to the discharge voltage by the control signal dis. Such a discharge transistor DisTr is commonly used for discharging the first and second source lines.

Note that, during the pixel electrode selection period of the display panel 12, the first and second source short-circuit switches C2SW ₁ and C2SW ₂ are set in a conductive state, and the discharge transistor DisTr is turned on, so that The two source lines S ₁ and S ₂ can be discharged. By so doing, so-called off-writing can be performed with a very simple configuration. Here, off writing means giving a given off voltage to the source line in order to shift to the display off state.

In addition, the operational amplifier circuit block OPC ₁ can further include a _first bypass switch BSW ₁ . The first bypass switch BSW ₁ is on / off controlled by control signals c2 and xc2. The control signal xc2 is an inverted signal of the control signal c2. In the operational amplifier circuit block OPC ₁ , after the charge recycling as described above is performed in the first half of one horizontal scanning period as a pixel selection period, the first source output is performed in the second driving period of the horizontal scanning period. The drive control of the source line S ₁ is performed by the switch SS ₁ and the first bypass switch BSW ₁ .

That is, in the first half of the driving period, the first source output switch SS ₁ is set in the conductive state and the first bypass switch BSW ₁ is set in the non-conductive state, and the operational amplifier VOP ₁ sets the first source output node SND. ₁ is driven. Thereafter, in the second half of the driving period, the operational amplifier is connected to the first source output node SND ₁ with the first source output switch SS _{1 set} in a non-conductive state and the first bypass switch BSW ₁ set in a conductive state. It provides an input voltage of VOP _1. Thus, the voltage set at the first source output node SND ₁ can be set at high speed and with high accuracy.

  FIG. 14 shows a configuration example of the common electrode voltage generation circuit 56 and the common electrode charge storage switch VSW shown in FIG.

  The counter electrode voltage generation circuit 56 generates a counter electrode voltage VCOM applied to the counter electrode CE facing the pixel electrode of the display panel (electro-optical device) 12 and the liquid crystal element (electro-optical material). The counter electrode voltage generation circuit 56 includes first and second operational amplifiers OP1 and OP2 that are operational amplifiers connected in voltage follower, and a switching circuit SEL. The first operational amplifier OP1 outputs a high potential side voltage VCOMH of the common electrode voltage VCOM. The second operational amplifier OP2 outputs a low potential side voltage VCOML of the common electrode voltage VCOM. The switching circuit SEL outputs one of the high potential side voltage VCOMH and the low potential side voltage VCOML as the counter electrode voltage VCOM in accordance with the polarity inversion timing for inverting the polarity of the voltage applied to the liquid crystal element (electro-optical material). To do. Note that the first and second operational amplifiers OP1 and OP2 may be operated as regulators.

  The switching circuit SEL includes a P-type (first conductivity type) metal oxide semiconductor (MOS) transistor (hereinafter simply referred to as a transistor) PTr and an N-type (second conductivity type) transistor NTr. Can do. The source of the transistor PTr is connected to the output of the first operational amplifier OP1. The drain of the transistor PTr is electrically connected to the counter electrode CE. A control signal XPOLc is supplied to the gate of the transistor PTr. The source of the transistor NTr is connected to the output of the second operational amplifier OP2. The drain of the transistor NTr is electrically connected to the counter electrode CE. A control signal POLc is supplied to the gate of the transistor NTr.

  The control signals XPOLc and POLc are generated based on the polarity inversion signal POL that defines the polarity inversion timing. The switching circuit SEL can output the high potential side voltage VCOMH or the low potential side voltage VCOML based on the control signals XPOLc and POLc. The switching circuit SEL can set its output to a high impedance state based on the control signals XPOLc and POLc.

  Such a counter electrode voltage generation circuit 56 can include a VCOMH generation circuit (counter electrode high potential side voltage generation circuit) 62 and a VCOML generation circuit (counter electrode low potential side voltage generation circuit) 64. The VCOMH generation circuit 62 can generate the voltage VCOMH0 by a known charge pump operation based on, for example, the system ground power supply voltage VSS and the power supply voltage VDDHS. The voltage VCOMH0 is supplied to the input of the first operational amplifier OP1. The VCOML generation circuit 64 can generate the voltage VCOML0 by a known charge pump operation based on, for example, the system ground power supply voltage VSS and the power supply voltage VDDHS. The voltage VCOML0 is supplied to the input of the second operational amplifier OP2.

  When the switching circuit SEL outputs the high potential side voltage VCOMH as the common electrode voltage VCOM, the common electrode voltage generation circuit 56 performs control to stop or limit the operating current of the second operational amplifier OP2 by a control signal (not shown). Do. In addition, when the switching circuit SEL outputs the low potential side voltage VCOML as the common electrode voltage VCOM, the common electrode voltage generation circuit 56 performs control to stop or limit the operating current of the first operational amplifier OP1 by a control signal (not shown). .

  Thus, when one of the high potential side voltage VCOMH and the low potential side voltage VCOML of the common electrode voltage VCOM is applied to the common electrode CE, an operational amplifier that outputs the other of the high potential side voltage VCOMH and the low potential side voltage VCOML. Therefore, it is possible to reduce current consumption unnecessary for generating the common electrode voltage VCOM.

  The output of the switching circuit SEL is electrically connected to the common electrode voltage output node VND. The common electrode voltage output node VND is electrically connected to a first capacitor element connection node C1ND to which one end of the first capacitor element can be connected. The first capacitor element connection node C1ND is electrically connected to the counter electrode CE of the display panel 12 through the counter electrode voltage output terminal TL3.

3.3.1 Example of Control Timing in First Operation Mode FIG. 15 shows a timing diagram of a control example of the operational amplifier circuit block OPC ₁ and various switches in FIG. 13 in the first operation mode.

In FIG. 15, when the control signals c1, c2, cc, cs, ch, and dis in FIG. 13 are at the H level, each switch is set to ON (conductive state). In the example of FIG. 15, it is assumed that the control signal dis is always at the L level. In FIG. 15, only a control example of the operational amplifier circuit block OPC ₁ will be described, but the operational amplifier circuit blocks OPC _{2 to} OPC _N are also controlled by the same control signal as the operational amplifier circuit block OPC ₁ .

In the charge recycling period, which is the first half of one horizontal scanning period, the control signals cc and ch are set to the H level, and the control signals c1, c2, and cs are set to the L level. As a result, the common electrode charge storage switch VSW and the source charge storage switch CSW are set in a non-conductive state, and the node short-circuit switch HSW is set in a conductive state. In other words, the node short circuit switch is set to a conductive state in a state where the counter electrode charge storage switch VSW and the source charge storage switch CSW are set to a non-conductive state. As a result, the common line COL and the counter electrode voltage output node VND are electrically connected. Accordingly, charges accumulated in the parasitic capacitance of the common line COL or the common electrode voltage output node VND are reused, and the potentials of the common line COL and the common electrode voltage output node VND change. At this time, the source short-circuit switch of each operational amplifier circuit block is also set to the conductive state, so that the first to Nth source lines S _{1 to} S _N and the counter electrode CE have the same potential.

  Thereafter, as described below, the common electrode voltage VCOM is supplied to the common electrode voltage output node VND to drive the common electrode CE, and the voltage corresponding to the display data is supplied to the source line to drive the source line.

That is, in the pre-buffer driving period after the charge recycle period, the control signals cc and ch are at the L level and the control signal c1 is at the H level. Note that, during the driving period, the common electrode charge storage switch VSW and the source charge storage switch CSW are set to OFF (non-conducting state). As a result, the first source output node SND ₁ whose potential has changed within the charge recycling period is driven by the operational amplifier VOP ₁ . The operational amplifier VOP ₁ is supplied with the data voltage selected by the DAC 28. The operational amplifier VOP ₁ consumes an operating current, but can change the potential of the first source output node SND ₁ at high speed with high driving capability.

Next, in the DAC driving period of the driving period, the control signal c1 becomes L level and the control signal c2 becomes H level. Thus, the first source output node SND ₁ is electrically disconnected from the output of the operational amplifier VOP ₁ and the data voltage from the DAC 28 is directly supplied. Thereby, the voltage of the first source output node SND ₁ can be set to a highly accurate data voltage from the DAC 28. In the DAC drive period, the operation of the operational amplifier VOP ₁ can be stopped, so that power consumption can be reduced.

  As described above, with the common electrode charge storage switch VSW and the source charge storage switch CSW set to the non-conductive state, the node short-circuit switch HSW is once set to the conductive state, and then opposed to the common electrode voltage output node VND. The counter electrode CE is driven by supplying the electrode voltage VCOM, and the source line is driven by supplying a voltage corresponding to the display data to the source line.

More specifically, after setting the outputs of the source line driving circuit 20 and the common electrode voltage generation circuit 56 to a high impedance state and electrically connecting the source voltage output node SVND and the common electrode voltage output node VND, The source voltage output node SVND and the counter electrode voltage output node VND are electrically cut off. In this state, the source line drive circuit 20 supplies a voltage corresponding to the display data to the first or second source line S ₁ , S ₂ , and the counter electrode voltage generation circuit 56 applies to the counter electrode CE. A counter electrode voltage VCOM is supplied.

FIG. 16 shows a timing chart of another control example of the operational amplifier circuit block OPC ₁ and various switches in FIG. 13 in the first operation mode.

  FIG. 16 shows a timing diagram of a so-called off-write control example. Control of the charge recycle period and switch control of the source charge storage switch CSW are the same as in FIG.

In the pre-buffer period and the DAC driving period of the driving period, the control signal cc is at the H level and the control signal dis is at the H level. As a result, the common line COL is set to the system ground power supply voltage VSS by the discharging transistor DisTr. Then, the first source output node SND ₁ whose potential has fluctuated within the charge reuse period is set to the system ground power supply voltage VSS via the _first source short-circuit switch C2SW ₁ set to the conductive state. The first voltage source output node SND ₁ is supplied to the first source line S _1, so-called off-writing control is performed. Thus, in the display panel 12, the voltage of the _first source output node SND ₁ supplied to the source line need only be written to the pixel electrode in the same manner as in the normal display operation.

The off-write control as described above is similarly performed in the operational amplifier circuit blocks OPC _{2 to} OPC _N. In this way, display off control can be performed with a very simple configuration without supplying a predetermined off voltage from the DAC.

3.3.2 Example of Control Timing in Second Operation Mode FIG. 17 shows a timing diagram of a control example of the operational amplifier circuit block OPC ₁ and various switches in FIG. 13 in the second operation mode.

In FIG. 17, when the control signals c1, c2, cc, cs, ch, and dis in FIG. 13 are at the H level, each switch is set to ON (conductive state). In the example of FIG. 17, it is assumed that the control signal dis is always at the L level. In FIG. 17, only a control example of the operational amplifier circuit block OPC ₁ will be described, but the operational amplifier circuit blocks OPC _{2 to} OPC _N are also controlled by the same control signal as the operational amplifier circuit block OPC ₁ .

In the charge recycling period, which is the first half of one horizontal scanning period, the control signals cc, cs, cv are set to the H level, and the control signals c1, c2, ch are set to the L level. As a result, the source charge storage switch CSW is set in a conductive state. Then, the first source output node SND ₁ and one end of the second capacitor element CCS connected to the second capacitor element connection terminal TL2 are set to the same potential. As a result, the charge of the second capacitor element CCS is reused, and the potential of the first source output node SND ₁ varies. Further, the common electrode voltage output node VND is set to the same potential as one end of the first capacitor element CCV connected to the first capacitor element connection terminal TL1. Thereby, the charge of the first capacitor element CCV is reused, and the potential of the common electrode voltage output node VND varies.

  Here, the control signal cv has the same timing as the control signal cc in FIG. Therefore, a period for electrically connecting the source voltage output node SVND and the second capacitor element connection node C2ND, and a period for electrically connecting the counter electrode voltage output node VND and the first capacitor element connection node C1ND. But there are duplicates.

In the subsequent pre-buffer driving period, the control signals cc, cs, cv are at the L level, and the control signal c1 is at the H level. Note that, within the driving period, the source charge storage switch CSW is set to OFF (non-conducting state). As a result, the first source output node SND ₁ whose potential has changed within the charge recycling period is driven by the operational amplifier VOP ₁ . The operational amplifier VOP ₁ is supplied with the data voltage selected by the DAC 28. The operational amplifier VOP ₁ consumes an operating current, but can change the potential of the first source output node SND ₁ at high speed with high driving capability.

Next, in the DAC driving period of the driving period, the control signal c1 becomes L level and the control signal c2 becomes H level. As a result, the first source output node SND ₁ is electrically disconnected from the output of the operational amplifier VOP ₁ and is directly supplied with the data voltage from the DAC 28. Thereby, the voltage of the first source output node SND ₁ can be set to a highly accurate data voltage from the DAC 28. In the DAC drive period, the operation of the operational amplifier VOP ₁ can be stopped, so that power consumption can be reduced.

  As described above, in the second operation mode, the node short-circuit switch HSW is set to a non-conductive state. In this state, the counter electrode voltage output node VND and the first capacitor element connection node C1ND are once electrically connected by the counter electrode charge storage switch VSW, and then the counter electrode voltage VCOM is connected to the counter electrode voltage output node VND. To drive the counter electrode CE. At the same time, the source voltage output node SVND and the second capacitor element connection node C2ND are once electrically connected by the source charge storage switch CSW, and then the source charge output switch SVSW and the second voltage element connection node CND In a state where the capacitor element connection node C2ND is electrically cut off, a voltage corresponding to display data is supplied to the source line to drive the source line.

More specifically, the first or second source output node SND ₁ , SND ₂ and the second capacitor element connection node C2ND are electrically connected in a state where the output of the source line driver circuit 20 is set to a high impedance state. After the first and second source output nodes SND ₁ , SND ₂ and the second capacitor element connection node C 2 ND are electrically disconnected, the source line driver circuit 20 is connected to the first or second source output node SND ₁ , SND 2. A voltage corresponding to the display data is supplied to the source lines S ₁ and S ₂ . The counter electrode voltage output node VND and the first capacitor element connection node C1ND are electrically connected by the counter electrode charge storage switch VSW in a state where the output of the counter electrode voltage generation circuit 56 is set to a high impedance state. Thereafter, the counter electrode voltage generation circuit 56 supplies the counter electrode voltage VCOM to the counter electrode CE.

FIG. 18 shows a timing chart of another control example of the operational amplifier circuit block OPC ₁ and various switches in FIG. 13 in the second operation mode.

  FIG. 18 shows a timing chart of a so-called off write control example. Control of the charge recycle period and switch control of the source charge storage switch CSW are the same as in FIG.

In the pre-buffer period and the DAC driving period of the driving period, the control signal cc is at the H level and the control signal dis is at the H level. As a result, the common line COL is set to the system ground power supply voltage VSS by the discharging transistor DisTr. Then, the first source output node SND ₁ whose potential has fluctuated within the charge reuse period is set to the system ground power supply voltage VSS via the _first source short-circuit switch C2SW ₁ set to the conductive state. The first voltage source output node SND ₁ is supplied to the first source line S _1, so-called off-writing control is performed. Thus, in the display panel 12, the voltage of the _first source output node SND ₁ supplied to the source line need only be written to the pixel electrode in the same manner as in the normal display operation.

The off-write control as described above is similarly performed in the operational amplifier circuit blocks OPC _{2 to} OPC _N. In this way, display off control can be performed with a very simple configuration without supplying a predetermined off voltage from the DAC.

3.3.3 Generation of Control Signal The above control signal is generated by a control circuit (not shown) of the display driver 60.

  FIG. 19 shows a main part of the configuration of a control circuit (not shown) of the display driver 60.

  In FIG. 19, the control circuit includes a control register unit 80 and a timing generation unit 110. The control register unit 80 includes a plurality of control registers, and the set value of each control register is set by the host or the display controller 40.

  The timing generation unit 110 is based on the number of clocks of the reference clock OSC corresponding to the set value set in each register of the control register unit 80 according to the polarity of the voltage applied to the liquid crystal element defined by the polarity inversion signal POL. Various control signals are output. The reference clock OSC is generated in an oscillation circuit (not shown) in the display driver 60.

  FIG. 20 shows an outline of the configuration of the control register unit 80 of FIG.

  The control register unit 80 includes an operation mode setting register 81, a counter electrode charge storage switch-on timing setting register 82, a counter electrode charge storage switch-off timing setting register 84, a source charge storage switch-on timing setting register 86, and a source charge storage. Switch off timing setting register 88, prebuffer driving start timing setting register 90, prebuffer driving end timing setting register 92, DAC driving start timing setting register 94, DAC driving end timing setting register 96, source short circuit switch on timing setting register 98 Source short circuit switch off timing setting register 100, node short circuit switch on timing setting register 102, and node short circuit switch off timing setting register 104. .

  In the operation mode setting register 81, control data corresponding to the first or second operation mode is set. Based on the control signal Mode corresponding to the control data of the operation mode setting register 81, each unit of the display driver 60 performs control corresponding to the first or second operation mode when performing charge recycling control.

  The counter electrode charge storage switch on timing setting register 82 stores the number of reference clocks OSC corresponding to the on timing of the counter electrode charge storage switch VSW with reference to the start timing of the horizontal scanning period (scanning period in a broad sense). Vcon is set. In the counter electrode charge storage switch off timing setting register 84, the clock number Vcoff of the reference clock OSC corresponding to the off timing of the counter electrode charge storage switch VSW is set with reference to the start timing of the horizontal scanning period. The timing generator 110 generates control signals cv and xcv based on the control signal Mode and the clock numbers Vcon and Voff.

  In the source charge storage switch on timing setting register 86, the clock number Scon of the reference clock OSC corresponding to the on timing of the source charge storage switch CSW is set with reference to the start timing of the horizontal scanning period. In the source charge accumulation switch off timing setting register 88, the clock number Scoff of the reference clock OSC corresponding to the off timing of the source charge accumulation switch CSW is set with reference to the start timing of the horizontal scanning period. The timing generator 110 generates control signals cs and xcs based on the control signal Mode and the clock numbers Scon and Scoff.

The pre-buffer driving start timing setting register 90, based on the start timing of the horizontal scanning period, the number of clocks PBon reference clock OSC corresponding to the ON timing of the source output switch SS ₁ ~ SS _N of the first to N is set Is done. The pre-buffer driving end timing setting register 92, based on the start timing of the horizontal scanning period, the number of clocks PBoff reference clock OSC corresponding to off timing of the source output switch _SS 1 ~ SS _N of the first to N is set Is done. The timing generator 110 generates the control signals c1 and xc1 based on the control signal Mode and the clock numbers PBon and PBoff.

The DAC drive start timing setting register 94, based on the start timing of the horizontal scanning period, the number of clocks DDon reference clock OSC corresponding to the ON timing of the bypass switch _BSW 1 _{~BSW N} of the first to N is set . In the DAC drive end timing setting register 96, the clock number DDoff of the reference clock OSC corresponding to the off timing of the _{first to} Nth bypass switches BSW _{1 to} BSW _N is set based on the start timing of the horizontal scanning period. . The timing generator 110 generates control signals c2 and xc2 based on the control signal Mode and the clock numbers DDon and DDoff.

In the source short circuit switch on timing setting register 98, the clock number SBo of the reference clock OSC corresponding to the on timing of the _{first to} Nth source short circuit switches C2SW _{1 to} C2SW _N is set with reference to the start timing of the horizontal scanning period. Is done. In the source short circuit switch off timing setting register 100, the clock number SBoff of the reference clock OSC corresponding to the off timing of the _{first to} Nth source short circuit switches C2SW _{1 to} C2SW _N is set based on the start timing of the horizontal scanning period. Is done. The timing generation unit 110 generates control signals cc and xcc based on the control signal Mode and the clock numbers SBon and SBoff.

  In the node short circuit switch on timing setting register 102, the clock number NBon of the reference clock OSC corresponding to the on timing of the node short circuit switch HSW is set with reference to the start timing of the horizontal scanning period. In the node short circuit switch off timing setting register 104, the clock number NBoff of the reference clock OSC corresponding to the off timing of the node short circuit switch HSW is set with reference to the start timing of the horizontal scanning period. The timing generator 110 generates the control signals ch and xch based on the control signal Mode and the clock numbers NBon and NBoff.

  FIG. 21 illustrates an example of a circuit that generates the control signals cv and xcv in the timing generation unit 110.

  The timing generation unit 110 includes a counter 112, comparators 114 and 116, and a set / reset flip-flop 118.

  The counter 112 counts up in synchronization with the reference clock OSC with reference to the change point of the polarity inversion signal POL. The comparator 114 compares the count value of the counter 112 with the clock number Vcon that is the setting value of the counter electrode charge storage switch-on timing setting register 82, and outputs a pulse when they match. The comparator 116 compares the count value of the counter 112 with the clock number Vcoff, which is the setting value of the counter electrode charge storage switch-off timing setting register 84, and outputs a pulse when they match. The set / reset flip-flop 118 is set by a pulse from the comparator 114 and reset by a pulse from the comparator 116.

  The data output signal and the inverted data output signal of the set / reset flip-flop 118 are input to the mask circuit 119, for example. The mask circuit 1190 performs mask control of the data output signal and the inverted data output signal of the set / reset flip-flop 118 based on the control signal Mode, and outputs the control signals cv and xcv. That is, when the first operation mode is designated by the control signal Mode, the control signal cv is generated as shown in FIG. 15 or FIG. 16, and when the second operation mode is designated by the control signal Mode, FIG. Alternatively, a control signal is generated as shown in FIG. There are various methods for generating the control signal cv in accordance with such a control signal Mode, and the method is not limited to that shown in FIG.

  Although the control signals cv and xcv have been described with reference to FIG. 21, the control signals c1, xc1, c2, xc2, cc, xcc, cs, xcs, ch, and xch can be generated in the same manner.

FIG. 22 shows an example of a timing diagram of the control signals ch, cc, cs, cv, the common line COL, the counter electrode CE, and the first source line S1 in the _first operation mode.

  By controlling the change timing of the control signals ch and cc using the control register as described above, a so-called charge recycling period can be provided. At this time, the control signal dis is set to L level.

By so doing, charge replenishment is performed between the _first to Nth source lines S _{1 to} S _N and the counter electrode CE via the shared line COL, without charge replenishment from the power supply circuit. The potentials of the _first to Nth source lines S _{1 to} S _N and the counter electrode CE can be changed.

  Thereafter, the control signal cc is set to the L level, and the driving period is started.

23 shows the control signal in the second operation mode ch, cc, cs, cv shared line COL, the counter electrode CE, an example of a first timing diagram of a source line _{S 1.}

  By using the control register as described above and controlling the control signals cc, cs, and cv so as to change at substantially the same timing, a so-called charge recycling period can be provided. At this time, the control signal dis is set to L level.

As a result, the common line COL is replenished with the second capacitor element CCS, and the potential of the common line COL is changed without replenishing the charge from the power supply circuit. it is possible to change the potential of the source line S _1. Similarly, the common electrode voltage output node VND is replenished with the first capacitive element CCV and changes the potential of the common electrode voltage output node VND without replenishing the charge from the power supply circuit. be able to.

  Thereafter, the control signals cc, cs, cv are set to the L level, and the driving period is started.

  FIG. 24 shows a timing chart of an operation example of the display driver 60 in the present embodiment.

  In FIG. 24, it is assumed that the display driver 60 is set to the second operation mode. In the present embodiment, the reference clock OSC can be used as a dot clock. Display data for one pixel or one dot is supplied from the display controller 40 to the display driver 60 in dot clock units.

  For example, the count value of the counter 112 in FIG. 1 starts counting up at the timing shown in FIG. Then, for example, the control signals cs and cv change at a count value corresponding to the value set in the control register of the control register unit 80 of FIG.

  Then, as described above, the source output changes. Here, a period in which a high impedance state is set is provided between the DAC drive period and the charge recycle period, and between the charge recycle period and the prebuffer drive period. Thereby, generation | occurrence | production of a through current can be suppressed at the time of the transition of a period.

  Note that the gate output timing can be changed by the set value of the control register in the same manner as described above.

As described above, the display driver 60 can include a control register in which control data is set. Then, it can be said that the common electrode charge storage switch VSW, the source charge storage switch CSW, the first source short circuit switch C2SW ₁ or the second source short circuit switch C2SW ₂ are switch-controlled based on the control data.

In the above description, each switch is controlled based on the control data set in the control register. However, the present invention is not limited to this. For example, the display driver 60 includes an external setting terminal, and the counter electrode charge storage switch VSW, the source charge storage switch CSW, the first source short circuit switch C2SW ₁ or the second source short circuit switch C2SW ₂ are connected to the external setting terminal. The switch may be controlled in accordance with the signal state supplied to. That is, the control signal of each switch may be supplied from an external setting terminal or generated based on a signal input to the external setting terminal.

4). Transistor structure of switch In this embodiment, the common electrode charge storage switch VSW, the source charge storage switch CSW, the node short circuit switch HSW, the first to Nth source short circuit switches C2SW _{1 to} C2SW _N , the first to Nth bypass switch _BSW 1 _{~BSW N,} and first to transistors constituting the respective switches of the N source output switch _SS 1 ~ SS _N of varied structure of the discharge transistor DISTR. More specifically, the chip area of the display driver 60 can be minimized and the manufacturing cost can be reduced by making the structure of the transistor or the discharging transistor DisTr constituting the switch different as follows.

For example, first to except transistors constituting the respective switches of the N source output switch _SS 1 ~ SS _N of the counter electrode charge storage switch VSW, the source charge storage switch CSW, a node short-circuit switch HSW, first to The N-th source short-circuit switches C2SW _{1 to} C2SW _N , the first to N-th bypass switches BSW _{1 to} BSW _N , and the discharge transistor DisTr are formed in a so-called triple well structure. Meanwhile, the transistors constituting the respective switches of the first to the source output switch SS ₁ ~ SS _N of the N, form a so-called twin-well structure.

Each of the _{first to} Nth source output switches SS _{1 to} SS _N is realized by a transfer gate including a P-type transistor and an N-type transistor.

25A and 25B schematically show cross-sectional views of a twin-well transistor that forms the _first source output switch SS1. FIG. 25A is a cross-sectional view of an N-type transistor, and FIG. 25B is a cross-sectional view of a P-type transistor. In FIGS. 25A and 25B, cross-sectional views of transistors formed on a P-type semiconductor substrate are shown; however, it is a matter of course that the transistors may be formed on an N-type semiconductor substrate.

In FIG. 25A, high-concentration impurity diffusion layers 132 and 134 containing N-type impurities are formed in a P-type semiconductor substrate 130 as drain and source regions, respectively, and high-concentration containing P-type impurities. The impurity diffusion layer 136 is formed. A gate electrode 138 is provided on the region of the P-type semiconductor substrate 130 sandwiched between the impurity diffusion layers 132 and 134 via a gate insulating film. A system ground power supply voltage VSS, which is the lowest potential of the source line driving circuit 20, is supplied to the impurity diffusion layer 136 as a substrate potential. The control signal c1 is supplied to the gate electrode 138 in a state where the voltage of the first source output node SND ₁ is supplied to the impurity diffusion layer 132 and the output voltage of the operational amplifier VOP ₁ is supplied to the impurity diffusion layer 134. Thus, a channel region is formed.

In FIG. 25B, an N-type well (low-concentration impurity layer; hereinafter the same) 140 containing an N-type impurity is formed in a P-type semiconductor substrate 130. In the N-type well 140, high-concentration impurity diffusion layers 142 and 144 containing P-type impurities are formed as a drain region and a source region, respectively, and a high-concentration impurity diffusion layer 146 containing N-type impurities is formed. Is formed. A gate electrode 148 is provided on the region of the N-type well 140 sandwiched between the impurity diffusion layers 142 and 144 via a gate insulating film. The impurity diffusion layer 146 is supplied with the power supply voltage VDDHS which is the highest potential of the source line driver circuit 20. The control signal xc1 is supplied to the gate electrode 148 in a state where the voltage of the first source output node SND ₁ is supplied to the impurity diffusion layer 142 and the output voltage of the operational amplifier VOP ₁ is supplied to the impurity diffusion layer 144. Thus, a channel region is formed.

  On the other hand, the common electrode charge storage switch VSW is realized by a transfer gate including a P-type transistor and an N-type transistor.

  FIG. 26 schematically shows a cross-sectional view of an N-type transistor having a triple well structure constituting the counter electrode charge storage switch VSW.

  Note that in FIG. 26, the same portions as those in FIG. 25A are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In the case of the triple well structure, an N-type well 150 containing an N-type impurity is formed in the P-type semiconductor substrate 130. A P-type well 152 containing P-type impurities is formed in the N-type well 150. High-concentration impurity diffusion layers 154 and 156 containing an N-type impurity are formed in the P-type well 152 as a drain region and a source region, respectively, and a high-concentration impurity diffusion layer 158 containing a P-type impurity is formed. Is done. A gate electrode 160 is provided on the region of the P-type well 152 sandwiched between the impurity diffusion layers 154 and 156 via a gate insulating film. A low potential side voltage VCOML is supplied to the impurity diffusion layer 158 as a substrate potential. The control signal cv is supplied to the gate electrode 160 in a state where the voltage of the first capacitor element connection node C1ND is supplied to the impurity diffusion layer 154 and the voltage of the counter electrode voltage output node VND is supplied to the impurity diffusion layer 156. By applying, a channel region is formed. That is, the low potential side voltage VCOML is supplied to the impurity layer in which the channel region is formed.

  At this time, the well voltage VNW1 is supplied to the N-type well 150 via the high-concentration impurity diffusion layer 162 containing the N-type impurity. The system ground power supply voltage VSS is supplied to the P-type semiconductor substrate 130 via a high-concentration impurity diffusion layer 164 containing P-type impurities. The well voltage VNW1 only needs to be higher than the system ground power supply voltage VSS and the low potential side voltage VCOML, and can be, for example, the voltage VDD of the high potential side power supply.

  Note that in the case of a P-type transistor having a triple well structure, a high potential side voltage VCOMH is supplied as a substrate potential to an impurity layer in which a channel region is formed.

That is, as described above, the counter electrode charge storage switch VSW includes, for example, an N-type first transistor (first conductivity type first transistor), and constitutes the _first source output switch SS1. When a transistor composed of a twin well such as a transistor is an N-type transistor, the substrate potential of the first transistor is set to a transistor composed of a twin well such as a transistor constituting the _first source output switch SS1. This is different from the substrate potential.

  Since the triple well transistor has a larger layout area than the twin well transistor, the chip area of the display driver 60 can be minimized by forming the transistor as described above.

4.1 Arrangement of Transistors Constituting Switches In this embodiment, the mounting area of the display panel 12 and the display driver 60 is minimized in consideration of the display driver 60 being arranged along one side of the display panel 12. For this reason, each part of the display driver 60 is formed on an elongated chip. For this reason, elements to be normally arranged in the circuit block are also arranged in a pad arrangement area such as an output side I / F area provided on the signal output side to the display panel 12. In this case, if the transistors constituting the source line driving circuit 20 can be arranged in the pad arrangement region, a reduction in the chip area can be expected.

  However, in general, the number of output lines of the source line driving circuit 20 is very large. Therefore, when transistors or the like constituting the operational amplifier included in the source line driver circuit 20 are arranged in the pad arrangement region, a large number of signal lines must be routed in the pad arrangement region, and the area of the wiring region is increased. The width of the chip in the D2 direction cannot be reduced.

  Therefore, in the present embodiment, a method is adopted in which transistors constituting a switch controlled by a common control signal in the source line driving circuit 20 among the transistors constituting the source line driving circuit 20 are arranged in the pad arrangement region. .

  FIG. 27 shows a layout image diagram of a chip on which the display driver 60 in this embodiment is formed.

The source line drive circuit 20 of the display driver 60 includes a source driver block DB for driving the source lines S ₁ , S ₂ ,..., S _N−1 , S _N. The source line drive circuit 20 of the display driver 60 includes a plurality of control transistors TC1 to TCN and a pad arrangement region (output-side I / F region).

  Here, each control transistor of the control transistors TC1 to TCN is provided corresponding to each of the output lines QL1 to QLN of the source driver block DB, and each control transistor is based on a control signal on the common control signal line. Note that the control transistor may be an N-type (first conductivity type in a broad sense) transistor or a P-type (second conductivity type in a broad sense) transistor. Alternatively, a circuit in which an N-type transistor and a P-type transistor are combined, for example, a transfer gate transistor may be used.

  In the pad arrangement region, source driver pads (pad metal) for electrically connecting the source lines of the display panel and the output lines QL1, QL2, QL3, QL4,... Of the source driver block DB are arranged. . Note that pads other than the source driver pads may be arranged in the pad arrangement area, or dummy pads may be arranged. Or you may arrange | position the electrostatic protection element mentioned later and the protection circuit between power supplies. The pad arrangement area is, for example, an area between the side (boundary, edge) of the circuit block and the long side of the display driver 60 chip, for example, an output side I / F area. It is sufficient that at least the center position (pad center) of the pad is arranged in the pad arrangement region.

  In this embodiment, as shown in FIG. 27, control transistors TC1, TC2, TC3... Are arranged in the pad arrangement region. That is, the transistors constituting the differential section and the drive section of the operational amplifier of the data driver are not arranged in the pad arrangement area, and the control transistors TC1, TC2, TC3... As shown in FIG. Is arranged.

  For example, an output transistor that constitutes a driving unit of an operational amplifier is controlled by inputting a different input signal to the gate for each source output. Therefore, when such an output transistor is arranged in the pad arrangement region, the width of the chip of the display driver 60 in the D2 direction may increase due to the wiring region of these input signals.

  In this respect, the control transistors TC1, TC2, TC3,... Are controlled by a control signal on a common control signal line between the source outputs, not by a signal different for each source output. Therefore, even if the control transistors TC1, TC2, TC3,... Are arranged in the pad arrangement region, the area of the wiring region does not increase so much, so that the width of the display driver 60 in the D2 direction can be reduced.

FIG. 28 shows a configuration example of the operational amplifier circuit blocks OPC ₁ and OPC ₂ of the source line driving circuit 20.

In FIG. 28, the same parts as those in FIG. The operational amplifier VOP ₁ of the operational amplifier circuit block OPC ₁ provided corresponding to the pad P1 performs impedance conversion of the data signal output to the source line. That is, impedance conversion of the output signal from the DAC in the previous stage is performed to output a data signal to the source line, and the source line is driven.

In FIG. 28, in the pad arrangement region, the shared line COL is arranged in the same direction (D1 direction, D3 direction) as the control signal line. Further, as the control transistor TC1, the first source short circuit switch C2SW ₁ of FIG. 13 is employed. When the control signals cc and xcc on the control signal line become active, the output line QL1 and the shared line are electrically connected. As a control transistor TC2, the second source short-circuit switch C2SW ₂ of Figure 13 is employed. When the control signals cc and xcc on the control signal line become active, the output line QL2 and the shared line are electrically connected. The same applies to other source short-circuit switches.

  In this embodiment, control transistors TC1 and TC2 as shown in FIG. 28 are arranged in the pad arrangement region. Specifically, the control transistors TC1 and TC2 have at least a part (a part or all) of the control transistors TC1 and TC2 so as to overlap the pads (pad metal) P1 and P2 in a plan view (below the pads P1 and P2) ). In other words, pads P1 and P2 (pads for source driver) are arranged on the upper layer of TC1 and TC2 so as to overlap part or all of the control transistors TC1 and TC2 in plan view.

When a transistor is disposed below the pad, the threshold voltage of the transistor may fluctuate due to stress applied to the pad during bonding wire bonding or bump mounting. In addition, the capacitance of the interlayer film of the transistor may vary as compared with the designed capacitance. For this reason, there is a concern that the transistor characteristics on the wafer may be different from the characteristics at the time of mounting. Therefore, a transistor for outputting an analog voltage, such as a transistor as an analog circuit constituting the differential section (differential stage) and the driving section (driving stage) of the operational amplifiers VOP ₁ and VOP ₂ , dares to Place in the source driver block, not in the lower layer.

  On the other hand, transistors that function as digital switches and output digital voltages, such as the control transistors TC1 and TC2, are arranged below the pads. By doing so, the occurrence of the above-mentioned problems can be avoided, the chip layout area of the display driver 60 can be reduced, and the width of the display driver 60 chip in the D2 direction can be further reduced. For example, since the number of output lines of the source driver is very large, the area reduction effect is remarkable.

Further, the gates of the output transistors constituting the driving units of the operational amplifiers VOP ₁ and VOP ₂ are controlled by another gate control signal in the operational amplifier circuit blocks OPC ₁ and OPC ₂ . Therefore, when these output transistors are arranged in the pad arrangement region, it is necessary to wire a large number of gate control signals in the same number as the source lines in the pad arrangement region, and the area of the wiring region increases.

  On the other hand, the control transistors TC1 and TC2 in FIG. 28 are controlled by a control signal on the common control signal line. Therefore, when the control transistors TC1 and TC2 are arranged in the pad arrangement area, a common control signal line may be wired in the pad arrangement area. Further, since the output lines QL1 and QL2 are connected to the pads P1 and P2 by connection lines, if the control transistors TC1 and TC2 are disposed below the connection lines and the drains of TC1 and TC2 are connected to the connection lines, the wiring region The area of is hardly increased. Accordingly, an increase in the area of the wiring region due to the arrangement of the control transistors TC1 and TC2 is minimized.

  In FIG. 29, the first electrostatic protection element ESD1 is provided corresponding to the pad P1, and the second electrostatic protection element ESD2 is provided corresponding to the pad P2. Here, the first electrostatic protection element ESD1 includes a first diode DI1 provided between the high potential side power supply (VDDHS) and the output line QL1 of the source driver block, a low potential side power supply (VSS), and the output line QL1. Includes a second diode DI2. The second electrostatic protection element ESD2 includes a third diode DI3 provided between the high-potential-side power supply and the output line QL2 of the source driver block, and a second diode DI3 provided between the low-potential-side power supply and the output line QL2. 4 diodes DI4. These diodes DI1 to DI4 may be Zener diodes formed at the boundary between the diffusion region and the well region or the like, or GCD transistor diodes configured by connecting the source and gate of the transistor. Also good.

  In the present embodiment, such electrostatic protection elements ESD1 and ESD2 are also arranged in the pad arrangement region. Specifically, the electrostatic protection elements ESD1 and ESD2 are arranged below the pads P1 and P2 so that at least a part thereof overlaps the pads P1 and P2. By so doing, the width of the display driver 60 chip in the D2 direction can be further reduced.

4.2 Layout of Pad Arrangement Area FIG. 30 shows a layout example of the pad arrangement area. FIG. 31A shows an example of an electrostatic protection element provided between the power supplies VDDHS and VSS. In FIG. 31A, a diode DI1 (DI3) is provided between the output line QL1 (QL2) connected to the pad P1 (P2) and the power supply VDDHS. A diode DI2 (DI4) is provided between the output line QL1 (QL2) and the power supply VSS. If these diodes DI1 and DI2 are provided, even when an electrostatic voltage is applied to the pad P1, the charge can be released to the VDD2 side or the VSS side. Transistor) can be protected from static electricity.

  In FIG. 31A, an inter-power supply protection circuit 210 is provided between the high potential side power supply VDDHS and the low potential side power supply VSS. The inter-power supply protection circuit 210 functions as a voltage clamp circuit that clamps a voltage at a constant voltage value when a voltage higher than a given voltage is applied between VDDHS and VSS. As the inter-power supply protection circuit 210, an SCR (silicon controlled rectifier), a bipolar transistor, or a plurality of diodes connected in series in a reverse direction connection can be used.

  FIG. 31B shows a connection relationship between the pads P1 and P2 of FIG. 30, the diodes DI1 to DI4 constituting the electrostatic protection elements ESD1 and ESD2, and the control transistors TC1 and TC2. As shown in FIG. 31B, the diodes DI1 and DI2 that constitute the electrostatic protection element ESD1 and the control transistor TC1 are connected to the pad P1. The diodes DI3 and DI4 and the control transistors TC2, TCN2, and TCP2 constituting the electrostatic protection element ESD2 are connected to the pad P2. The diodes DI1 and DI3 are formed in the first well region, and the diodes DI2 and DI4 are formed in the second well region formed separately from the first well region.

  In FIG. 30, the direction in which the source lines (output lines) of the display panel are arranged is the D1 direction, and the direction orthogonal to the D1 direction is the D2 direction. As shown in FIG. 30, the control transistors TC1 and TC2 described in FIG. 29 are arranged in the direction D2 of the source driver block. The electrostatic protection elements ESD1 (diodes DI1, DI2) and ESD2 (diodes DI3, DI4) are arranged on the D2 direction side of the control transistors TC1, TC2. That is, the control transistors TC1 and TC2 are disposed between the source driver block and the electrostatic protection elements ESD1 and ESD2. In FIG. 30, the control transistors TC1 and TC2 and the electrostatic protection elements ESD1 and ESD2 are arranged in the lower layer (below) of the pads P1 and P2 so as to partially overlap the pads P1 and P2 in plan view. Is done.

  According to such an arrangement, the control transistors TC1 and TC2 are arranged in the immediate vicinity of the source driver block, so that the output line from the source driver block can be connected to the control transistors TC1 and TC2 through a short path, and the layout efficiency Wiring efficiency can be improved. Further, according to this arrangement, the electrostatic protection elements ESD1 and ESD2 are arranged closer to the pads P1 and P2 than the control transistors TC1 and TC2. Therefore, when an electrostatic voltage is applied to the pads P1 and P2, static electricity is discharged to the control transistors TC1 and TC2 with a time delay after being discharged by the electrostatic protection elements ESD1 and ESD2. This can prevent the control transistors TC1 and TC2 from being electrostatically destroyed.

  In this case, there is a technique for increasing the electrostatic withstand voltage by increasing the drain areas of the control transistors TC1 and TC2. However, if this technique is employed, the width of the pad arrangement region in the direction D2 increases, and the integrated circuit device D2 increases. The width in the direction will also increase.

  In this regard, according to the arrangement shown in FIG. 30, the electrostatic breakdown voltage can be increased without increasing the drain areas of the control transistors TC1 and TC2, so that the width of the integrated circuit device in the D2 direction is further reduced. it can.

  30, the pad arrangement area has a plurality of arrangement areas AR1, AR2, AR3,... Arranged along the D3 direction. In the arrangement area AR1 (each arrangement area), two source driver pads P1 and P2 (pad center positions) arranged in the direction D2 (K in a broad sense; K is an integer of 2 or more) are arranged. The Further, two (K) electrostatic protection elements ESD1 and ESD2 are arranged, each of which is connected to each of the pads P1 and P2. Furthermore, control transistors TC1 and TC2 are also arranged.

  In FIG. 30, two pads are staggered in each placement area. For example, the pads P1 and P2 arranged along the direction D2 are arranged with their center positions shifted in the direction D3. That is, when the D3 direction is the X axis, the pads P1 and P2 have different X coordinates.

  If the pads P1 and P2 are arranged in a staggered manner in this way, many pads can be arranged along the D3 direction (D1 direction), and a large number of data signals from the source driver block can be sent to the source line via the pads. Can be output.

  Further, when the pads are arranged in a staggered manner in this way and the pad pitch is reduced, the width of the arrangement area AR1 in the D3 direction (D1 direction) becomes narrow. In this regard, in FIG. 30, the arrangement area AR1 is formed by combining a plurality of pads P1 and P2. Therefore, it is possible to secure the width of the arrangement area AR1 in the D3 direction (D1 direction) to a certain extent. Thereby, the electrostatic protection elements ESD1 and ESD2 and the control transistors TC1 and TC2 can be arranged in the arrangement area AR1.

  In FIG. 30, the first electrostatic protection element ESD1 of the two (K) electrostatic protection elements arranged in the arrangement area AR1 includes first and second diodes DI1 and DI2, and the second The electrostatic protection element ESD2 includes third and fourth diodes DI3 and DI4. These diodes DI1, DI2, DI3, and DI4 are arranged along the direction D2 in the arrangement area AR1. Thus, if the diodes DI1 to DI4 are stacked in the D2 direction, the width of the arrangement area AR1 in the D1 direction can be reduced.

  That is, as a method of the comparative example, a method in which the diodes DI1 and DI2 are stacked along the direction D1 and the diodes DI3 and DI4 are stacked above the direction D1 can be considered. However, according to this method, since the diodes are stacked in the D3 direction (D1 direction) and the P-type well region and the N-type well region are formed side by side in the D1 direction, the width in the D1 direction of the placement area AR1 Will spread.

  In this regard, in FIG. 30, the diodes DI1 to DI4 are stacked in the D2 direction, and the P-type well region and the N-type well region are also formed in the D2 direction. That is, the first well region (N type) in which the diodes DI1 and DI3 are formed and the second well region (P type) in which the diodes DI2 and DI4 are formed are separately formed in the D2 direction. Therefore, the width of the arrangement area AR1 in the D1 direction can be reduced, and a narrow pad pitch can be handled.

  In FIG. 30, the inter-power supply protection circuit 210 provided between the high-potential side power supply and the low-potential side power supply is arranged on the D2 direction side of the electrostatic protection elements ESD1 and ESD2. In other words, the inter-power supply protection circuit 210 needs to immediately clamp the voltage when a high voltage is applied to protect the transistors in the circuit block, and thus the circuit scale is often large. On the other hand, the inter-power supply protection circuit 210 need not be provided on a one-to-one basis for each output pad of the source driver, unlike the electrostatic protection elements ESD1 and ESD2.

  Therefore, in FIG. 30, the inter-power protection circuit 210 is formed along the outer periphery of the chip of the display driver 60 on the D2 direction side of the electrostatic protection elements ESD1 and ESD2. In this way, it is possible to form a plurality of inter-power supply protection circuits 210, each of which is arranged for each of a plurality of pads, by effectively utilizing the region below the pads. Accordingly, the electrostatic withstand voltage can be improved while minimizing the increase in the chip area of the display driver 60.

  In this embodiment, a source line discharge transistor SdisTr may be provided for each source output instead of the discharge transistor DisTr connected to the common line COL.

  FIG. 32 is an explanatory diagram of a source line discharge transistor.

In FIG. 32, the same parts as those in FIG. The first source output node SND ₁ the voltage of the first to the source line _{S 1} is supplied, the drain of the first source line discharge transistor SdisTr ₁ is connected. The first source of the source line discharge transistor SdisTr _1, a discharge voltage, for example, the system ground power supply voltage VSS is supplied. A control signal diss generated by a control circuit (not shown) is supplied to the gate of the first source line discharge transistor SdisTr ₁ . A first source short circuit switch C2SW ₁ is provided between the first source output node SND ₁ and the source voltage output node SVND.

Similarly to FIG. 32, the drains of the source line discharge transistors are connected to the source output nodes of the _{second to} Nth source output nodes SND _{2 to} SND _N for each source output. The first to Nth source line discharge transistors SdisTr _{1 to} SdisTr _N are ON / OFF controlled by the same control signal diss or a control signal controlled for each source line.

  As shown in FIG. 32, a source short-circuit switch and a source line discharge transistor provided for each source output may be provided in the pad arrangement region.

FIG. 33 shows a layout example of the first source short circuit switch C2SW ₁ and the first source line discharge transistor SdisTr ₁ in the pad arrangement region.

In FIG. 33, the same parts as those of FIG. As shown in FIG. 33, the first source line discharge transistor SdisTr ₁ is arranged under the pad P2 (P1) as the _first source line connection pad S ₁ _P to which the first source line S ₁ is connected. Is done. More specifically, the active region of the _first source line discharge transistor SdisTr ₁ is disposed below the pad P2, and the pad P2 and the active region are disposed so as to at least partially overlap in plan view. .

Then, in FIG. 33, the region near the pad P2, the first source short-circuit switch C2SW ₁ is formed. As described above, the first source line discharge transistor SdisTr ₁ and the first source short-circuit switch C2SW ₁ need only to function as digital switches, and thus do not deteriorate the characteristics in the D2 direction of the chip of the display driver 60. Can be made even smaller.

  Further, in the present embodiment, as described below, the counter electrode charge storage switch CVW may be arranged in the vicinity of the first capacitor element connection pad PD1 as the first capacitor element connection terminal TL1. Good.

  FIG. 34 shows a layout arrangement example of the counter electrode charge storage switch CVW formed in the vicinity of the first capacitor element connection pad PD1.

  In FIG. 34, for the purpose of facilitating understanding of the drawing, illustration of the wiring layer is omitted, and only the active region, the gate electrode, and the pad metal constituting the pad are shown. The first capacitor element connection pad PD1, in which the first capacitor element connection node is electrically connected to the pad arrangement region provided at the long side end portion SD of the chip of the display driver 60, and the counter electrode voltage output A counter electrode connection pad PD2 electrically connected to the node is arranged. The counter electrode connection pad PD2 and the first capacitor element connection pad PD1 are disposed adjacent to each other in the first direction. The counter electrode charge storage switch VSW is disposed adjacent to the first capacitor element connection pad PD1 in the second direction intersecting the first direction. The first capacitor element connection pad PD1 is electrically connected to an N-type transistor and a P-type transistor constituting the common electrode charge storage switch VSW via a wiring layer (not shown).

  In FIG. 34, the N-type transistor constituting the counter electrode charge storage switch VSW is formed in a region where a gate electrode (indicated by G in FIG. 34) is disposed on the active region ACT1. 34, the P-type transistor constituting the counter electrode charge storage switch VSW is formed in a region where a gate electrode (denoted by G in FIG. 34) is disposed on the active region ACT2.

  Further, the formation region of the counter electrode charge storage switch VSW may be formed so that at least a part of the first capacitor element connection pad PD1 (pad metal) overlaps in plan view.

  FIG. 35 shows another example of the layout arrangement of the counter electrode charge storage switch CVW formed in the vicinity of the first capacitor element connection pad PD1.

  In FIG. 35, the same parts as those of FIG. Also in FIG. 35, the counter electrode connection pad PD2 and the first capacitor element connection pad PD1 are disposed adjacent to each other. The counter electrode charge storage switch VSW is disposed below the first capacitor element connection pad PD1 (or the counter electrode charge connection pad PD2).

  By arranging as shown in FIG. 34 or FIG. 35, the length of the connection line between the first capacitor element connection pad PD1 and the counter electrode charge storage switch CVW can be shortened. As a result, current consumption based on charges charged / discharged from the first capacitor element CCV having a large capacity can be reduced. Further, since the increase in the chip area of the display driver 60 can be suppressed even if the size of the transistor constituting the counter electrode charge storage switch CVW is increased, the on-resistance of the counter electrode charge storage switch CVW is reduced, The current consumption based on the charge charged / discharged from the first capacitor element CCV can be further reduced.

  As described above, while the effect of charge reuse using the second capacitor element CCS depends on the display data, the charge is reused when the high potential side voltage VCOMH or the low potential side voltage VCOML is applied. The effect of charge recycling using the capacitive element CCV is extremely high. Therefore, by disposing the counter electrode charge storage switch CVW in the vicinity of or below the first capacitor element connection pad PD1 as the first capacitor element connection terminal TL1, the chip area can be reduced and the charge can be reused. You can get the maximum effect.

5). Modification In the present embodiment, the display driver 60 that drives the display panel 12 shown in FIG. 1 or 2 has been described, but the present invention is not limited to this.

  FIG. 36 shows an outline of another configuration example of the display panel.

36, the same reference numerals are given to the same portions as those in FIG. 1 or FIG. The display panel 200 of FIG. 36 includes a demultiplexer for each source output driven by the display driver. That includes a demultiplexer DMUX _{L + 1} corresponds to correspond to the source line _{S L} demultiplexer DMUX _L, the source line _{S L + 1.} The demultiplexer DMUX divides each source output into three color component source lines. In the display panel 200, the source of the TFT is connected to each color component source line. Therefore, the data voltage corresponding to the display data for 3 dots is output to each source output in a time division manner, so that the demultiplexer DMUX separates the time division multiplexed data voltage and outputs it to each color component source line. Can be made.

  FIG. 37 shows a main part of a display driver that drives the display panel of FIG.

In FIG. 37, the same parts as those in FIG. In the display driver of FIG. 37, a data voltage of 3 dots is time-division multiplexed in advance and inputted to each operational amplifier block. Then, by supplying the time division multiplex timing signal to the display panel 200, each of the demultiplexers DMUX _{1 to} DMUX _N can separate each source output.

Note that the demultiplexers DMUX _{1 to} DMUX _N of FIG. 36 may be provided on the display driver side as shown in FIG. That is, the display driver 202 includes a demultiplexer for separating the time-divided voltage of each source output node into a plurality of output voltages, and supplies each output voltage of the plurality of output voltages to each source line of the display panel. To do. In this case, it is not necessary to supply a time division multiplexed timing signal of the data voltage to the display panel, so that the mounting area can be further reduced.

6). Electronic Device FIG. 39 shows a block diagram of a configuration example of the electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera, and supplies image data captured by the CCD camera to the display controller 540 in the YUV format. The display controller 540 has the function of the display controller 40 of FIG. 1 or FIG.

  The mobile phone 900 includes a display panel 512. The display panel 512 is driven by the source driver 520 and the gate driver 530. The display panel 512 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels. The display panel 512 has the function of the display panel 12 shown in FIG.

  The display controller 540 is connected to the source driver 520 and the gate driver 530 and supplies gradation data in RGB format to the source driver 520.

  The power supply circuit 542 is connected to the source driver 520 and the gate driver 530, and supplies a driving power supply voltage to each driver. The power supply circuit 542 has the function of the power supply circuit 50 in FIG. 1 or FIG. The display driver 544 includes a source driver 520, a gate driver 530, and a power supply circuit 542, and the display driver 544 can drive the display panel 512.

  The host 940 is connected to the display controller 540. The host 940 controls the display controller 540. In addition, the host 940 can supply the gradation data received via the antenna 960 to the display controller 540 after demodulating by the modem 950. The display controller 540 causes the display panel 512 to display the source driver 520 and the gate driver 530 based on the gradation data. The source driver 520 has the function of the source line driver circuit 20 shown in FIG. The gate driver 530 has a function of the gate line driving circuit 30 of FIG. 1 or FIG.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the display panel 512 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a block diagram of a configuration example of a liquid crystal device according to an embodiment. The block diagram of the example of a structure of the other liquid crystal device of this embodiment. FIG. 3 is a block diagram of a configuration example of the source line driver circuit in FIG. 1 or FIG. 2. FIG. 4 is a diagram illustrating a configuration example of a reference voltage generation circuit, a DAC, and an output buffer in FIG. 3. FIG. 3 is a block diagram of a configuration example of a gate line driving circuit in FIG. 1 or FIG. 2. FIG. 3 is a block diagram illustrating a configuration example of a power supply circuit in FIG. 1 or FIG. 2. FIG. 3 is a diagram showing an example of a drive waveform of the display panel of FIG. 1 or FIG. 2. Explanatory drawing of a scanning line inversion drive. FIG. 2 is a principle configuration diagram in a first operation mode of the liquid crystal device of the embodiment. FIG. 10 is a waveform diagram of an operation example of the liquid crystal device of FIG. 9. FIG. 5 is a diagram illustrating a principle configuration in a second operation mode of the liquid crystal device according to the embodiment. FIG. 12 is a waveform diagram of an operation example of the liquid crystal device of FIG. 11. The figure which shows the structural example of the operational amplifier circuit block of FIG. 4, a shared line, and various switches. FIG. 7 is a diagram illustrating a configuration example of the common electrode voltage generation circuit in FIG. 6. The timing diagram of the example of control of the operational amplifier circuit block and various switches in the first operation mode. The timing diagram of the other example of control of an operational amplifier circuit block and various switches in the 1st operation mode. The timing diagram of the example of control of the operational amplifier circuit block and various switches in the second operation mode. The timing diagram of the other example of control of an operational amplifier circuit block and various switches in the 2nd operation mode. The figure which shows the principal part of a structure of the control circuit which the display driver does not illustrate. The figure which shows the outline | summary of a structure of the control register part of FIG. The figure which shows an example of the circuit which produces | generates a control signal in a timing generation part. FIG. 4 is an example of a timing diagram of a control signal, a common line, a counter electrode, and a first source line in the first operation mode. FIG. 10 is an example of a timing diagram of a control signal, a common line, a counter electrode, and a first source line in the second operation mode. FIG. 5 is a timing chart of an operation example of the display driver in the present embodiment. 25A and 25B are schematic cross-sectional views of a twin-well transistor that forms the first source output switch. FIG. 3 is a schematic cross-sectional view of a triple well structure transistor that constitutes a counter electrode charge storage switch. The layout image figure of the chip in which the display driver is formed. The figure which shows the structural example of the operational amplifier circuit block of a source line drive circuit. The figure which shows the structural example of the operational amplifier circuit block of a source line drive circuit. The figure which shows the example of a layout of a pad arrangement | positioning area | region. FIG. 31A illustrates an example of an electrostatic protection element provided between power supplies. FIG. 31B is a diagram showing a connection relationship among the pad, the diode, and the control transistor in FIG. Explanatory drawing of a source line discharge transistor. The figure which shows the layout example of the 1st source short circuit switch and the 1st source line discharge transistor in a pad arrangement | positioning area | region. The figure which shows the example of a layout arrangement | positioning of the counter electrode charge storage switch formed in the vicinity area | region of the 1st capacitive element connection pad. FIG. 10 is a diagram showing another example of the layout arrangement of the counter electrode charge storage switch formed in the vicinity of the first capacitor element connection pad. The figure which shows the outline | summary of the other structural example of a display panel. FIG. 37 is a diagram showing a configuration main part of a display driver that drives the display panel of FIG. 36. FIG. 37 is a diagram showing another configuration main part of a display driver that drives the display panel of FIG. 36; 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal device, 20 source line driving circuit, 30 gate line driving circuit,
40 display controller, 50 power supply circuit, 60 display driver,
BSW _{1 to} BSW _N 1st to Nth bypass switches,
C1ND first capacitor element connection node;
c1, xc1, c2, xc2, cc, xcc, ch, xchcs, xcs, cv, xcv, dis, POLc, XPOLc control signal, C2ND second capacitor element connection node,
C2SW _{1 to} C2SW _N 1st to Nth source short-circuit switches,
CCS second capacitor element, CCV first capacitor element, CE counter electrode,
COL common line, CSW source charge storage switch,
DisTr discharge transistor, _G 1 ~G _M gate lines,
HSW node short-circuit switch, OP1, OP2 operational amplifier,
OPC ₁ ~OPC _N operational amplifier circuit block, _S 1 to S _N source line,
SEL switching circuit, SND ₁ first source output node,
SS _{1 to} SS _N first to Nth source output switches,
SSW _{1 to} SSW _N first to Nth source output switching circuits,
SVND source voltage output node, TL1 first capacitor element connection terminal,
TL2 second capacitor element connection terminal, TL3 counter electrode voltage output terminal,
VCOM counter electrode voltage, VND counter electrode voltage output node,
Operational amplifiers connected to VOP _{1 to} VOP _N voltage followers,
VSS System ground power supply voltage, VSW Counter electrode charge storage switch

Claims (14)

A display driver for driving an electro-optical device,
A first capacitor element connection node to which one end of the first capacitor element can be connected and a counter electrode voltage output node to which a voltage of a counter electrode facing the pixel electrode of the electro-optical device is supplied via an electro-optical material A counter electrode charge storage switch provided therebetween;
A source charge storage switch provided between a second capacitor element connection node to which one end of the second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied;
A node short-circuit switch provided between the counter electrode voltage output node and the source voltage output node;
A common line electrically connected to the source voltage output node and having one end electrically connected to the source charge storage switch;
A first source short-circuit switch provided between a first source output node to which an output voltage to the first source line of the electro-optical device is supplied and the shared line;
A second source short-circuit switch provided between the second source output node to which an output voltage to the second source line of the electro-optical device is supplied and the shared line;
A discharge transistor connected to the common line,
The discharging transistor is
A display driver shared for discharging the first and second source lines. In claim 1,
In the selection period of the pixel electrode of the electro-optical device, the first and second source lines are discharged by the discharging transistor in a state where the first and second source short-circuit switches are set in a conductive state. Display driver. In claim 1 or 2,
A counter electrode voltage generating circuit for generating the counter electrode voltage;
A source line driving circuit for driving the first or second source line of the electro-optical device based on display data,
In the first operation mode,
After setting the outputs of the source line driving circuit and the common electrode voltage generation circuit to a high impedance state and electrically connecting the source voltage output node and the common electrode voltage output node, the source voltage output node and In a state where the counter electrode voltage output node is electrically disconnected,
The source line driving circuit supplies a voltage corresponding to display data to the first or second source line, and the counter electrode voltage generation circuit supplies the counter electrode voltage to the counter electrode. Display driver. In claim 3,
In the second operation mode,
The first or second source output node and the second capacitor element connection node are electrically connected in a state where the output of the source line driving circuit is set to a high impedance state, and then the first or second source output node is electrically connected. The source line driving circuit supplies a voltage corresponding to display data to the first or second source line in a state where the two source output nodes and the second capacitor element connection node are electrically cut off. ,
With the output of the common electrode voltage generation circuit set to a high impedance state, the common electrode voltage output node and the first capacitor element connection node are electrically connected by the common electrode charge storage switch, The display, wherein the counter electrode voltage generation circuit supplies the counter electrode voltage to the counter electrode in a state where the counter electrode voltage output node and the first capacitor element connection node are electrically cut off. driver. In any one of Claims 1 thru | or 4,
A demultiplexer for separating the time-divided voltage at each source output node into a plurality of output voltages;
A display driver, wherein each output voltage of the plurality of output voltages is supplied to each source line of the electro-optical device. Multiple source lines,
Multiple gate lines,
A plurality of pixel electrodes in which each pixel electrode is specified by each gate line and each source line;
A counter electrode facing the plurality of pixel electrodes;
A common electrode charge storage switch provided between a first capacitive element connection node to which one end of the first capacitive element can be connected and a common electrode voltage output node to which a common electrode voltage applied to the common electrode is supplied When,
A common line electrically connected to a second capacitor element connection node to which one end of the second capacitor element can be connected;
A node short-circuit switch provided between the common electrode voltage output node and the shared line;
A first source short circuit switch provided between a first source output node to which an output voltage to the first source line of the plurality of source lines is supplied and the shared line;
A second source short-circuit switch provided between a second source output node to which an output voltage to a second source line of the plurality of source lines is supplied and the shared line;
An electro-optical device comprising: a source charge storage switch provided between the shared line and the second capacitor element connection node. In claim 6,
In the first mode of operation,
With the common electrode charge storage switch and the source charge storage switch set in a non-conductive state, the node short circuit switch is once set in a conductive state, and then the common electrode voltage is supplied to the common electrode voltage output node. And driving the counter electrode and supplying the voltage corresponding to display data to the first or second source line to drive the first or second source line. . In claim 6 or 7,
In the second mode of operation,
With the node short-circuit switch set to a non-conductive state,
After the common electrode voltage output node and the first capacitor element connection node are electrically connected once by the common electrode charge storage switch, the common electrode voltage output node and the first capacitor node are electrically connected by the common electrode charge storage switch. Driving the counter electrode by supplying the counter electrode voltage to the counter electrode voltage output node in a state where the capacitor element connection node is electrically cut off,
After the source charge storage switch electrically connects the shared line and the second capacitor element connection node, the source charge storage switch connects the shared line and the second capacitor element connection node. An electro-optical device that drives the first or second source line by supplying a voltage corresponding to display data to the first or second source line in a state of being electrically cut off. In claim 8,
A period in which the common electrode voltage output node and the first capacitor element connection node are electrically connected, and the first or second source output node and the second capacitor element connection node are electrically connected. An electro-optical device, characterized in that the period to be overlapped. In any one of Claims 6 thru | or 9.
A discharge transistor connected to the common line,
The discharging transistor is
An electro-optical device that is commonly used for discharging the first and second source lines. In claim 10,
In the selection period of the pixel electrode, the first and second source lines are discharged by the discharging transistor in a state where the first and second source short-circuit switches are set in a conductive state. Optical device. In any of claims 6 to 11,
A demultiplexer for separating the time-divided voltage at each source output node into a plurality of output voltages;
An electro-optical device, wherein each output voltage of the plurality of output voltages is supplied to each source line.   An electro-optical device comprising the display driver according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 6.

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