JP2007325031A - Image processor, and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor that achieves decoding of encoded image data corresponding to magnification or reduction without requiring a large-capacity buffer memory, even when reduction or magnification of a display image is required. <P>SOLUTION: The image processor 1 is provided with a decoder 2 which decodes the encoded image data so as to generate decoded pixel data, a display processor 3 which generates display pixel data used for display on the basis of a pixel clock specifying a time interval required for display of one pixel data while using the decoded pixel data, a control unit 4 for controlling operation of the decoder 2 and display processor 3, and a decoding control unit 5 that controls the number of the decoded pixel data generated by the decoder 2 in a unit time defined by the pixel clock. The display processor 3 executes reduction processing for reducing the display image with respect to a normal image and/or magnification processing for magnifying the display image with respect to the normal image. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image processing apparatus and an image display method for decoding encoded image data and displaying the decoded image on a display unit.

  In recent years, recording media such as a digital versatile disk (hereinafter referred to as “DVD”) and a hard disk drive (hereinafter referred to as “HDD”) that record encoded data obtained by encoding an image signal and an audio signal have become widespread. An image processing apparatus that decodes encoded image data recorded on such a recording medium and displays the decoded image on a display unit is required.

  The encoded image data recorded on the recording medium is decoded by a decoding method corresponding to the encoding method, and decoded pixel data is generated. The generated decoded pixel data is generated as display pixel data at regular time intervals in order to be displayed on an actual display unit. The display pixel data is assigned to a display position in the display unit, and a picture, a frame, and a field that are a unit of image display are formed.

  At this time, in image display, the time required to display a picture or frame as a unit of image display is determined (for example, it is necessary to display 30 frames of pictures or frames per second). The generation speed of the necessary display pixel data is constant (that is, the time required for reproducing the display pixel is determined, and the time required for generating the display pixel is determined accordingly). That is, the time interval required to generate one display pixel data corresponds to the display interval of one display pixel data in a picture or frame. It is the pixel clock that defines the display interval (that is, the unit time required for generation).

  Here, when the displayed image has the same image size determined from the number of decoded pixel data corresponding to one frame or one picture (in this specification, such an image is referred to as a “normal image”). No problem occurs. That is, since the decoded pixel data need only be used as display pixel data as it is, the decoded pixel data is generated at the same speed as the pixel clock when decoding the image data (that is, when generating the decoded pixel data). Just do it.

  However, in the image display, there are many requests for displaying the image by reducing or enlarging the image size compared to the normal image.

  For example, in order to cope with the difference between the NTSC system and the PAL system, it is necessary to reduce (or enlarge) the image size for display.

  Alternatively, when movie data is recorded on a recording medium, sub-images such as subtitles and explanations may be recorded for main images that are actual images. At this time, it is often necessary to reduce and display the sub-image with respect to the main image.

  When reducing the display image, the number of display pixel data with respect to the decoded pixel data is reduced by thinning out or synthesizing the decoded pixel data. At this time, as described above, the pixel clock, which is the time required for generating the display pixel data, is constant, so it is necessary to increase the generation speed of the decoded pixel data. That is, it is necessary to decode image data encoded at a speed higher than the pixel clock.

  Conversely, when enlarging, it is necessary to generate display pixel data by interpolating the decoded pixel data, and to generate more display pixel data than in the case of a normal image. In the interpolation, the same decoded pixel data is used for both the display pixel data and the display pixel data positioned next to the display pixel data. Therefore, the generation speed of the decoded pixel data is higher than the pixel clock that is the generation speed of the display pixel data. It needs to be slow.

  In order to cope with such reduction and enlargement, the conventional technique includes a buffer memory having a sufficient size between the decoding process and the display process (see, for example, Patent Document 1).

  However, the conventional technique using this buffer memory has the following problems.

  One problem is that the capacity of the buffer memory increases.

  In particular, when dealing with enlargement, the buffer memory needs to store the decoded decoded pixel data. At this time, in the NTSC system, one frame or one picture has data of a maximum of 720 × 480 pixels, and one pixel data has 8-bit information for luminance and color difference. For this reason, when storing decoded pixel data of one frame or one picture, a buffer memory of 1 Mbytes or more is required. Of course, the same applies to the case of reduction because the decoded pixels are filtered to generate display pixels.

  If such a very large buffer memory is provided, the influence on the circuit scale, power consumption, and cost becomes very large.

  In addition, when the image processing apparatus is realized by an LSI, when the buffer memory is configured to be connected to another semiconductor element from the LSI, it relates to the decoded pixel data between the LSI and the buffer memory. There is a problem that the bandwidth required for data transfer increases. An increase in bandwidth results in an increase in the number of LSI terminals, which adversely affects circuit scale and cost. In addition, the processing load required for data transfer affects the processing speed inside the image processing apparatus.

In addition, there is a problem that the timing setting for image display becomes complicated in the exchange of data with the buffer memory.
Japanese Patent Application Laid-Open No. 2002-335496

  Therefore, the present invention provides an image that realizes decoding of encoded image data corresponding to enlargement / reduction without requiring a large-capacity buffer memory even when the display image needs to be reduced / enlarged. An object is to provide a processing apparatus.

  An image processing apparatus according to a first aspect of the invention defines a time interval required to display one pixel using a decoding unit that decodes encoded image data and generates decoded pixel data, and the decoded pixel data. A display processing unit that generates display pixels to be used for display based on a pixel clock, a control unit that controls operations of the decoding unit and the display processing unit, and a decoding unit that is generated in a unit time defined by the pixel clock. A decoding control unit that controls the number of decoded pixel data is provided, and the display processing unit reduces the display image size with respect to the normal image and / or enlarges the display image size with respect to the normal image. I do.

  With this configuration, even if the numbers of display pixel data and decoded pixel data generated per unit time are different, display pixel data and decoded pixel data can be generated at different generation speeds. For this reason, the reduced image and the enlarged image of the encoded image data can be displayed without providing an extra buffer memory.

  In the image processing apparatus according to the second invention, in addition to the first invention, the decoding unit operates based on the system clock, and the system clock has a frequency multiplied by the pixel clock.

  With this configuration, it is possible to decode the encoded image data without delaying the time specified for image display.

  In the image processing apparatus according to the third invention, in addition to any of the first to second inventions, the display processing unit includes a filter that filters the decoded pixel data to generate display pixel data.

  With this configuration, the display image can be easily reduced and enlarged.

  In the image processing apparatus according to the fourth invention, in addition to the third invention, in the reduction process, the filter generates one display pixel data by using a plurality of decoded pixel data.

  With this configuration, the display image can be easily reduced using the decoded pixel data.

  In the image processing device according to the fifth invention, in addition to any of the first to fourth inventions, in the reduction process, the decoding control unit decodes a larger number of pixels than the display pixel data generated in unit time. A control signal for controlling the pixel data to be generated is generated and output to the decoding unit, and the decoding unit generates decoded pixel data according to the control signal.

  With this configuration, it is possible to generate decoded pixel data necessary for reduced display without affecting the speed of the pixel clock determined based on the image display.

  In the image processing apparatus according to the sixth aspect, the control signal includes a processing clock signal, and the processing clock has a frequency multiplied by the pixel clock.

  With this configuration, it is possible to generate a larger number of decoded pixel data than the number of display pixel data per unit time without changing the pixel clock speed.

  In the image processing apparatus according to the seventh invention, in addition to the fifth invention, the control signal includes an enable signal, and the enable signal is valid for a plurality of effective periods with respect to the system clock in one period of the pixel clock. Have

  With this configuration, it is possible to generate a larger number of decoded pixel data than the number of display pixel data per unit time without changing the pixel clock speed.

  In the image processing apparatus according to the eighth invention, in addition to the third invention, in the enlargement process, the filter interpolates the decoded pixel data to generate display pixel data.

  With this configuration, the display image can be easily enlarged using the decoded pixel data.

  In the image processing device according to the ninth invention, in addition to any of the first to fourth inventions, in the enlargement process, the decoding control unit has a smaller number of decoded pixels than the display pixel data generated in unit time. A control signal for controlling data to be generated is generated and output to the decoding unit, and the decoding unit generates decoded pixel data according to the control signal.

  With this configuration, it is possible to generate decoded pixel data necessary for enlarged display without affecting the pixel clock speed determined based on the image display.

  In the image processing apparatus according to the tenth invention, in addition to the ninth invention, the control signal includes a processing clock signal, and the processing clock has a frequency divided by the pixel clock.

  With this configuration, it is possible to generate a smaller number of decoded pixel data than the number of display pixel data per unit time without changing the pixel clock speed.

  In the image processing apparatus according to the eleventh invention, in addition to the ninth invention, the control signal includes an enable signal, and the enable signal is effective once per system clock in a period obtained by dividing the pixel clock. Have

  With this configuration, it is possible to generate a smaller number of decoded pixel data than the number of display pixel data per unit time without changing the pixel clock speed.

  In addition to the eighth invention, the image processing device according to the twelfth invention further includes a storage unit that temporarily stores the decoded pixel data decoded by the decoding unit. In the enlargement process, the filter includes a storage unit Interpolation in the vertical direction of the image to be displayed is performed using the decoded pixel data stored in.

  With this configuration, an enlarged image can be displayed in the vertical direction.

  In addition to any of the first to twelfth inventions, the image processing apparatus according to the thirteenth invention further includes a display unit that displays an image using display pixel data.

  With this configuration, an actual image can be displayed.

  In the image processing device according to the fourteenth invention, in addition to the thirteenth invention, in the case of a reduction process, the decoding control unit instructs to generate decoded pixel data during a non-display period on the display unit. Is output to the decoding unit.

  With this configuration, even when the reduction ratio is very high, a larger number of decoded pixel data than the number of display pixel data per unit time based on the pixel clock can be generated without delaying the display.

  According to the present invention, a large-capacity buffer memory is not required between the decoding unit and the display processing unit, and display of a reduced image and an enlarged image can be realized without affecting the display speed.

  In addition, an image enlarged in the vertical direction can be displayed with a minimum storage unit.

  Furthermore, it is possible to decode and display a main image and a sub image having different reduction ratios and enlargement ratios in display, and display an image in which the sub image is superimposed on the main image.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram of an image processing apparatus according to Embodiment 1 of the present invention.

  The image processing apparatus 1 includes a decoding unit 2, a display processing unit 3, a control unit 4, and a decoding control unit 5.

  In addition, a storage unit 7 that stores encoded image data and a display unit 8 that displays an actual image using display pixel data are connected to the outside of the image processing apparatus 1. The storage unit 7 may be provided inside the image processing apparatus 1. Further, when the image processing apparatus 1 is realized by a semiconductor integrated circuit such as an IC or an LSI, it is preferable from the viewpoint of miniaturization.

(Overview of the whole)
The encoded image data stored in the storage unit 7 is read out and decoded by the decoding unit 2 to generate decoded pixel data. The display processing unit 3 generates display pixel data used for display using the decoded pixel data, and outputs the generated display pixel data to the display unit 8.

  Here, the decoding control unit 5 controls the number of decoded pixel data generated by the decoding unit in a unit time required for generating display pixel data.

  For example, when the normal image is reduced and displayed (in this specification, such an image is referred to as a “reduced image”), the decoding control unit 5 performs two or more pieces of decoded pixel data in one cycle of the pixel clock. To be generated. When a normal image is displayed in an enlarged manner (in this specification, such an image is referred to as an “enlarged image”), the decoding control unit 5 has one decoded pixel data in a period longer than one cycle of the pixel clock. To be generated. Alternatively, when the image is displayed as a normal image, control is performed so that decoded pixel data is generated at the same cycle as the pixel clock.

  Since the decoding pixel required for the display pixel by the decoding control unit 5 is generated in accordance with the generation speed of the display pixel, no extra buffer memory is required.

  Using the display pixel data generated in this way, the display unit 8 displays an actual image.

(Details of each part)
(Decryption unit)
First, the decoding unit 2 will be described.

  The decoding unit 2 decodes the encoded image data read from the storage unit 7 using a decoding method corresponding to the encoding method, generates decoded pixel data, and outputs the decoded pixel data to the display processing unit 3.

  The decoding unit 2 reads out the encoded image data from the storage unit 7 and decodes it. For this reason, the decoding unit 2 also has a read control function necessary for reading image data from the storage unit 7.

  Image data encoding methods include MPEG2, MPEG4, H.264, and the like. 263, H.M. There are image compression methods such as H.264. Of course, these are only examples, and other encoding methods may be used. For this reason, the decoding unit 2 performs decoding schemes corresponding to these encoding schemes, that is, MPEG2, MPEG4, H.264. 263, H.M. The encoded image data is decoded using a decoding method corresponding to H.264 or the like.

  The decoding unit 2 also performs error detection and error correction of decoded pixel data generated by decoding as necessary.

  Note that the decoding unit 2 operates based on a system clock having a frequency multiplied by a pixel clock described later. Since the system clock has a frequency that is a multiple of the pixel clock, the system clock may have the same frequency as the pixel clock. Further, the system clock may be frequency-divided and used by the decoding unit 2 in accordance with a reduction process or an enlargement process in the display processing unit 3.

  The decoding unit 2 outputs the decoded pixel data to the display processing unit 3.

(Display processing part)
Next, the display processing unit 3 will be described.

  The display processing unit 3 uses the decoded pixel data to generate display pixel data used for display based on the pixel clock. The generated display pixel data is output to the display unit 8, and the display unit 8 displays an actual image. Here, the pixel clock is a clock having a time period that defines a display interval of one pixel in display. In image display, since the update speed of one frame or picture is determined, this pixel clock is constant. When the image display is displayed in a progressive manner, the pixel clock frequency is 27 MHz.

  The display processing unit 3 outputs the generated display pixel data to the display unit 8, and the display unit 8 displays an actual image using the display pixel data. As the display unit 8, a liquid crystal panel, an organic EL panel, a CRT, or the like is used.

  The display processing unit 3 may reduce or enlarge the size of the display image by comparing the display image with the normal image. Of course, there is a case where display pixel data for displaying a normal image as it is is generated.

  Here, the display processing unit 3 performs processing for generating display pixel data corresponding to a normal image as “normal processing”, processing for generating display pixel data corresponding to a reduced image as “reduction processing”, and enlarges the image. Processing for generating corresponding display pixel data is referred to as “enlargement processing”.

  The filter 6 included in the display processing unit 3 performs the normal process, the reduction process, and the enlargement process.

  When normal processing is performed in the display processing unit 3, an image having the same size as the normal image is displayed on the display unit 8. When the reduction processing is performed in the display processing unit 3, an image smaller than the normal image is displayed on the display unit 8. When the enlargement processing is performed, the normal image is displayed on the display unit 8. A larger image is displayed.

  The display processing unit 3 uses the filter 6 to generate display pixel data using the decoded pixel data. The filter 6 combines the decoded pixel data to generate display pixel data. At this time, display pixel data is generated from a plurality of decoded pixel data.

  In the case of normal processing, the display processing unit 3 generates the same number of display pixel data as the decoded pixel data input to the filter 6. In the case of the reduction process, the display processing unit 3 generates a smaller number of display pixel data than the decoded pixel data input to the filter 6. In the case of the enlargement process, the display processing unit 3 generates a larger number of display pixel data than the decoded pixel data input to the filter 6.

  The processing of the filter 6 will be described with reference to FIG.

  FIG. 2 is an exemplary diagram of the filter processing in the first embodiment of the present invention. The content described with reference to FIG. 2 is merely an example, and other processing methods may be used.

  In order to simplify the explanation, three processes, a normal process (FIG. 2A), a reduction process (FIG. 2B), and an enlargement process (FIG. 2C) are shown in one drawing. . Originally, the time interval related to display between display pixels has the same time interval regardless of normal processing, reduction processing, and enlargement processing (for example, the time of display pixel data 1 and display pixel data 2 in normal processing). The time interval between the display pixel data 1 and the display pixel data 2 in the enlargement processing is the same), and the time interval between the decoded pixel data has different time intervals depending on the normal processing, reduction processing, and enlargement processing. However, in FIG. 2, in order to explain the three processes with one figure, the time interval of the decoded pixel data is apparently constant, and the time interval of the display pixel data is apparently non-uniformly displayed. However, this is for the convenience of explanation in FIG. 2, and in fact, as shown in FIGS. 3 to 8, the time interval between display pixels is the same regardless of the reduction process, the normal process, and the enlargement process. The time interval between the decoded pixels is different.

  In FIG. 2, four pieces of decoded pixel data of decoded pixel data 1 to 4 are shown. The display processing unit 3 generates display pixel data using the four decoded pixel data 1 to 4 by the filter 6.

  First, normal processing will be described.

  In the normal process, the filter 6 generates the same number of display pixel data as the decoded pixel data.

  As shown in FIG. 2A, the filter 6 performs decoding pixel data synthesis processing, and generates display pixel data 1 from the decoded pixel data 1 and the decoded pixel data 2. Similarly, the filter 6 generates display pixel data 2 from the decoded pixel data 2 and decoded pixel data 3, and generates display pixel data 3 from the decoded pixel data 3 and decoded pixel data 4. As a result, the filter 6 generates the same number of display pixel data as the decoded pixel data.

  Next, the reduction process will be described. In the reduction process, the filter 6 generates display pixel data whose number is smaller than the number of decoded pixel data.

  As shown in FIG. 2B, the filter 6 generates display pixel data 1 from the decoded pixel data 1 and the decoded pixel data 2. Further, the filter 6 generates display pixel data 2 from the decoded pixel data 3 and the decoded pixel data 4. As a result, the filter 6 generates display pixel data whose number is smaller than the number of decoded pixel data. In FIG. 2, the number of display pixel data is half the number of decoded pixel data.

  Next, the enlargement process will be described. In the enlargement process, the filter 6 generates a larger number of display pixel data than the number of decoded pixel data.

  As shown in FIG. 2C, the filter 6 generates display pixel data 1 and display pixel data 2 from the decoded pixel data 1 and the decoded pixel data 2. Here, the contribution ratio of the decoded pixel data 1 and the decoded pixel data 2 in the generation of the display pixel data 1 and the contribution ratio of the decoded pixel data 1 and the decoded pixel data 2 in the generation of the display pixel data 2 may be different. Alternatively, the display pixel data 2 may be a copy of the display pixel data 1.

  Similarly, the filter 6 generates display pixel data 3 and display pixel data 4 from the decoded pixel data 2 and decoded pixel data 3, and displays pixel data 5 and display pixel data from the decoded pixel data 3 and decoded pixel data 4. 6 is generated. As a result, in the enlargement process, the filter 6 generates display pixel data that is twice the number of decoded pixel data.

  The display processing unit 3 uses the filter 6 to perform normal processing for displaying the display image as a normal image having the same size, reduction processing for displaying the display image as a reduced image having a size smaller than the normal image, and display the display image. An enlargement process for displaying an enlarged image having a size larger than that of the normal image is performed.

  The display unit 8 displays any one of a normal image, a reduced image, and an enlarged image based on the display pixel data received from the display processing unit 3.

(Control part)
Next, the control unit 4 will be described.

  The control unit 4 controls the operations of the decoding unit 2 and the display processing unit 3. The control unit 4 includes a central processing unit (hereinafter referred to as “CPU”), a ROM, and a RAM, and controls the operations of the decoding unit 2 and the display processing unit 3 in accordance with programs stored in the ROM and RAM. For example, the control unit 4 adds an inverse quantization coefficient in decoding by the decoding unit 2 and adds a detection expression for error detection. Alternatively, the control unit 4 instructs the display processing unit 3 to perform normal processing, reduction processing, or enlargement processing.

(Decryption control unit)
Next, the decoding control unit 5 will be described.

  The decoding control unit 5 controls the number of decoded pixel data generated by the decoding unit 2 in a unit time based on the pixel clock.

(Decryption control for normal processing)
First, the operation of the decoding control unit 5 in the case of normal processing will be described.

  When the normal processing is performed in the display processing unit 3, the decoding control unit 5 controls the decoding unit 2 so as to generate the same number of decoded pixel data as the display pixel data within this unit time. In the case of normal processing, since a normal image that is an image having a size determined by the number of decoded pixel data is displayed, the decoding unit 2 generates display pixels generated every one cycle of the pixel clock defined by the display speed. This is because it is necessary to generate decoded pixel data in accordance with the data generation speed.

  The case of this normal process will be described with reference to FIGS.

  3 and 4 are timing charts showing generation of decoded pixel data in normal processing in Embodiment 1 of the present invention.

  In FIG. 3, the system clock is a common clock signal used in the image processing apparatus 1 including the decoding unit 2. The pixel clock is a clock signal that defines a time interval required to display one pixel data determined by a display speed when displaying an image, and defines a generation interval of display pixel data. Display pixel data is generated according to this pixel clock. The processing clock 20 is one type of control signal generated by the decoding control unit 5, and the decoded pixel data is generated based on the processing clock 20. The enable signal in FIG. 4 is one type of this control signal.

  In normal processing, decoded pixel data may be generated in accordance with the generation speed of display pixel data (that is, the same number of decoded pixel data as the generated display pixel data is generated in a unit time based on the pixel clock). )

  The display pixel data is generated based on the pixel clock, and is generated in synchronization with the rising edge of the pixel clock in FIGS. That is, one display pixel data is generated in one cycle of the pixel clock.

  The processing clock 20 has the same cycle as the pixel clock. The processing clock 20 generated by the decoding control unit 5 is used by the decoding unit 2. The decoding unit 2 generates decoded pixel data in synchronization with the rising edge of the processing clock 20. For this reason, in the unit time, the same number of decoded pixel data as the display pixel data is generated.

  Display pixel data 1 is generated from decoded pixel data 0 (not shown) and decoded pixel data 1, display pixel data 2 is generated from decoded pixel data 1 and decoded pixel data 2, and display pixel data 3 is decoded. It is generated from pixel data 2 and decoded pixel data 3. A 2-tap filter may be used.

  Further, as shown in FIG. 4, decoded pixel data may be generated using the enable signal 21 as a control signal.

  The enable signal 21 has an effective period of one time with respect to the system clock in one period of the pixel clock. The decoding unit 2 generates decoded pixel data based on the enable signal 21 and the system clock. Specifically, the decoding unit 2 generates decoded pixel data at a timing when both the rising edge of the system clock and the high level (valid period) of the enable signal are satisfied.

  Also with this enable signal 21, the decoding unit 2 generates the same number of decoded pixel data as the display pixel data in a unit time.

  With the above processing, decoded pixel data can be generated in accordance with the generation speed of display pixel data, and no extra buffer memory is required between the decoding unit 2 and the display processing unit 3. Furthermore, the display unit 8 can display a normal image using the generated display pixel data.

(Decryption control for reduction processing)
Next, the operation of the decoding control unit 5 in the case of the reduction process will be described.

  When the reduction processing is performed in the display processing unit 3, the decoding control unit 5 controls the decoding unit 2 so as to generate a larger number of decoded pixel data than the display pixel data within this unit time. In the case of the reduction process, one display pixel data generated every one cycle of the pixel clock is generated from a plurality of decoded pixel data. Therefore, within one cycle of the pixel clock, the decoding unit 2 This is because it is necessary to generate decoded pixel data.

  The reduction process will be described with reference to FIGS.

  5 and 6 are timing charts showing generation of decoded pixel data in the reduction process according to Embodiment 1 of the present invention.

  In the reduction process, an image is displayed using a smaller number of display pixel data than the number of decoded pixel data corresponding to a normal image. Here, the generation of display pixel data is constant by the pixel clock which is the time interval of image display, and therefore the generation speed of decoded pixel data needs to be increased.

  As in normal processing, display pixel data is generated in synchronization with the rising edge of the pixel clock. That is, one display pixel data is generated in one period of the pixel clock.

  First, the process in which decoded pixel data is generated by the processing clock 22 having a cycle of pixel clock multiplication will be described with reference to FIG.

  The processing clock 22 is one type of control signal generated by the decoding control unit 5 and is a clock signal having a cycle of multiplying the pixel clock. In FIG. 5, it has a period twice that of the pixel clock.

  The decoding unit 2 generates decoded pixel data based on the processing clock 22. Specifically, decoded pixel data is generated in synchronization with the rising edge of the processing clock. For this reason, the number of decoded pixel data that is twice the number of display pixel data generated in unit time is generated.

  That is, six pieces of decoded pixel data of decoded pixel data 1 to 6 are generated while three pieces of display pixel data of display pixel data 1 to 3 are generated. If the pixel clock is used as a reference, six decoded pixel data are generated during three periods of the pixel clock.

  Display pixel data 1 is generated by combining decoded pixel data 0 (not shown) and decoded pixel data 1. Display pixel data 2 is generated by combining decoded pixel data 2 and decoded pixel data 3. Display pixel data 3 is displayed by combining decoded pixel data 4 and decoded pixel data 5. As a result, three display pixel data are generated from the six decoded pixel data, resulting in display pixel data having a reduced number of pixels compared to the number of pixel data of the normal image, thereby realizing a reduced image. A display pixel may be generated by a 2-tap filter for the decoded pixel.

  Next, generation of decoded pixel data using an enable signal will be described with reference to FIG.

  The enable signal 23 is an enable signal having a valid period of a plurality of times (twice in FIG. 6) in one cycle of the pixel clock.

  The decoding unit 2 generates decoded pixel data at a timing when the enable signal 23 is in a valid period (High period in FIG. 6) in synchronization with the rising edge of the system clock. As a result, in FIG. 6, two decoded pixel data are generated during one cycle of the pixel clock, and finally, the decoded pixel data whose number is twice that of the display pixel data is generated.

  Through the above processing, it is possible to generate a larger number of decoded pixel data than the number of display pixel data generated by a pixel clock that defines a display interval of one pixel, and display pixel data having a number smaller than the number of decoded pixel data. And a reduced image can be generated. Note that the time intervals of the processing clock and the enable signal do not always have to be constant, and may change according to the design specifications. In the first embodiment, the reduction process has been described by taking a reduction of half in the horizontal direction as an example. However, the time interval of the processing clock and the enable signal changes according to the reduction ratio.

(Decryption control for enlargement processing)
Next, decoding control in the case of enlargement processing will be described with reference to FIGS.

  7 and 8 are timing charts showing generation of decoded pixel data in the enlargement process according to the first embodiment of the present invention. In the enlargement process, the generation time interval of the decoded pixel data is longer than that in the case of the normal process and the reduction process. Is described.

  In the enlargement process, an image is displayed with a larger number of display pixel data than the number of decoded pixel data corresponding to a normal image. Here, the generation of the display pixel data is constant by the pixel clock that is the time interval of image display, and therefore the generation speed of the decoded pixel data needs to be slowed down. This is because one decoded pixel data is commonly used in the generation of a plurality of display pixel data.

  As in normal processing, display pixel data is generated in synchronization with the rising edge of the pixel clock. That is, one display pixel data is generated in one period of the pixel clock.

  First, it will be described with reference to FIG. 7 that decoded pixel data is generated by the processing clock 24 having a period obtained by dividing the pixel clock.

  The processing clock 24 is one type of control signal generated by the decoding control unit 5 and is a clock signal having a cycle obtained by dividing the pixel clock. In FIG. 7, it has a half period of the pixel clock.

  The decoding unit 2 generates decoded pixel data based on the processing clock 24. Specifically, decoded pixel data is generated in synchronization with the rising edge of the processing clock. Therefore, half the number of decoded pixel data of display pixel data generated in a unit time is generated.

  Display pixel data 1 is generated by combining decoded pixel data 1 and decoded pixel data 2. Display pixel data 2 is generated by combining decoded pixel data 1 and decoded pixel data 2. That is, the decoded pixel data 1 is used to generate both display pixel data 1 and display pixel data 2. The decoding process of the decoded pixel data 3 so that the decoded pixel data 1 and the decoded pixel data 2 are held until the display pixel data 2 is output so that the display pixel data 1 and the display pixel data 2 are generated. The time is controlled. As a result, the decoded pixel data 1 is held without being overwritten with the decoded pixel data 3, so that the display pixel data 2 is accurately generated. Moreover, although both the display pixel data 1 and the display pixel data 2 are generated from both the decoded pixel data 1 and the decoded pixel data 2, the ratio at the time of synthesis may be changed. Since these are generated from a 2-tap filter, they can be realized by changing the filter coefficient.

  Next, generation of decoded pixel data using an enable signal will be described with reference to FIG.

  The enable signal 25 is an enable signal having one effective period between a plurality of periods (two periods in FIG. 8) of the pixel clock.

  The decoding unit 2 generates decoded pixel data at a timing when the enable signal 25 is in a valid period (High period in FIG. 8) in synchronization with the rising edge of the system clock. As a result, in FIG. 8, one decoded pixel data is generated during two periods of the pixel clock, and finally, decoded pixel data whose number is half of the display pixel data is generated.

  Through the above processing, it is possible to generate a smaller number of decoded pixel data than the number of display pixels generated by a pixel clock that defines the display interval of one pixel, and to generate display pixel data that is larger than the number of decoded pixel data. Thus, an enlarged image can be generated.

  With the image processing apparatus 1 described in the first embodiment, a large-capacity buffer memory is not required between the decoding unit 2 and the display processing unit 3, and a reduced image and an enlarged image are displayed without affecting the display speed. Can be realized. In the first embodiment, it has been described that a display pixel is generated from a decoded pixel using a 2-tap filter. However, this is an example, and a display pixel is generated from a filter of 3 taps or more. It may be.

(Embodiment 2)
Next, a second embodiment will be described.

  In addition to the functions of the image processing apparatus described in the first embodiment, the image processing apparatus described in the second embodiment has a storage unit 10 for vertical interpolation in the enlargement process.

  FIG. 9 is a block diagram of an image processing apparatus according to the second embodiment of the present invention, and FIG. 10 is an explanatory diagram for explaining vertical interpolation according to the second embodiment of the present invention.

  The storage unit 10 temporarily stores the decoded pixel data decoded by the decoding unit 2. The capacity of the storage unit 10 may be arbitrarily determined, but a capacity for storing decoded pixel data for one horizontal line necessary for vertical interpolation in enlargement processing is required at a minimum. The display processing unit 3 performs vertical interpolation using both the decoded pixel data output from the decoding unit 2 and the decoded pixel data stored in the storage unit 10, and in addition to the horizontal direction / separately in the vertical direction The enlargement process is performed.

  The storage unit 10 may be provided separately from the storage unit 7 or may be provided in a part of the storage unit 7.

  Vertical interpolation will be described with reference to FIG.

  Here, horizontal refers to the horizontal direction on the display screen, and vertical refers to the vertical direction on the display screen.

  This will be described with reference to FIG. FIG. 10 shows three horizontal lines: a first horizontal line, a second horizontal line, and an interpolation line formed between the two. In FIG. 10, first decoding of the first horizontal line and horizontal enlargement processing are performed, then decoding of the second horizontal line and horizontal expansion processing are performed, and the decoded pixel data of the first horizontal line and the first horizontal line are processed. Pixel data corresponding to the position of the decoded pixel of the interpolation line is generated from the decoded pixel data of the two horizontal lines, and finally the interpolation line is expanded in the horizontal direction. At this time, the storage unit 10 stores the display pixel data of the first horizontal line that has been enlarged in the horizontal direction by the display processing unit 3 in order to generate an interpolation line. In FIG. 10, ◯ indicates decoded pixel data, and X indicates display pixel data.

  First, the decoding unit 2 decodes the decoded pixel data of the first horizontal line (circle mark of the first horizontal line in FIG. 10) and outputs the decoded pixel data to the display processing unit 3. The display processing unit 3 performs an enlargement process of the first horizontal line using the filter 6 to generate display pixel data (x mark in FIG. 10). The display processing unit 3 outputs the display pixel data of the first horizontal line subjected to the enlargement process to the storage unit 10, and the storage unit 10 stores the display pixel data of the first horizontal line.

  Next, the decoding unit 2 generates decoded pixel data (circle mark of the second horizontal line in FIG. 10) of the second horizontal line and outputs the data to the display processing unit 3. The display processing unit 3 uses the filter 6 to perform horizontal enlargement processing of the second horizontal line to generate display pixel data (the x mark of the second horizontal line in FIG. 10).

  Next, the display processing unit 3 reads the display pixel data of the first horizontal line stored in the storage unit 10, and the display pixel data directly generated from the decoded pixel data in the display pixel data (in FIG. 10, The pixel data in which the ◯ and X marks are superimposed on the first horizontal line) and the corresponding pixel data on the second horizontal line (pixel data in which the ◯ and X marks on the second horizontal line in FIG. 10 are superimposed). ) Is used to generate pixel data at the decoded pixel position of the interpolation line. Next, the display processing unit 3 performs an enlargement process of the interpolation line in the horizontal direction. This horizontal enlargement process may use the filter 6 as well as the horizontal enlargement process of the first horizontal line and the second horizontal line, or may be performed by copying pixel data at the decoded pixel position. As a result of the above processing, the vertical enlargement processing is realized by appropriately using the storage unit 10.

  Here, it has been described that the horizontal enlargement process of the interpolation line is performed based on the pixel data of the interpolation line. However, all display pixel data of the first horizontal line and the second horizontal line after the enlargement process is completed. May be used to generate all pixel data of the interpolation line. In this case, the enlargement process in the horizontal direction of the interpolation line can be reduced.

  Even in the second embodiment, since it is necessary to generate a smaller number of decoded pixel data than the number of display pixel data, the pixel clock has a period divided as in the first embodiment. The decoding unit 2 generates decoded pixel data by an enable signal having a valid period of one time between a processing clock and a plurality of periods of the pixel clock.

  The image processing apparatus 1 according to the second embodiment realizes reduced display and enlarged display of an encoded image without requiring an extra buffer memory and without affecting the display speed. In addition, in the enlarged display, the enlarged display in the vertical direction can be realized in addition to / in addition to the horizontal direction with a minimum configuration.

  Further, the enlargement in the vertical direction may be performed by the following procedure.

  First, the decoding unit 2 performs a decoding process on the first horizontal line, and the storage unit 10 stores the decoded pixels on the first horizontal line. Next, the decoding unit 2 reads the decoded pixel data of the first horizontal line from the storage unit 10 while decoding the second horizontal line. The display processing unit 3 generates an interpolation line from the first horizontal line and the second horizontal line. Thereby, enlargement in the vertical direction is performed.

  Next, enlargement processing in the horizontal direction of the first horizontal line, the second horizontal line, and the interpolation line is performed, thereby realizing horizontal and vertical enlargement. As described above, the display pixel data is output to the display unit 8 in the order of the first horizontal line, the interpolation line, and the second horizontal line after the enlargement process in the horizontal direction and the vertical direction is completed. An enlarged image is displayed on the screen.

(Embodiment 3)
Next, a third embodiment will be described.

  In the third embodiment, a further idea of decoding in the decoding unit 2 in the reduction process will be described.

  FIG. 11 is an explanatory diagram showing a relationship between an image and decoding in Embodiment 3 of the present invention.

  In the reduction process, decoded pixel data (that is, a larger number of decoded pixel data than the display pixel data in a unit time) is obtained at a high speed with respect to the speed required for generating the display pixel data (determined by the pixel clock). Need to be generated. In the first embodiment, by generating a processing clock obtained by multiplying the pixel clock as a control signal, it is possible to generate a larger number of decoded pixel data than the number of display pixel data per unit time.

  However, when the reduction ratio increases, it is necessary to further increase the generation speed of the decoded pixel data per unit time. At this time, there is a limit to the processing time in the decoding unit 2, and there is also a limit to speeding up the processing clock, which is a cycle for generating decoded pixel data.

  Alternatively, when vertical reduction processing is performed, decoding of a certain horizontal line needs to be completed and decoded pixel data must be stored, but the required display time is shorter than the time required for the decoding processing. In some cases. In such a case, decoded pixel data is generated using a period corresponding to the non-display area as described below.

  In the third embodiment, the decoding unit 2 uses the period corresponding to the blank area in the image display (horizontal blank area, vertical blank area) and the period corresponding to the non-display area due to the reduced display, so that the decoding unit 2 Generate.

  In FIG. 11, a non-display area exists around the display image, and a horizontal blank area and a vertical blank area exist around the non-display area.

  Now, decoding from the first horizontal line to the third horizontal line is necessary. Here, it is necessary to start decoding of the third horizontal line by the time when the actual display of the display image starts. However, even if the processing clock is advanced, the decoding of the second horizontal line cannot be completed by the time when the actual display of the display image starts.

  In order to solve this, the second horizontal line is decoded using a period related to the horizontal blank area and the non-display area.

  Specifically, the decoding control unit 5 outputs a control signal to the decoding unit 2 when the reduction rate of the reduction process is equal to or greater than a predetermined value. As described above, this control signal includes an instruction to generate decoded pixel data using a period related to a blank area or a non-display area.

  By the above processing, the decoding of the second horizontal line is completed by the time when the actual display of the display image starts, and display pixel data is generated using the decoded pixel data of the second horizontal line.

  The encoded image data processed in the image processing apparatus 1 according to the first to third embodiments may process only the main image, may process only the sub-image, or may process both. Also good.

(Embodiment 4)
Next, a fourth embodiment will be described.

  The image processing apparatus according to the fourth embodiment may process each of the main image and the sub-image through separate processing paths when the encoded image data includes two images, the main image and the sub-image. Explained. The main image is, for example, an image related to the main part of a movie, and the sub-image is an image related to movie subtitles.

  FIG. 12 is a block diagram of an image processing apparatus according to Embodiment 4 of the present invention.

  The image processing apparatus 1 includes two series of decoding units 2a and 2b, display processing units 3a and 3b, filters 6a and 6b, decoding control units 5a and 5b, and storage units 10a and 10b. The control unit 4 is commonly used in each of the two systems. Control unit 4, decoding units 2a and 2b, display processing units 3a and 3b, filters 6a and 6b, decoding control units 5a and 5b, and storage units 10a and 10b are the same as those described in the first to third embodiments. Perform the operation.

  One series processes the main image and the other series processes the sub-image.

  The storage unit 7 stores both the encoded image data related to the main image and the encoded image data related to the sub-image.

  The decoding unit 2a reads encoded image data related to the main image from the storage unit 7. The decoding unit 2a decodes the read encoded image data, generates decoded pixel data, and outputs the decoded pixel data to the display processing unit 3a. The display processing unit 3a generates display pixel data from the decoded pixel data using the filter 6a. At this time, when performing the reduction process / enlargement process, the decoding control unit 5a outputs a control signal to the decoding unit 2a. The control signal is the processing clock or enable signal described in the first embodiment. The decoding unit 2a generates decoded pixel data according to this control signal. For example, in the case of reduction processing, a larger number of decoded pixel data than the number of display pixel data is generated in unit time, and in the case of enlargement processing, the number of decoded pixels smaller than the number of display pixel data in unit time. Generate data. This decoding control is the same as that described in the first to third embodiments.

  The display processing unit 3 a outputs the generated display pixel data to the display unit 8. The display unit 8 displays an image using the display pixel data. This displayed image is the main image.

  In parallel with the decoding and display processing of the main image, the sub-image is decoded and displayed in the other series.

  The decoding unit 2b reads out the encoded image data related to the sub-image from the storage unit 7. The decoding unit 2b decodes the read encoded image data, generates decoded pixel data, and outputs the decoded pixel data to the display processing unit 3b. The display processing unit 3b generates display pixel data from the decoded pixel data using the filter 6b. At this time, when performing the reduction process / enlargement process, the decoding control unit 5b outputs a control signal to the decoding unit 2b. The control signal is the processing clock or enable signal described in the first embodiment. The decoding unit 2b generates decoded pixel data according to this control signal. For example, in the case of reduction processing, a larger number of decoded pixel data than the number of display pixel data is generated in unit time, and in the case of enlargement processing, the number of decoded pixels less than the number of display pixel data in unit time. Generate data. This decoding control is the same as that described in the first to third embodiments.

  The display processing unit 3 b outputs the generated display pixel data to the display unit 8. The display unit 8 displays an image using the display pixel data. This displayed image is a sub-image. The display unit 8 displays the sub image so as to overlap the main image. For example, a sub-image with a reduced size is superimposed and displayed on a main image that is the size of a normal image.

  Here, there are cases where both the main image and the sub-image are subjected to reduction / enlargement processing, but the reduction ratio and enlargement ratio may differ between the case of the main image and the case of the sub-image. For example, the main image may be displayed in the normal image size and the sub-image may be reduced.

  In such a case, as shown in FIG. 1, when there is only one series of decoding and display processing, it is impossible to cope with different reductions and enlargements between the main image and the sub-image. On the other hand, since the image processing apparatus 1 shown in FIG. 12 has two series of decoding and display processes, it can cope with different reduction and enlargement in the main image and the sub-image.

  In order to reduce the circuit scale, it is preferable that the main image is always displayed as a normal image and only the sub-image is reduced or enlarged, and the decoding control unit 5a related to the main image series is reduced. .

  The present invention can be suitably used in the field of image display for decoding and displaying encoded image data, such as a DVD player and a DVD recorder.

1 is a block diagram of an image processing apparatus according to Embodiment 1 of the present invention. Exemplary diagram of filter processing in Embodiment 1 of the present invention Timing chart showing generation of decoded pixel data in normal processing in Embodiment 1 of the present invention Timing chart showing generation of decoded pixel data in normal processing in Embodiment 1 of the present invention Timing chart showing generation of decoded pixel data in reduction processing in Embodiment 1 of the present invention Timing chart showing generation of decoded pixel data in reduction processing in Embodiment 1 of the present invention Timing chart showing generation of decoded pixel data in enlargement processing in Embodiment 1 of the present invention Timing chart showing generation of decoded pixel data in enlargement processing in Embodiment 1 of the present invention Block diagram of an image processing apparatus according to Embodiment 2 of the present invention Explanatory drawing explaining the vertical interpolation in Embodiment 2 of this invention Explanatory drawing which shows the relationship between the image and decoding in Embodiment 3 of this invention Block diagram of an image processing apparatus in Embodiment 4 of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 2 Decoding part 3 Display processing part 4 Control part 5 Decoding control part 6 Filter 7 Storage part 8 Display part

Claims (15)

A decoding unit that decodes the encoded image data and generates decoded pixel data;
A display processing unit that generates display pixels used for display based on a pixel clock that defines a time interval required to display one pixel, using the decoded pixel data;
A control unit for controlling operations of the decoding unit and the display processing unit;
A decoding control unit for controlling the number of the decoded pixel data generated by the decoding unit in a unit time defined by the pixel clock;
The display processing unit is an image processing apparatus that performs a reduction process for reducing the size of a display image with respect to a normal image and / or an enlargement process for expanding the size of a display image with respect to a normal image. The image processing apparatus according to claim 1, wherein the decoding unit operates based on a system clock, and the system clock has a frequency multiplied by the pixel clock. The image processing apparatus according to claim 1, wherein the display processing unit includes a filter that filters the decoded pixel data to generate the display pixel data. The image processing apparatus according to claim 3, wherein in the reduction process, the filter generates one display pixel data using a plurality of decoded pixel data. In the reduction processing, the decoding control unit generates a control signal for controlling the decoding pixel data to be generated in a larger number than the display pixel data generated in the unit time, and sends the control signal to the decoding unit. The image processing apparatus according to claim 1, wherein the decoding unit generates the decoded pixel data according to the control signal. The image processing apparatus according to claim 5, wherein the control signal includes a processing clock signal, and the processing clock has a frequency multiplied by the pixel clock. The image processing apparatus according to claim 5, wherein the control signal includes an enable signal, and the enable signal has a plurality of valid periods with respect to the system clock in a period of one cycle of the pixel clock. The image processing apparatus according to claim 3, wherein, in the enlargement process, the filter generates the display pixel data by interpolating the decoded pixel data. In the enlargement process, the decoding control unit generates a control signal for controlling to generate a smaller number of the decoded pixel data than the display pixel data generated in the unit time, and outputs the control signal to the decoding unit. The image processing apparatus according to claim 1, wherein the decoding unit generates the decoded pixel data according to the control signal. The image processing apparatus according to claim 9, wherein the control signal includes a processing clock signal, and the processing clock has a frequency division of the pixel clock. The image processing apparatus according to claim 9, wherein the control signal includes an enable signal, and the enable signal has an effective period of one time with respect to the system clock in a period obtained by dividing the pixel clock. The image processing apparatus further includes a storage unit that temporarily stores the decoded pixel data decoded by the decoding unit, and in the enlargement process, the filter is an image displayed using the decoded pixel data stored in the storage unit The image processing apparatus according to claim 8, wherein interpolation in the vertical direction is performed. The image processing apparatus according to claim 1, further comprising a display unit configured to display an image using the display pixel data. The image processing according to claim 13, wherein, in the reduction process, the decoding control unit outputs the control signal instructing to generate decoded pixel data to the decoding unit during a non-display period on the display unit. apparatus. A decoding step of decoding the encoded image data to generate decoded pixel data;
A display processing step of generating display pixels used for display based on a pixel clock that defines a time interval required for display of one pixel, using the decoded pixel data;
A control step for controlling operations of the decoding step and the display processing step;
A decoding control step for controlling the number of the decoded pixel data generated in the decoding step in a unit time defined by the pixel clock;
The display processing step is an image processing method for performing a reduction process for reducing the size of the display image with respect to the normal image and / or an enlargement process for expanding the size of the display image with respect to the normal image.

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