JP2011040004A - Image processing apparatus and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus which can eliminate discontinuity of images and reduce a circuit scale, and an image processing method. <P>SOLUTION: An image processing apparatus includes: an image shaping part 102 which successively receives image data of a plurality of divided areas obtained by dividing one image and adds image data included in the one divided area and present in the vicinity of a boundary between the one area and an adjacent divided area, to image data of the adjacent divided area to generate image data of a shaped divided area; and an image processing part 104 which successively receives image data of a plurality of shaped divided areas and successively performs image processing of the image data of shaped divided areas. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus and an image processing method.

  In recent years, video display devices such as televisions and broadcasting environments have been adapted to a resolution of 1920 × 1080 pixels (Full HD (High Definition)). Development into resolutions exceeding FullHD, for example, resolution of 3840 × 2160 pixels or 4096 × 2160 pixels (4k2k) and resolution of 7680 × 4320 pixels (super high vision) has come into the field of view. In particular, video display devices having a resolution of 4k2k are being commercialized.

  However, the current situation is that the hardware performance for high-resolution video processing has not caught up, and parallel processing using existing circuits is being studied. For example, a video having a resolution of 4k2k (3840 × 2160) may be divided into four crosses, and parallel processing may be performed by an existing circuit that can process the resolution of FullHD (1920 × 1080).

  However, when image processing in the spatial direction (for example, filter processing or scaling processing) is performed at the division boundary portion, discontinuity of the image becomes a problem when the divided regions are combined after image processing is performed on the divided regions. Therefore, in Patent Document 1 (Japanese Patent Laid-Open No. 2007-67499), a method is used in which overlapping portions are provided and divided and recombined.

JP 2007-67499 A

  If the correspondence by the parallel processing as described in Patent Document 1 described above is taken, it is not necessary to newly design high-performance hardware that processes 4k2k resolution, but it is necessary to execute image processing in parallel in a plurality of circuits. Therefore, the entire circuit scale becomes huge.

  Hardware capable of processing 60 Hz at a resolution of 4k2k corresponds to four times the performance of hardware processing 60 Hz at the current FullHD resolution. Since a quadruple speed video display device such as 240 Hz has already been developed, it is presumed that hardware capable of processing 60 Hz with a resolution of 4k2k will soon become widespread. However, it is necessary to design and develop a new device accompanying an algorithm change due to an increase in resolution, which takes time and cost.

  For example, when performing spatial image processing such as vertical filtering, the horizontal resolution doubles, which increases the amount of memory for storing data for a plurality of lines, that is, increases hardware resources. Expected.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is a new and improved technique capable of eliminating image discontinuity and reducing the circuit scale. An object is to provide an image processing apparatus and an image processing method.

  In order to solve the above problems, according to an aspect of the present invention, image data of a plurality of divided regions generated by dividing one image into a plurality of images are sequentially input, and adjacent ones included in one divided region An image shaping unit that generates image data of a shaped divided area by adding image data in the vicinity of the boundary between the divided areas to image data of an adjacent divided area, and image data of a plurality of shaped divided areas sequentially An image processing apparatus is provided that includes an image processing unit that sequentially performs image processing on image data that has been input and has been subjected to shaping.

  The image data in the vicinity of the boundary between the adjacent divided areas included in the one divided area, which is added to the image data of the adjacent divided area, may be determined according to the image processing of the image processing unit.

  The image processing speed of the image data of one shaped divided area in the image processing unit may be N times or more the frame rate when displaying an image, where N is the number of divided areas of the image. .

  The image processing apparatus further includes a storage unit that stores image data near a boundary between adjacent divided areas included in one divided area, and the stored image data near the boundary is added to the image data of the adjacent divided area. It may be read at the time.

  The image data of the plurality of divided regions may be data generated by dividing an image into four parts by four crosses.

  In order to solve the above-described problem, according to another aspect of the present invention, a step of sequentially inputting image data of a plurality of divided areas generated by dividing one image into a plurality of divisions, and one division Adding image data in the vicinity of the boundary between adjacent divided areas included in the area to the image data of the adjacent divided areas to generate image data of the shaped divided areas; and There is provided an image processing method including a step of sequentially inputting image data and a step of sequentially performing image processing on the image data of the shaped divided region.

  As described above, according to the present invention, image discontinuity can be eliminated and the circuit scale can be reduced.

It is explanatory drawing which shows the image input into the image processing apparatus 100 which concerns on the 1st Embodiment of this invention. FIG. 2 is a block diagram showing an image processing apparatus 100 according to the same embodiment. It is explanatory drawing which shows the arrangement | sequence of each pixel of an image. It is explanatory drawing which shows the arrangement | sequence of each pixel of an image. It is explanatory drawing which shows the division area of an image. It is explanatory drawing which shows the division area of an image. 4 is an explanatory diagram showing changes in input data and output data of an image shaping unit 102 and data stored in a memory 112. FIG. It is explanatory drawing which shows the division area of an image. It is explanatory drawing which shows the arrangement | sequence of each pixel of an image. It is explanatory drawing which shows the image imaged with an imaging device or displayed with a video display apparatus. It is explanatory drawing which shows the image input into the image processing apparatus 200 which concerns on the 2nd Embodiment of this invention, and is processed. 2 is a block diagram showing an image processing apparatus 200 according to the embodiment. FIG.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

The description will be made in the following order.
1. First embodiment (filter processing)
2. Second embodiment (up-converter processing and high image quality processing)

<1. First Embodiment>
As shown in FIG. 2, the image processing apparatus 100 according to the first embodiment of the present invention includes, for example, an image shaping unit 102, a memory 112, an image processing unit 104, and the like. FIG. 2 is a block diagram illustrating the image processing apparatus 100 according to the present embodiment. The image processing device 100 is provided in a video display device such as a television device, an information processing device such as a personal computer, an imaging device such as a video camera, and the like. The image processing apparatus 100 is, for example, an image processing circuit (processor).

  When the image processing apparatus 100 has an operating frequency that can be processed at a speed higher than the frame rate, the high resolution image is divided, and the image processing is performed by time division multiplexing for each divided region, thereby reducing the circuit scale. To do. Thus, the present embodiment can be realized by omitting the cost of designing a new algorithm and hardware for high resolution, and by slightly changing the image processing circuit corresponding to the existing resolution.

  Further, according to the present embodiment, when one image is divided and image processing is performed on the divided areas and then the divided areas are combined, conventionally, an image discontinuity occurs at the boundary between the areas. The memory capacity required for a series of processing can be reduced.

  FIG. 1 is an explanatory diagram showing an image input to the image processing apparatus 100 and shows a state in which the image is divided into four. In the example shown in FIG. 1, the resolution of the image is a resolution of 3840 × 2160 pixels (4k2k). In the following description, a case where a high-resolution image input to the image processing apparatus 100 has a resolution of 3840 × 2160 pixels as shown in FIG. 1 will be described, but the present embodiment is not limited to this example. . For example, an image having a resolution of 4096 × 2160 pixels (4k2k) or a resolution of 7680 × 4320 pixels may be used.

  An image having a resolution of 3840 × 2160 pixels is divided into four crosses into four areas of 1920 × 1080 pixels and input to the image shaping unit 102 of the image processing apparatus 100. 1920 × 1080 pixels corresponds to FullHD resolution. At this time, each divided region has an image shaping unit in the order of upper left (LU = <1>), upper right (RU = <2>), lower left (LD = <3>), and lower right (RD = <4>). It is assumed that the data is input to 102.

  By the way, if the processing speed (operation frequency) for processing an image with a FullHD resolution for one frame in the image processing apparatus 100 is four times the normal frame rate, an image with a resolution of 3840 × 2160 pixels. Can be displayed at the correct frame rate. In this case, an image having a resolution of 3840 × 2160 pixels is divided into four crosses, and each divided region is sequentially processed by a time division multiplexing method.

  However, simply by sequentially processing each divided region, when performing spatial image processing (for example, filter processing, scaling processing, etc.) at the division boundary portion, after performing image processing on the divided region, the division is performed. Image discontinuity occurs when regions are combined.

  The cause of the image discontinuity will be specifically described with reference to FIG. FIG. 3 is an explanatory diagram showing the arrangement of each pixel of the image, and is an enlarged view of the lower right corner of the upper left region 21A (<1>). FIG. 3 shows a specific example in the case of performing horizontal 3 × vertical 3 filter processing on the target pixel 10 in the upper left region 21A of the example shown in FIG. In order to obtain the output result of the pixel 10 of interest, 3 × 3 pixel data surrounded by a thick frame 12 is required.

  However, when the target pixel 10 is in the vicinity of the boundaries 21a and 21b between the upper left region 21A and the other regions 30 (<2>, <3>, <4>), pixel data that does not exist in the upper left region 21A is virtually Need to be input and filtered. For example, pixel data that does not exist in the upper left area 21A is obtained by performing filtering using zero-value data, repeated data of the last pixel (pixels along the boundaries 21a and 21b), or pseudo-predicted prediction data. Often used as input. However, since the actual data (pixel data in the region 30 other than the upper left region 21A) is input and filtered, the actual result is only the range 21B surrounded by the thick broken lines 21c and 21d in FIG. Is a range where image processing can be performed effectively.

  In the case of 3 × 3 filter processing, the pixel data range necessary for the target pixel 10 is −1 pixel to +1 pixel in both the horizontal direction and the vertical direction. Here, N = 1 and M = 1 are defined as image processing where N is a horizontal range and M is a vertical range.

  The same thing occurs in the upper right, lower left, and lower right regions as in the upper left region, and discontinuity occurs in the output of the image processing result near the cross-shaped boundary. By the way, this problem can be avoided by providing an overlapping portion and dividing as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2007-67499). However, Patent Document 1 requires a parallel processing system in which four image processing units that perform image processing are arranged in parallel and simultaneously execute the four image processing units, which increases the circuit scale.

  On the other hand, in order to have one image processing unit and one image processing unit to perform image processing by time division multiplexing, a frame memory capable of storing image data corresponding to an image having a resolution of 3840 × 2160 pixels is provided. Keep it. And like patent document 1, an overlap area | region can also be read and processed for every division area.

  However, in the present embodiment, when image processing is performed by the time division multiplexing method, only the minimum necessary image data is sent to and added to the image data of other divided areas, so that the image data of one frame can be stored. Memory capacity is not required and memory consumption can be reduced.

  Specifically, discontinuity of the image can be prevented by sending a part of the image data to the image data of another divided region and adding it. FIG. 4 is an explanatory diagram showing the arrangement of each pixel of the image. FIG. 4 (A) shows the upper left area, FIG. 4 (B) shows the upper right area, and FIG. 4 (C) shows the lower left area. FIG. 4 shows a case where a horizontal 3 × vertical 3 filter process is performed as an example.

  In the upper left area of the example of FIG. 4, a range of (1920-1) × (1080-1) can be set as the effective processing result. Then, 2 × 1080 rectangular area data at the right end of the upper left area is sent to the processing of the upper right area, and 1920 × 2 rectangular area data of the lower end of the upper left area is sent to the processing of the lower left area. Thus, discontinuity does not occur in the vicinity of the boundary by connecting ranges that can be effectively processed.

  In the example of FIG. 4, only the case of spatial direction processing that is symmetrical in the vertical and horizontal directions has been described. On the other hand, if N is a horizontal range and M is a vertical range, when 2 parts of area data is sent from the upper left area to the image process of the upper right area, 2N × 1080 rectangular area data is not required. send. Further, when a part of the image area is sent from the upper left area to the lower left area, 1920 × 2M rectangular area data is sent. Thereby, discontinuity of the boundary between the upper left region and the upper right region and the boundary between the upper left region and the lower left region can be prevented.

  Similarly, a data copy process necessary to remove all boundary discontinuities will be described with reference to FIG. 5 and 6 are explanatory diagrams showing the divided areas of the image. FIGS. 5 (A) and 6 (A) show the upper left area, and FIGS. 5 (B) and 6 (B) show the upper right area. 5 (C) and 6 (C) show the lower left region, and FIGS. 5 (D) and 6 (D) show the lower right region.

[Image shaping unit 102]
In the image shaping unit 102, the image data divided into the four divided areas is, as shown in FIG. 2, an upper left area <1>, an upper right area <2>, a lower left area <3>, and a lower right area <4>. Are entered in the order. Then, a part of the image data of the divided areas of the upper left area <1>, the upper right area <2>, and the lower left area <3> is stored in the memory 112 (storage unit). Next, the image shaping unit 102 adds a part of the image data stored in the memory 112 to the image data of the divided areas of the upper right area <2>, the lower left area <3>, and the lower right area <4>. Then, the image shaping unit 102 converts the image data (image data of the shaped divided area) to which a part of the image data has been added into the upper left area <1> -1, the upper right area <2> -1, and the lower left area <3>. -1, Output as lower right area <4> -1.

FIG. 5 shows the divided areas input to the image shaping unit 102.
For example, a 2N × 1080 rectangular area indicated as “<1> aW” illustrated in FIG. 5A is displayed when the upper left area <1> is input to the image shaping unit 102. Of these, it is a (Write) partial area a ”to be written to the memory 112. Similarly, a 1920 × 2M rectangular area indicated as “<1> bW” is “a partial area b to be written to the memory 112 in the upper left area <1>”. Further, a 1920 × 2M rectangular area indicated as “<2> aW” illustrated in FIG. 5B is displayed when the upper right area <2> is input to the image shaping unit 102. Of these, it is a (Write) partial area a ”to be written to the memory 112. A rectangular area of 2N × 1080 indicated as “<3> aW” illustrated in FIG. 5C is displayed when the lower left area <3> is input to the image shaping unit 102 as “memory in the lower left area <3>. 112 is a (Write) partial area a ”.

FIG. 6 shows divided areas output by the image shaping unit 102.
The 2N × 1080 rectangular area indicated as “<1> aR” shown in FIG. 6B is displayed when the upper right area <2> −1 is output from the image shaping unit 102 to the image processing unit 104. 112 is a partial area a of the upper left area <1> to be read out of the data stored in 112. Further, in the 1920 × 2M rectangular area indicated as “<1> bR” illustrated in FIG. 6C, when the lower left area <3> −1 is output from the image shaping unit 102 to the image processing unit 104, “Partial area b of upper left area <1> to be read out of data stored in memory 112”.

  Furthermore, in the 2N × 2M rectangular area indicated as “<1> aR” shown in FIG. 6D, the lower right area <4> −1 is output from the image shaping unit 102 to the image processing unit 104. , “A partial area a of the upper left area <1> to be read out of the data stored in the memory 112”. Similarly, the 1920 × 2M rectangular area indicated as “<2> aR” is “partial area a of the upper right area <2> to be read from the data stored in the memory 112 (Read)”. The 2N × 1080 rectangular area indicated as “<3> aR” is “a partial area a of the lower left area <3> to be read from the data stored in the memory 112 (Read)”.

  The image shaping unit 102 creates data to be output to the image processing unit 104 by writing partial data to the memory 112 or reading from the memory 112 as described above.

  FIG. 7 is an explanatory diagram illustrating changes in input data and output data of the image shaping unit 102 and data stored in the memory 112, and the horizontal axis indicates the passage of time. <1> a and <1> b are stored in the memory 112 when the upper left region <1> is input to the image shaping unit 102. <1> a is stored in the memory 112 until the image shaping unit 102 outputs the lower right region <4> -1, and <1> b is output by the image shaping unit 102 in the lower left region <3> -1. Are stored in the memory 112. <2> a is stored in the memory 112 when the upper right area <2> is input to the image shaping unit 102, and is saved in the memory 112 until the image shaping unit 102 outputs the lower right area <4> -1. Is done. <3> a is stored in the memory 112 when the lower left area <3> is input to the image shaping unit 102, and is saved in the memory 112 until the image shaping unit 102 outputs the lower right area <4> -1. .

  Strictly, as can be seen from FIG. 6D, a part of <1> a region (2N × (1080-2M) region) can be deleted immediately after generating <2> -1. In order to simplify the explanation, <1> a is assumed to be left as a whole. Therefore, the present embodiment is not limited to this example, and a part of the <1> a region (2N × (1080-2M) region) may be deleted immediately after generating <2> -1.

[Image processing unit 104]
8A and 8B are explanatory views showing the divided areas of the image. FIG. 8A shows the upper left area, FIG. 8B shows the upper right area, FIG. 8C shows the lower left area, and FIG. (D) shows the lower right region.

  FIG. 8 shows divided areas output by the image processing unit 104. In the image processing unit 104, an upper left region <1> -1, an upper right region <2> -1, a lower left region <3> -1, and a lower right region <4> -1 are sequentially input. Then, the image processing unit 104 performs spatial image processing (for example, filter processing or scaling processing) on each divided region. As described above, in the case of 3 × 3 filter processing, when N = 1 and M = 1, and the upper left region <1> −1 is image processed, (1920-1) × (1080-1) ) Is an effective image processing range (effective processing range) <1> -2. When the effective processing range is generally expressed, as shown in FIG. 8A, the effective processing range <1> -2 in the upper left region is a range of (1920-N) × (1080-M).

  Similarly, the effective processing range <2> -2 in the upper right region is a range of (1920 + N) × (1080−M) as shown in FIG. The effective processing range <3> -2 in the lower left region is a range of (1920−N) × (1080 + M) as shown in FIG. The effective processing range <4> -2 in the lower right region is a range of (1920 + N) × (1080 + M) as shown in FIG.

  After performing the image processing, the image processing unit 104 sequentially outputs only the effective processing ranges <1> -2, <2> -2, <3> -2, <4> -2. In the case of a liquid crystal television, the output result is sequentially transferred to a panel timing controller or the like provided in the liquid crystal television and displayed based on image data in the effective processing range. At this time, since the data near the boundary of the divided areas is a result of image processing using actual data, an image having continuity at the boundary portion can be obtained simply by sequentially processing each divided area. Can be displayed. Note that the speed at which the image processing unit 104 processes the image data of one shaped divided area is N times or more the frame rate at which an image is displayed, where N is the number of divided areas of the image. For example, a high-resolution image can be displayed at a normal frame rate at a normal frame rate. The example described above is for N = 4.

  As described above, according to the present embodiment, it is not necessary to newly design an image processing circuit dedicated to high resolution (3840 × 2160 pixel resolution (4k2k) in the above-described example). In addition, it is not necessary to prepare image processing circuits corresponding to the resolution of existing 1920 × 1080 pixels by the number of divided areas and use them in parallel. Using only one existing image processing circuit corresponding to the resolution of the existing 1920 × 1080 pixels, the image processing of the resolution of 3840 × 2160 pixels is processed by the time division multiplexing method without causing the boundary portion to fail. Can do. Also, when image processing is performed using the time division multiplexing method, only the minimum necessary image data is sent to and added to the image data in other divided areas, thereby eliminating the need for a memory capacity for storing all the image data of one frame. , Memory consumption can be reduced.

  Note that the video processing apparatus may require a frame memory corresponding to a high-resolution image. For example, when I / F conversion such as rearrangement is necessary when image data is input, or when performing time-direction image processing, a high-resolution frame memory is required. In this case, it is not necessary to reduce the memory consumption by performing image processing by the time division multiplexing method. However, by applying this embodiment, it is only necessary to use one circuit corresponding to the existing resolution, and therefore it is sufficiently effective to perform image processing by the time division multiplexing method.

[About image processing range]
In the description using FIG. 4, image processing using a data range symmetrical in the vertical and horizontal directions is described as an example, and FIG. 4 shows a case where the horizontal range N and the vertical range M are the same number. On the other hand, the range of the divided region to be subjected to image processing may be asymmetrical in the vertical and horizontal directions, and the shape of the data range necessary for image processing may not be rectangular. At this time, the data range to be sent to another divided region may be changed according to the image processing range.

  FIG. 9 is an explanatory diagram showing the arrangement of each pixel of the image. FIG. 9 (A) shows the upper left area, FIG. 9 (B) shows the upper right area, and FIG. 9 (C) shows the lower left area. FIG. 9 shows an example in which a horizontal 4 × vertical 3 filter process is performed.

  In the example of FIG. 9, the data range is required to be longer in the horizontal right direction than in the case of the horizontal 3 × vertical 3 filter processing shown in FIG. Therefore, in the example shown in FIG. 9, the data range to be sent to another divided area is changed compared to the example of FIG.

  For example, in the upper left area of the example of FIG. 9, a range of (1920-2) × (1080-1) can be set as the effective processing result. Then, 3 × 1080 rectangular area data at the right end of the upper left area is sent to the upper right area process, and 1920 × 2 rectangular area data at the lower end of the upper left area is sent to the lower left area process. In this example as well, discontinuity does not occur near the boundary by connecting the effective processing ranges.

[Processing capacity of image processing circuit]
In the above description, according to the present embodiment, it has been described that an existing circuit capable of processing an image having a resolution of 1920 × 1080 pixels (corresponding to FullHD) can be used. Strictly speaking, it is assumed that the existing circuit supports a resolution of (1920 + 2N) × (1080 + 2M) pixels. Note that general values of N and M necessary for image processing are on the order of several tens at most. Therefore, the processing according to the present embodiment can be performed using an existing circuit that can process an image having a resolution of 1920 × 1080 pixels (corresponding to FullHD). Further, even if it is not possible to cope with a slight difference, the change can be made more easily than when designing a circuit corresponding to an image having a resolution four times that of an existing circuit.

[Image division method]
In the above description, the case where the image is divided into four crosses and the image data of the divided areas divided into the four crosses is sequentially transferred has been described. On the other hand, in what format content having high resolution such as 3840 × 2160 pixels is sent, many formats are assumed depending on forms such as broadcasting, network streaming, and disk media distribution.

  For example, as described above, it is conceivable that a high-resolution content is divided into four crosses as the resolution of the current FullHD standard × 4. Furthermore, as shown in FIG. 10, an example in which high-resolution content is divided horizontally or vertically can be considered. FIG. 10 is an explanatory diagram showing an image captured by the imaging device or displayed on the video display device, and shows a state where the image is divided into four.

  In the example of horizontal division shown in FIG. 10A, the horizontal direction of each divided region is the same as the number of pixels of the high resolution image, and the vertical direction is the number of pixels obtained by dividing the high resolution image into four. In the example of horizontal division, the scanning method is the same as when a high-resolution video is transmitted in the same size. Therefore, if the existing image processing circuit supports high resolution in the horizontal direction, or if it is easy to support high resolution in the horizontal direction, this embodiment can be easily applied and high resolution images can be processed. .

  Specifically, as shown in FIG. 10A, when image data of divided areas is sequentially transmitted from the top in the order of <1> → <2> → <3> → <4> The lower end portion (horizontal resolution × 2M rectangular area data) of the divided area (<1>, <2>, <3>) is sequentially sent to another divided area and added. By this processing, the above-described effects of the present embodiment can be similarly realized.

  In the example of vertical division shown in FIG. 10B, the vertical direction of each divided region is the same as the number of pixels of the high-resolution image, and the horizontal direction is the number of pixels obtained by dividing the high-resolution image into four. The example of vertical division can reduce the memory capacity of the line memory when the line memory is required in the algorithm specification. In order to divide the number of horizontal pixels, as shown in FIG. 10 (B), when sequentially transferred from the left in the order of <1> → <2> → <3> → <4> <1>, <2>, <3>) right end part (2N × vertical resolution) is sequentially sent to another divided area and added. By this processing, the above-described effects of the present embodiment can be similarly realized.

<2. Second Embodiment>
As shown in FIG. 12, the image processing apparatus 200 according to the second embodiment of the present invention includes an up-converter image shaping unit 222, a memory 232, an up-converter image processing unit 224, and a high-quality image shaping unit 202. And a memory 212, a high quality image processing unit 204, and the like. FIG. 12 is a block diagram showing an image processing apparatus 200 according to this embodiment.

  In this embodiment, image data of an image input to the image processing apparatus 200 is converted to a high resolution image by up-conversion.

  For example, the image processing apparatus 200 receives content having a resolution of 1920 × 1080 pixels, performs up-conversion (enlargement scaling) processing, and converts the content into high-resolution content exceeding the resolution of 1920 × 1080 pixels. As a result, it is possible to provide high-resolution content by up-conversion of existing content at a stage where a transmission path corresponding to content exceeding 1920 × 1080 pixel resolution (FullHD) is not established, for example, in a transition period to the spread of high-resolution content. .

FIG. 11 is an explanatory diagram showing an image that is input to the image processing apparatus 200 and processed.
In the upconverter image shaping unit 222, an image before upconversion processing, for example, an image having a resolution of 1920 × 1080 pixels, and image data divided into four divided regions as shown in FIG. Is done. Then, a part of the image data of each divided area is stored in the memory 232 (storage unit). Next, the up-converter image shaping unit 222 adds a part of the image data stored in the memory 232 to the image data of the adjacent divided area. Then, the up-converter image shaping unit 222 outputs the image data to which part of the image data is added for each divided area.

  The upconverter image processing unit 224 is sequentially inputted with image data to which a part of the image data is added. Then, the up-converter image processing unit 224 performs up-conversion processing in the spatial direction on each divided region. Thereby, the discontinuity of the boundary between each divided area can be prevented. When the image data in the effective processing range after the up-conversion process are combined, as shown in FIG. 11B, for example, it is possible to increase the definition to an image obtained by combining four images with a resolution (FullHD) of 1920 × 1080 pixels, for example.

  Furthermore, as shown in FIG. 11B, the high-quality image shaping unit 202 receives image data in which each divided area is divided into four divided areas having a resolution of 1920 × 1080 pixels. Then, a part of the image data of each divided area is stored in the memory 212 (storage unit). Next, the high quality image shaping unit 202 adds a part of the image data stored in the memory 212 to the image data of the adjacent divided areas. Then, the high quality image shaping unit 202 outputs image data to which a part of the image data is added for each divided region.

  Image data to which part of the image data is added is sequentially input to the high quality image processing unit 204. Then, the high quality image processing unit 204 performs spatial filtering on each divided region. Thereby, the discontinuity of the boundary between each divided area can be prevented.

  In the present embodiment, not only image processing for improving the image quality of a high-resolution image, but also up-conversion processing is performed by time division multiplexing. Then, by applying the method described in detail in the first embodiment for both the high image quality processing and the up-conversion processing, discontinuity of the image after image processing can be prevented.

  As described above, according to the first and second embodiments of the present invention, image processing for a high-resolution image is performed using only one existing image processing circuit that does not support high-resolution exceeding Full HD, for example. Can do. Further, in the high resolution image processing, it is possible to solve the problem that the output result near the boundary generated by dividing the image causes discontinuity. Further, when the image is divided and processed, the discontinuity of the image can be solved by copying a minimum amount of image data, so that the necessary memory capacity can be reduced. Further, since it is not necessary to process a plurality of image processing circuits in parallel, the circuit scale can be reduced.

  The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious that a person having ordinary knowledge in the technical field to which the present invention pertains can come up with various changes or modifications within the scope of the technical idea described in the claims. Of course, it is understood that these also belong to the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 100,200 Image processing apparatus 102 Image shaping part 104 Image processing part 112,212,232 Memory 202 High quality image shaping part 204 High quality image processing part 222 Upconverter image shaping part 224 Upconverter image processing part

Claims (6)

Image data of a plurality of divided regions generated by dividing one image into a plurality of images are sequentially input, and image data in the vicinity of the boundary between the adjacent divided regions included in one of the divided regions is adjacent to the image data. In addition to the image data of the divided area, an image shaping unit that generates image data of the shaped divided area;
An image processing apparatus comprising: an image processing unit that sequentially inputs image data of a plurality of the shaped divided areas and sequentially performs image processing on the image data of the shaped divided areas.   The image data in the vicinity of the boundary between the adjacent divided areas included in the one divided area, which is added to the image data of the adjacent divided areas, is determined according to the image processing of the image processing unit. The image processing apparatus according to claim 1.   The speed at which the image processing unit processes the image data of one of the shaped divided areas is N times or more the frame rate at which the image is displayed, where N is the number of the divided areas of the image. The image processing apparatus according to claim 1, wherein there is an image processing apparatus. A storage unit for storing image data in the vicinity of a boundary between the adjacent divided areas included in the one divided area;
The image processing apparatus according to claim 1, wherein the stored image data in the vicinity of the boundary is read when added to the image data of the adjacent divided region.   5. The image processing apparatus according to claim 1, wherein the image data of the plurality of divided regions is data generated by dividing the image into four parts by four crosses. 6. A step of sequentially inputting image data of a plurality of divided areas generated by dividing one image into a plurality of parts;
Adding image data in the vicinity of the boundary between the adjacent divided areas included in one of the divided areas to the image data of the adjacent divided areas to generate image data of the shaped divided areas;
A step of sequentially inputting image data of a plurality of the shaped divided regions;
And sequentially performing image processing on the image data of the shaped divided area.

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