WO2013077203A1 - Video output device and display device - Google Patents

Video output device and display device Download PDF

Info

Publication number
WO2013077203A1
WO2013077203A1 PCT/JP2012/079178 JP2012079178W WO2013077203A1 WO 2013077203 A1 WO2013077203 A1 WO 2013077203A1 JP 2012079178 W JP2012079178 W JP 2012079178W WO 2013077203 A1 WO2013077203 A1 WO 2013077203A1
Authority
WO
WIPO (PCT)
Prior art keywords
video
data
channel
display device
frame
Prior art date
Application number
PCT/JP2012/079178
Other languages
French (fr)
Japanese (ja)
Inventor
忠夫 森下
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2013077203A1 publication Critical patent/WO2013077203A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0221—Addressing of scan or signal lines with use of split matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/045—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial
    • G09G2370/047—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial using display data channel standard [DDC] communication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/20—Details of the management of multiple sources of image data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal

Definitions

  • the present invention relates to video output and video display.
  • the number of pixels of the current high-definition television broadcast is 1920 ⁇ 1080 (so-called 2K1K), which is four times as many pixels as this HDTV (so-called 4K2K) or 16 times as many pixels.
  • 2K1K high definition television broadcast
  • 4K2K high definition television broadcast
  • 8K4K 8K4K
  • Patent Document 1 a plurality of video data obtained by dividing frame data of one frame (the number of pixels exceeds the number of pixels of HDTV) is divided into a plurality of channels corresponding to each (each channel is an HD-SDI standard). A configuration for transmitting data is disclosed.
  • the present invention proposes a method for obtaining a correct frame display even when the connection relationship between the plurality of output terminals on the video output device side and the plurality of input terminals on the display device side is wrong when performing such transmission.
  • the present video output apparatus divides one frame of frame data to generate first to n-th channel video data, and the first to n-th channel video data corresponding to each of the first to n-th channel video data.
  • N output terminals for connection to a display device that receives at the input terminal of the nth channel, n input terminals obtained from the display device via the first to nth channel input terminals and the n output terminals.
  • a data distribution circuit that distributes video data of the first to n-th channels to n output terminals based on channel data (channel information).
  • a plurality of video data obtained by dividing frame data of one frame is transmitted between a video output device and a display device through a plurality of channels (cables), a plurality of output terminals on the video output device side.
  • a correct frame display can be obtained even if the connection relationship between the display device and the plurality of input terminals on the display device side is wrong.
  • FIG. 1 is a block diagram illustrating a configuration of a video system according to Embodiment 1 (a state in which a video output device and a display device are not connected).
  • FIG. It is a schematic diagram explaining the function of the video output device of FIG.
  • It is a schematic diagram which shows the method (partition system) which divides
  • 1 is a block diagram illustrating a configuration of a video system according to Embodiment 1 (a state in which a video output device and a display device are erroneously connected).
  • FIG. 6 is a block diagram illustrating another configuration of the display device according to Embodiment 1.
  • FIG. 10 is a block diagram illustrating another configuration of the display device according to the second embodiment.
  • FIGS. 1 to 11 The embodiment of the present invention will be described with reference to FIGS. 1 to 11 as follows.
  • the video system As shown in FIG. 1, the video system according to the first embodiment includes a display device 1 and a video output device 10.
  • the display device 1 includes four channel (four) input terminals IT1 to IT4 (HDMI standard), a video processing circuit VP, timing controllers TC1 to TC4, source drivers SD1 to SD2, gate drivers GD1 to GD2, and a liquid crystal panel LCP.
  • the liquid crystal panel LCP is a so-called 4K2K panel (ultra-high-definition liquid crystal panel) having, for example, horizontal 3840 pixels or 4096 pixels ⁇ vertical 2160 pixels
  • the video processing circuit VP has channel data Dx1 stored in a memory (for example, EEPROM). ⁇ Dx4 is included.
  • the channel data Dx1 to Dx4 are a part of EDID (Extended / Display / identification / Date) which is binary data defined by the VESA standard.
  • EDID Extended / Display / identification / Date
  • Each input terminal is configured by a connector of HDMI (High-definitioninMultimedia Interface) standard.
  • the video output device 10 includes a video data generation circuit VGC, a data distribution circuit 5 including a matrix switch MSW and a connection determination circuit CDC, and four channel (four) output terminals OT1 to OT4.
  • the video data generation circuit VGC divides one frame of frame data Df to generate first to fourth channel video data Dv1 to Dv4, and the corresponding first to fourth channels.
  • the video terminals VT1 to VT4 are connected in parallel to the output terminals OT1 to OC4 via the matrix switch MSW as shown in FIG.
  • Each output terminal is configured with an HDMI standard connector.
  • the frame data Df and the video data Dv1 to Dv4 as shown in FIG.
  • the frame data Df corresponds to a single video of 4K2K size
  • each of the video data Dv1 to Dv4 is a high-definition partial video of 2K1K size
  • the video data Dv1 corresponds to the upper left part
  • the video data Dv2 corresponds to the upper right part
  • the video data Dv3 corresponds to the lower left part
  • the video data Dv4 corresponds to the lower right part
  • FIG. 4 shows a (wrong) connection state between the video output device 10 and the display device 1. That is, the output terminal OT1 of the video output device 10 is connected to the input terminal IT3 of the display device 1 via the cable CA1 (HDMI standard), and the output terminal OT2 of the video output device 10 is displayed via the cable CA2 (HDMI standard).
  • the output terminal OT3 of the video output device 10 is connected to the input terminal IT2 of the display device 1 via the cable CA3 (HDMI standard), and the output terminal OT4 of the video output device 10 is connected to the cable CA4. It is connected to the input terminal IT4 of the display device 1 via (HDMI standard).
  • the channel data Dx3 in the video processing circuit VP is input to the connection determination circuit CDC via the input terminal IT3 and the output terminal OT1, and the channel data Dx1 in the video processing circuit VP is input.
  • the signal is input to the connection determination circuit CDC via the terminal IT1 and the output terminal OT2, and the channel data Dx2 in the video processing circuit VP is input to the connection determination circuit CDC via the input terminal IT2 and the output terminal OT3, and the video processing circuit VP.
  • the channel data Dx4 is input to the connection determination circuit CDC via the input terminal IT4 and the output terminal OT4.
  • the output terminal OT1 is connected to the input terminal IT3, the output terminal OT2 is connected to the input terminal IT1, the output terminal OT3 is connected to the input terminal IT2, and the output terminal OT4 is connected to the input terminal IT4.
  • a control signal is transmitted to the matrix switch MSW.
  • the matrix switch MSW connects the video terminal VT1 of the first channel and the output terminal OT2, connects the video terminal VT2 of the second channel and the output terminal OT3, and connects the video terminal of the third channel.
  • the VT3 and the output terminal OT1 are connected, and the fourth channel video terminal VT4 and the output terminal OT4 are connected.
  • the first to fourth channel video data Dv1 to Dv4 are input to the video processing circuit VP from the first to fourth channel input terminals IT1 to IT4, respectively.
  • the video processing circuit VP has 4 channel outputs, which are input to the timing controllers TC1 to TC4.
  • the timing controllers TC1 and TC2 control the source driver SD1 and the gate drivers GD1 and GD2, and the timing controllers TC3 and TC4 control the source driver SD2 and the gate drivers GD1 and GD2.
  • the source driver SD1 and the gate drivers GD1 and GD2 drive the upper left area AR1 (pixel number 2K1K) and upper right area AR2 (pixel number 2K1K) of the liquid crystal panel LCP, and the source driver SD2 and gate drivers GD1 and GD2
  • the lower left area AR3 (pixel number 2K1K) and lower right area AR4 (pixel number 2K1K) of the liquid crystal panel LCP are driven.
  • each area may have the same size or different sizes.
  • the display device 3 is provided with one video processing circuit VP, but a plurality of video processing circuits VP may be provided.
  • timing controller of the display device 3 is not limited to four, and may be two or one.
  • the division format of the screen (and frame data Df) of the liquid crystal panel is arbitrary.
  • the display device 1 may be configured as shown in FIG. 10, the liquid crystal panel may be divided into four in the horizontal direction, and the four regions Ar1 to Ar4 may be arranged in the horizontal direction (direction orthogonal to the scanning direction).
  • the user can connect the four output terminals on the video output device side and the four input terminals on the display device side in any way, so that a correct frame display can be obtained, which is convenient. is there.
  • the video system includes a display device 1 and a video output device 10.
  • the display device 1 includes four channels (four) of input terminals IT1 to IT4 (HDMI standard), a data distribution circuit 15 including a matrix switch msw and a connection determination circuit cdc, and ports PT1 to PT4 of the first to fourth channels. It includes a video processing circuit VP, timing controllers TC1 to TC4, source drivers SD1 to SD2, gate drivers GD1 to GD2, and a liquid crystal panel LCP.
  • the liquid crystal panel LCP is a so-called 4K2K panel (ultra-high-definition liquid crystal panel) having, for example, horizontal 3840 pixels or 4096 pixels ⁇ vertical 2160 pixels.
  • Each input terminal is composed of a connector of HDMI (High-definition Multimedia Interface) standard, and the input terminals IT1 to IT4 are ports of the first to fourth channels via a matrix switch msw as shown in FIG. Connected to PT1 to PT4.
  • HDMI High-definition Multimedia Interface
  • the video output device 10 includes a video data generation circuit VGC and first to fourth channel (four) output terminals OT1 to OT4. Each output terminal is configured with an HDMI standard connector.
  • the video data generation circuit VGC divides one frame of frame data Df to generate video data Dv1 to Dv4 for the first to fourth channels, and each of the video data Dv1 to Dv4.
  • Channel data dx1 to dx4 are added after the first line (1920 effective pixel data in which the data enable signal DE is active), and then the video terminals VT1 to VT4 of the first to fourth channels corresponding to the channel data dx1 to dx4, respectively. Output in parallel.
  • the frame data Df corresponds to a single video of 4K2K size
  • each of the video data Dv1 to Dv4 is a high-definition partial video (video data) of 2K1K size.
  • Dv1 corresponds to the upper left part
  • video data Dv2 corresponds to the upper right part
  • video data Dv3 corresponds to the lower left part
  • video data Dv4 corresponds to the lower right part).
  • FIG. 8 shows a (wrong) connection state between the video output device 10 and the display device 1. That is, the output terminal OT1 of the video output device 10 is connected to the input terminal IT2 of the display device 1 via the cable CA1 (HDMI standard), and the output terminal OT2 of the video output device 10 is displayed via the cable CA2 (HDMI standard).
  • the output terminal OT3 of the video output device 10 is connected to the input terminal IT1 of the display device 1 via the cable CA3 (HDMI standard), and the output terminal OT4 of the video output device 10 is connected to the cable CA4. It is connected to the input terminal IT3 of the display device 1 via (HDMI standard).
  • the channel data dx1 in the video data Dv1 is input to the connection determination circuit CDC via the output terminal OT1 and the input terminal IT2
  • the channel data dx2 in the video data Dv2 is input to the output terminal OT2
  • the channel data dx3 in the video data Dv3 is input to the connection determination circuit CDC via the input terminal IT4
  • the channel data dx4 in the video data Dv4 is input to the connection determination circuit CDC via the output terminal OT3 and the input terminal IT1. Is input to the connection determination circuit CDC via the output terminal OT4 and the input terminal IT3.
  • the output terminal OT1 is connected to the input terminal IT2
  • the output terminal OT2 is connected to the input terminal IT4
  • the output terminal OT3 is connected to the input terminal IT1
  • the output terminal OT4 is connected to the input terminal IT3.
  • a control signal is transmitted to the matrix switch msw.
  • the matrix switch msw connects the input terminal IT1 and the port PT3, connects the input terminal IT2 and the port PT1, connects the input terminal IT3 and the port PT4, and connects the input terminal IT4 and the port PT4.
  • Connect PT2 As a result, the video data Dv1 to Dv4 of the first to fourth channels are input to the video processing circuit VP from the ports PT1 to PT4 of the first to fourth channels, respectively.
  • the video processing circuit VP has 4 channel outputs, which are input to the timing controllers TC1 to TC4.
  • the timing controllers TC1 and TC2 control the source driver SD1 and the gate drivers GD1 and GD2, and the timing controllers TC3 and TC4 control the source driver SD2 and the gate drivers GD1 and GD2.
  • the source driver SD1 and the gate drivers GD1 and GD2 drive the upper left area AR1 (pixel number 2K1K) and upper right area AR2 (pixel number 2K1K) of the liquid crystal panel LCP, and the source driver SD2 and gate drivers GD1 and GD2
  • the lower left area AR3 (pixel number 2K1K) and lower right area AR4 (pixel number 2K1K) of the liquid crystal panel LCP are driven.
  • each area may have the same size or different sizes.
  • one video processing circuit VP is provided in the display device 3, but a plurality of video processing circuits VP may be provided. Further, the number of timing controllers of the display device 3 is not limited to four, and may be two or one.
  • the division format of the screen (and frame data Df) of the liquid crystal panel is arbitrary.
  • the display device 1 may be configured as shown in FIG. 11, the liquid crystal panel may be divided into four in the horizontal direction, and the four regions Ar1 to Ar4 may be arranged in the horizontal direction (direction perpendicular to the scanning direction).
  • a user can connect the four output terminals on the video output device side and the four input terminals on the display device side in any way, so that a correct frame display can be obtained, which is convenient. .
  • Example 3 As shown in FIG. 9, the video data generation circuit VGC shown in FIGS. Low-definition whole video (so-called thinned video) may be supported.
  • the present video output device divides one frame of frame data to generate the first to n-th channel video data and the first to n-th channel video data respectively.
  • N output terminals for connection to display devices that accept at the first to n-th channel input terminals corresponding to, from the display device via the first to n-th channel input terminals and the n output terminals.
  • a data distribution circuit that distributes video data of the first to n-th channels to n output terminals based on the obtained n channel data (channel information).
  • the one frame may include a number of pixels exceeding the video standard for high-definition television broadcasting.
  • each output terminal may be configured with a connector of HDMI (High-definition Multimedia Interface) standard.
  • HDMI High-definition Multimedia Interface
  • the data distribution circuit may include a matrix switch, and the matrix switch may be configured to connect the video data generation circuit and n output terminals.
  • each of the video data of the first to n-th channels may be configured to correspond to the partial video of the one frame.
  • each of the video data of the first to nth channels can be configured to correspond to the thinned video of the one frame.
  • each channel data may be included in an EDID (Extended Display Identification Date) stored in a memory in the display device.
  • EDID Extended Display Identification Date
  • the display apparatus receives n channel data corresponding to the first to n-th channel video data and the first to n-th channel video data obtained by dividing one frame of frame data, respectively.
  • a terminal a video processing circuit including first to n-th channel ports corresponding to the first to n-th channel video data, and n channel data corresponding to the first to n-th channel video data, respectively.
  • a data distribution circuit that distributes the first to n-th channel video data to the first to n-th channel ports.
  • the one frame may include a number of pixels exceeding the video standard for high-definition television broadcasting.
  • each input terminal may be configured by a connector of HDMI (High-Definition Multimedia Interface) standard.
  • HDMI High-Definition Multimedia Interface
  • the data distribution circuit may include a matrix switch, and the matrix switch may be configured to connect n input terminals and first to n-th channel video processing circuits.
  • each of the video data of the first to n-th channels can be configured to correspond to the partial video of the one frame.
  • each of the video data of the first to n-th channels can be configured to correspond to the thinned video of the one frame.
  • the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on known techniques and common general knowledge or combinations thereof are also included in the embodiments of the present invention. It is. In addition, the operational effects described in each embodiment are merely examples.
  • the present invention is suitable for, for example, an ultra-high definition liquid crystal display device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

This video output device is provided with: a video data generation circuit that generates first to nth channel video data by splitting the frame data for one frame; n output terminals to be connected to a display device for receiving the first to nth channel video data by means of corresponding first to nth channel input terminals; and a data sorting circuit that distributes the first to nth channel video data to n output terminals on the basis of n channel data obtained from the display device via the first to nth channel input terminals and the n output terminals. According to this configuration, the correct frame display can be obtained even if an error is made in the connection relationships between the plurality of output terminals on the video output device side and the plurality of input terminals on the display device side.

Description

映像出力装置、表示装置Video output device, display device
　本発明は映像出力および映像表示に関する。 The present invention relates to video output and video display.
　現行の高精細度テレビジョン放送（High Definition television：ＨＤＴＶ）の画素数は、横１９２０×縦１０８０（いわゆる２Ｋ１Ｋ）であるが、このＨＤＴＶの４倍の画素数（いわゆる４Ｋ２Ｋ）あるいは１６倍の画素数（いわゆる８Ｋ４Ｋ）の映像規格（スーパーハイビジョンＳＨＶもこの１つ）が提唱されている。 The number of pixels of the current high-definition television broadcast (High Definition television: HDTV) is 1920 × 1080 (so-called 2K1K), which is four times as many pixels as this HDTV (so-called 4K2K) or 16 times as many pixels. Several (so-called 8K4K) video standards (Super Hi-Vision SHV is one of them) have been proposed.
　特許文献１には、１フレーム（画素数はＨＤＴＶの画素数を越える）のフレームデータを分割して得られる複数の映像データを、それぞれに対応する複数のチャネル（各チャネルはＨＤ－ＳＤＩ規格）で伝送する構成が開示されている。 In Patent Document 1, a plurality of video data obtained by dividing frame data of one frame (the number of pixels exceeds the number of pixels of HDTV) is divided into a plurality of channels corresponding to each (each channel is an HD-SDI standard). A configuration for transmitting data is disclosed.
特開２００９－１３０６３９号公報JP 2009-130639 A
　このように、１フレームのフレームデータを分割して得られる複数の映像データを映像出力装置および表示装置間で複数チャネル（ケーブル）で伝送するときに、映像出力装置側の複数の出力端子と表示装置側の複数の入力端子との接続関係を間違えて（ケーブルを挿し違えて）しまうと正しいフレーム表示がなされない。 As described above, when a plurality of video data obtained by dividing one frame of frame data is transmitted between the video output device and the display device through a plurality of channels (cables), a plurality of output terminals on the video output device side are displayed. If the connection relation with a plurality of input terminals on the device side is wrong (cable is wrongly inserted), the correct frame display is not made.
　本発明では、このような伝送を行うときに、映像出力装置側の複数の出力端子と表示装置側の複数の入力端子との接続関係を間違えても正しいフレーム表示が得られる手法を提案する。 The present invention proposes a method for obtaining a correct frame display even when the connection relationship between the plurality of output terminals on the video output device side and the plurality of input terminals on the display device side is wrong when performing such transmission.
　本映像出力装置は、１フレームのフレームデータを分割して第１～第ｎチャネルの映像データを生成する映像データ生成回路と、上記第１～第ｎチャネルの映像データをそれぞれに対応する第１～第ｎチャネルの入力端子で受け付ける表示装置に接続するためのｎ個の出力端子と、第１～第ｎチャネルの入力端子および上記ｎ個の出力端子を介して表示装置から得られるｎ個のチャネルデータ（チャネル情報）に基づいて、第１～第ｎチャネルの映像データをｎ個の出力端子に振り分けるデータ振り分け回路とを備えることを特徴とする。 The present video output apparatus divides one frame of frame data to generate first to n-th channel video data, and the first to n-th channel video data corresponding to each of the first to n-th channel video data. N output terminals for connection to a display device that receives at the input terminal of the nth channel, n input terminals obtained from the display device via the first to nth channel input terminals and the n output terminals. And a data distribution circuit that distributes video data of the first to n-th channels to n output terminals based on channel data (channel information).
　本発明によれば、１フレームのフレームデータを分割して得られる複数の映像データを映像出力装置および表示装置間で複数チャネル（ケーブル）で伝送するときに、映像出力装置側の複数の出力端子と表示装置側の複数の入力端子との接続関係を間違えても正しいフレーム表示が得られる。 According to the present invention, when a plurality of video data obtained by dividing frame data of one frame is transmitted between a video output device and a display device through a plurality of channels (cables), a plurality of output terminals on the video output device side. A correct frame display can be obtained even if the connection relationship between the display device and the plurality of input terminals on the display device side is wrong.
実施例１の映像システムの構成（映像出力装置および表示装置を接続していない状態）を示すブロック図である。1 is a block diagram illustrating a configuration of a video system according to Embodiment 1 (a state in which a video output device and a display device are not connected). FIG. 図１の映像出力装置の機能を説明する模式図である。It is a schematic diagram explaining the function of the video output device of FIG. 単一映像で構成されたフレームのフレームデータを分割する手法（パーティション方式）を示す模式図である。It is a schematic diagram which shows the method (partition system) which divides | segments the frame data of the flame | frame comprised by the single image | video. 実施例１の映像システムの構成（映像出力装置および表示装置を誤って接続した状態）を示すブロック図である。1 is a block diagram illustrating a configuration of a video system according to Embodiment 1 (a state in which a video output device and a display device are erroneously connected). FIG. 実施例２の映像システムの構成（映像出力装置および表示装置を接続していない状態）を示すブロック図である。It is a block diagram which shows the structure (state which has not connected the video output device and the display apparatus) of the video system of Example 2. FIG. 図５の映像出力装置の機能を説明する模式図である。It is a schematic diagram explaining the function of the video output device of FIG. 図６の映像データおよびチャネルデータについて説明する模式図である。It is a schematic diagram explaining the video data and channel data of FIG. 実施例２の映像システムの構成（映像出力装置および表示装置を誤って接続した状態）を示すブロック図である。It is a block diagram which shows the structure (state which connected the video output device and the display apparatus accidentally) of the video system of Example 2. 実施例３でのフレームデータを分割する手法（間引き方式）を示す模式図である。It is a schematic diagram which shows the method (decimation method) which divides | segments the frame data in Example 3. FIG. 実施例１の表示装置の別構成を示すブロック図である。6 is a block diagram illustrating another configuration of the display device according to Embodiment 1. FIG. 実施例２の表示装置の別構成を示すブロック図である。FIG. 10 is a block diagram illustrating another configuration of the display device according to the second embodiment.
　本発明の実施の形態を、図１～１１を用いて説明すれば、以下のとおりである。 The embodiment of the present invention will be described with reference to FIGS. 1 to 11 as follows.
　〔実施例１〕
　実施例１の映像システムは、図１に示すように、表示装置１と映像出力装置１０とを備える。 [Example 1]
As shown in FIG. 1, the video system according to the first embodiment includes a display device 1 and a video output device 10.
　表示装置１は、４チャネル（４つ）の入力端子ＩＴ１～ＩＴ４（ＨＤＭＩ規格）、映像処理回路ＶＰ、タイミングコントローラＴＣ１～ＴＣ４、ソースドライバＳＤ１～ＳＤ２、ゲートドライバＧＤ１～ＧＤ２、および液晶パネルＬＣＰを備える。液晶パネルＬＣＰは、例えば、横３８４０画素または４０９６画素×縦２１６０画素のいわゆる４Ｋ２Ｋパネル（超高精細液晶パネル）であり、映像処理回路ＶＰは、メモリ（例えば、ＥＥＰＲＯＭ）に格納されたチャネルデータＤｘ１～Ｄｘ４を含んでいる。なお、チャネルデータＤｘ１～Ｄｘ４は、ＶＥＳＡ規格で規定されたバイナリデータであるＥＤＩＤ（Extended Display identification Date）の一部である。また、各入力端子は、ＨＤＭＩ（High-definition Multimedia Interface）規格のコネクタで構成される。 The display device 1 includes four channel (four) input terminals IT1 to IT4 (HDMI standard), a video processing circuit VP, timing controllers TC1 to TC4, source drivers SD1 to SD2, gate drivers GD1 to GD2, and a liquid crystal panel LCP. Prepare. The liquid crystal panel LCP is a so-called 4K2K panel (ultra-high-definition liquid crystal panel) having, for example, horizontal 3840 pixels or 4096 pixels × vertical 2160 pixels, and the video processing circuit VP has channel data Dx1 stored in a memory (for example, EEPROM). ~ Dx4 is included. The channel data Dx1 to Dx4 are a part of EDID (Extended / Display / identification / Date) which is binary data defined by the VESA standard. Each input terminal is configured by a connector of HDMI (High-definitioninMultimedia Interface) standard.
　映像出力装置１０は、映像データ生成回路ＶＧＣと、マトリクススイッチＭＳＷおよび接続決定回路ＣＤＣを含むデータ振り分け回路５と、４チャネル（４つ）の出力端子ＯＴ１～ＯＴ４とを備える。映像データ生成回路ＶＧＣは、図２に示すように、１フレームのフレームデータＤｆを分割して第１～第４チャネルの映像データＤｖ１～Ｄｖ４を生成し、それぞれに対応する第１～第４チャネルの映像端子ＶＴ１～ＶＴ４に並列出力するものであり、映像端子ＶＴ１～ＶＴ４は、図１に示すように、マトリクススイッチＭＳＷを介して出力端子ＯＴ１～ＯＣ４に接続されている。なお、各出力端子は、ＨＤＭＩ規格のコネクタで構成される。また、フレームデータＤｆおよび映像データＤｖ１～Ｄｖ４については、図３に示すように、フレームデータＤｆが４Ｋ２Ｋサイズの単一映像に対応し、映像データＤｖ１～Ｄｖ４それぞれが２Ｋ１Ｋサイズの高精細部分映像（映像データＤｖ１が左上部分、映像データＤｖ２が右上部分、映像データＤｖ３が左下部分、映像データＤｖ４が右下部分）に対応する。 The video output device 10 includes a video data generation circuit VGC, a data distribution circuit 5 including a matrix switch MSW and a connection determination circuit CDC, and four channel (four) output terminals OT1 to OT4. As shown in FIG. 2, the video data generation circuit VGC divides one frame of frame data Df to generate first to fourth channel video data Dv1 to Dv4, and the corresponding first to fourth channels. The video terminals VT1 to VT4 are connected in parallel to the output terminals OT1 to OC4 via the matrix switch MSW as shown in FIG. Each output terminal is configured with an HDMI standard connector. As for the frame data Df and the video data Dv1 to Dv4, as shown in FIG. 3, the frame data Df corresponds to a single video of 4K2K size, and each of the video data Dv1 to Dv4 is a high-definition partial video of 2K1K size ( The video data Dv1 corresponds to the upper left part, the video data Dv2 corresponds to the upper right part, the video data Dv3 corresponds to the lower left part, and the video data Dv4 corresponds to the lower right part).
　図４は、映像出力装置１０と表示装置１との（誤った）接続状態を示すものである。すなわち、映像出力装置１０の出力端子ＯＴ１がケーブルＣＡ１（ＨＤＭＩ規格）を介して表示装置１の入力端子ＩＴ３に接続され、映像出力装置１０の出力端子ＯＴ２がケーブルＣＡ２（ＨＤＭＩ規格）を介して表示装置１の入力端子ＩＴ１に接続され、映像出力装置１０の出力端子ＯＴ３がケーブルＣＡ３（ＨＤＭＩ規格）を介して表示装置１の入力端子ＩＴ２に接続され、映像出力装置１０の出力端子ＯＴ４がケーブルＣＡ４（ＨＤＭＩ規格）を介して表示装置１の入力端子ＩＴ４に接続されている。 FIG. 4 shows a (wrong) connection state between the video output device 10 and the display device 1. That is, the output terminal OT1 of the video output device 10 is connected to the input terminal IT3 of the display device 1 via the cable CA1 (HDMI standard), and the output terminal OT2 of the video output device 10 is displayed via the cable CA2 (HDMI standard). The output terminal OT3 of the video output device 10 is connected to the input terminal IT2 of the display device 1 via the cable CA3 (HDMI standard), and the output terminal OT4 of the video output device 10 is connected to the cable CA4. It is connected to the input terminal IT4 of the display device 1 via (HDMI standard).
　この場合、映像出力装置１０では、映像処理回路ＶＰ内のチャネルデータＤｘ３が、入力端子ＩＴ３および出力端子ＯＴ１を介して接続決定回路ＣＤＣに入力され、映像処理回路ＶＰ内のチャネルデータＤｘ１が、入力端子ＩＴ１および出力端子ＯＴ２を介して接続決定回路ＣＤＣに入力され、映像処理回路ＶＰ内のチャネルデータＤｘ２が、入力端子ＩＴ２および出力端子ＯＴ３を介して接続決定回路ＣＤＣに入力され、映像処理回路ＶＰ内のチャネルデータＤｘ４が、入力端子ＩＴ４および出力端子ＯＴ４を介して接続決定回路ＣＤＣに入力される。 In this case, in the video output device 10, the channel data Dx3 in the video processing circuit VP is input to the connection determination circuit CDC via the input terminal IT3 and the output terminal OT1, and the channel data Dx1 in the video processing circuit VP is input. The signal is input to the connection determination circuit CDC via the terminal IT1 and the output terminal OT2, and the channel data Dx2 in the video processing circuit VP is input to the connection determination circuit CDC via the input terminal IT2 and the output terminal OT3, and the video processing circuit VP. The channel data Dx4 is input to the connection determination circuit CDC via the input terminal IT4 and the output terminal OT4.
　これにより、接続決定回路ＣＤＣは、出力端子ＯＴ１が入力端子ＩＴ３に接続され、出力端子ＯＴ２が入力端子ＩＴ１に接続され、出力端子ＯＴ３が入力端子ＩＴ２に接続され、出力端子ＯＴ４が入力端子ＩＴ４に接続されていることを認識し、マトリクススイッチＭＳＷに制御信号を送信する。この制御信号を受けて、マトリクススイッチＭＳＷは、第１チャネルの映像端子ＶＴ１と出力端子ＯＴ２とを接続し、第２チャネルの映像端子ＶＴ２と出力端子ＯＴ３とを接続し、第３チャネルの映像端子ＶＴ３と出力端子ＯＴ１とを接続し、第４チャネルの映像端子ＶＴ４と出力端子ＯＴ４とを接続する。この結果、第１～第４チャネルの映像データＤｖ１～Ｄｖ４はそれぞれ、第１～第４チャネルの入力端子ＩＴ１～ＩＴ４から映像処理回路ＶＰに入力される。 Thereby, in the connection determination circuit CDC, the output terminal OT1 is connected to the input terminal IT3, the output terminal OT2 is connected to the input terminal IT1, the output terminal OT3 is connected to the input terminal IT2, and the output terminal OT4 is connected to the input terminal IT4. Recognizing that it is connected, a control signal is transmitted to the matrix switch MSW. Upon receiving this control signal, the matrix switch MSW connects the video terminal VT1 of the first channel and the output terminal OT2, connects the video terminal VT2 of the second channel and the output terminal OT3, and connects the video terminal of the third channel. The VT3 and the output terminal OT1 are connected, and the fourth channel video terminal VT4 and the output terminal OT4 are connected. As a result, the first to fourth channel video data Dv1 to Dv4 are input to the video processing circuit VP from the first to fourth channel input terminals IT1 to IT4, respectively.
　映像処理回路ＶＰからは４チャネルの出力があって、それぞれがタイミングコントローラＴＣ１～ＴＣ４に入力される。そして、タイミングコントローラＴＣ１・ＴＣ２は、ソースドライバＳＤ１並びにゲートドライバＧＤ１およびＧＤ２を制御し、タイミングコントローラＴＣ３・ＴＣ４は、ソースドライバＳＤ２並びにゲートドライバＧＤ１およびＧＤ２を制御する。 The video processing circuit VP has 4 channel outputs, which are input to the timing controllers TC1 to TC4. The timing controllers TC1 and TC2 control the source driver SD1 and the gate drivers GD1 and GD2, and the timing controllers TC3 and TC4 control the source driver SD2 and the gate drivers GD1 and GD2.
　これにより、ソースドライバＳＤ１並びにゲートドライバＧＤ１およびＧＤ２は、液晶パネルＬＣＰの左上領域ＡＲ１（画素数２Ｋ１Ｋ）および右上領域ＡＲ２（画素数２Ｋ１Ｋ）を駆動し、ソースドライバＳＤ２並びにゲートドライバＧＤ１およびＧＤ２は、液晶パネルＬＣＰの左下領域ＡＲ３（画素数２Ｋ１Ｋ）および右下領域ＡＲ４（画素数２Ｋ１Ｋ）を駆動する。 Thereby, the source driver SD1 and the gate drivers GD1 and GD2 drive the upper left area AR1 (pixel number 2K1K) and upper right area AR2 (pixel number 2K1K) of the liquid crystal panel LCP, and the source driver SD2 and gate drivers GD1 and GD2 The lower left area AR3 (pixel number 2K1K) and lower right area AR4 (pixel number 2K1K) of the liquid crystal panel LCP are driven.
　なお、液晶パネルＬＣＰの領域分割の仕方は任意であり、各領域を同じサイズとしてもよいし、異なるサイズとしてもよい。 Note that the method of dividing the area of the liquid crystal panel LCP is arbitrary, and each area may have the same size or different sizes.
　また、図１では表示装置３に映像処理回路ＶＰを１個設けているが、複数でもよい。 In FIG. 1, the display device 3 is provided with one video processing circuit VP, but a plurality of video processing circuits VP may be provided.
　また、表示装置３のタイミングコントーラも４個に限定されず、２個あるいは１個でもよい。 Further, the timing controller of the display device 3 is not limited to four, and may be two or one.
　また、液晶パネルの画面（およびフレームデータＤｆ）の分割形式についても任意である。例えば、表示装置１を図１０のように構成し、液晶パネルを水平方向に４分割し、４つの領域Ａｒ１～Ａｒ４を横方向（走査方向と直交する方向）に並べてもよい。 Also, the division format of the screen (and frame data Df) of the liquid crystal panel is arbitrary. For example, the display device 1 may be configured as shown in FIG. 10, the liquid crystal panel may be divided into four in the horizontal direction, and the four regions Ar1 to Ar4 may be arranged in the horizontal direction (direction orthogonal to the scanning direction).
　このように、実施例１によれば、ユーザが、映像出力装置側の４つの出力端子と表示装置側の４つの入力端子とをどのように接続しても正しいフレーム表示が得られ、便利である。 As described above, according to the first embodiment, the user can connect the four output terminals on the video output device side and the four input terminals on the display device side in any way, so that a correct frame display can be obtained, which is convenient. is there.
　〔実施例２〕
　実施例１の映像システムは、図５に示すように、表示装置１と映像出力装置１０とを備える。 [Example 2]
As shown in FIG. 5, the video system according to the first embodiment includes a display device 1 and a video output device 10.
　表示装置１は、４チャネル（４つ）の入力端子ＩＴ１～ＩＴ４（ＨＤＭＩ規格）、マトリクススイッチｍｓｗおよび接続決定回路ｃｄｃを含むデータ振り分け回路１５と、第１～第４チャネルのポートＰＴ１～ＰＴ４を含む映像処理回路ＶＰ、タイミングコントローラＴＣ１～ＴＣ４、ソースドライバＳＤ１～ＳＤ２、ゲートドライバＧＤ１～ＧＤ２、および液晶パネルＬＣＰを備える。液晶パネルＬＣＰは、例えば、横３８４０画素または４０９６画素×縦２１６０画素のいわゆる４Ｋ２Ｋパネル（超高精細液晶パネル）である。なお、各入力端子は、ＨＤＭＩ（High-definition Multimedia Interface）規格のコネクタで構成され、入力端子ＩＴ１～ＩＴ４は、図５に示すように、マトリクススイッチｍｓｗを介して第１～第４チャネルのポートＰＴ１～ＰＴ４に接続される。 The display device 1 includes four channels (four) of input terminals IT1 to IT4 (HDMI standard), a data distribution circuit 15 including a matrix switch msw and a connection determination circuit cdc, and ports PT1 to PT4 of the first to fourth channels. It includes a video processing circuit VP, timing controllers TC1 to TC4, source drivers SD1 to SD2, gate drivers GD1 to GD2, and a liquid crystal panel LCP. The liquid crystal panel LCP is a so-called 4K2K panel (ultra-high-definition liquid crystal panel) having, for example, horizontal 3840 pixels or 4096 pixels × vertical 2160 pixels. Each input terminal is composed of a connector of HDMI (High-definition Multimedia Interface) standard, and the input terminals IT1 to IT4 are ports of the first to fourth channels via a matrix switch msw as shown in FIG. Connected to PT1 to PT4.
　映像出力装置１０は、映像データ生成回路ＶＧＣと、第１～第４チャネル（４つ）の出力端子ＯＴ１～ＯＴ４とを備える。なお、各出力端子は、ＨＤＭＩ規格のコネクタで構成される。映像データ生成回路ＶＧＣは、図６・７に示すように、１フレームのフレームデータＤｆを分割して第１～第４チャネルの映像データＤｖ１～Ｄｖ４を生成し、さらに、映像データＤｖ１～Ｄｖ４それぞれの１ライン目（データイネーブル信号ＤＥがアクティブである１９２０個の有効画素データ）の後にチャネルデータｄｘ１～ｄｘ４を付加した上で、それぞれに対応する第１～第４チャネルの映像端子ＶＴ１～ＶＴ４に並列出力するものである。フレームデータＤｆおよび映像データＤｖ１～Ｄｖ４については、図３に示すように、フレームデータＤｆが４Ｋ２Ｋサイズの単一映像に対応し、映像データＤｖ１～Ｄｖ４それぞれが２Ｋ１Ｋサイズの高精細部分映像（映像データＤｖ１が左上部分、映像データＤｖ２が右上部分、映像データＤｖ３が左下部分、映像データＤｖ４が右下部分）に対応する。 The video output device 10 includes a video data generation circuit VGC and first to fourth channel (four) output terminals OT1 to OT4. Each output terminal is configured with an HDMI standard connector. As shown in FIGS. 6 and 7, the video data generation circuit VGC divides one frame of frame data Df to generate video data Dv1 to Dv4 for the first to fourth channels, and each of the video data Dv1 to Dv4. Channel data dx1 to dx4 are added after the first line (1920 effective pixel data in which the data enable signal DE is active), and then the video terminals VT1 to VT4 of the first to fourth channels corresponding to the channel data dx1 to dx4, respectively. Output in parallel. For the frame data Df and the video data Dv1 to Dv4, as shown in FIG. 3, the frame data Df corresponds to a single video of 4K2K size, and each of the video data Dv1 to Dv4 is a high-definition partial video (video data) of 2K1K size. Dv1 corresponds to the upper left part, video data Dv2 corresponds to the upper right part, video data Dv3 corresponds to the lower left part, and video data Dv4 corresponds to the lower right part).
　図８は、映像出力装置１０と表示装置１との（誤った）接続状態を示すものである。すなわち、映像出力装置１０の出力端子ＯＴ１がケーブルＣＡ１（ＨＤＭＩ規格）を介して表示装置１の入力端子ＩＴ２に接続され、映像出力装置１０の出力端子ＯＴ２がケーブルＣＡ２（ＨＤＭＩ規格）を介して表示装置１の入力端子ＩＴ４に接続され、映像出力装置１０の出力端子ＯＴ３がケーブルＣＡ３（ＨＤＭＩ規格）を介して表示装置１の入力端子ＩＴ１に接続され、映像出力装置１０の出力端子ＯＴ４がケーブルＣＡ４（ＨＤＭＩ規格）を介して表示装置１の入力端子ＩＴ３に接続されている。 FIG. 8 shows a (wrong) connection state between the video output device 10 and the display device 1. That is, the output terminal OT1 of the video output device 10 is connected to the input terminal IT2 of the display device 1 via the cable CA1 (HDMI standard), and the output terminal OT2 of the video output device 10 is displayed via the cable CA2 (HDMI standard). The output terminal OT3 of the video output device 10 is connected to the input terminal IT1 of the display device 1 via the cable CA3 (HDMI standard), and the output terminal OT4 of the video output device 10 is connected to the cable CA4. It is connected to the input terminal IT3 of the display device 1 via (HDMI standard).
　この場合、表示装置１では、映像データＤｖ１内のチャネルデータｄｘ１が、出力端子ＯＴ１および入力端子ＩＴ２を介して接続決定回路ＣＤＣに入力され、映像データＤｖ２内のチャネルデータｄｘ２が、出力端子ＯＴ２および入力端子ＩＴ４を介して接続決定回路ＣＤＣに入力され、映像データＤｖ３内のチャネルデータｄｘ３が、出力端子ＯＴ３および入力端子ＩＴ１を介して接続決定回路ＣＤＣに入力され、映像データＤｖ４内のチャネルデータｄｘ４が、出力端子ＯＴ４および入力端子ＩＴ３を介して接続決定回路ＣＤＣに入力される。 In this case, in the display device 1, the channel data dx1 in the video data Dv1 is input to the connection determination circuit CDC via the output terminal OT1 and the input terminal IT2, and the channel data dx2 in the video data Dv2 is input to the output terminal OT2 and The channel data dx3 in the video data Dv3 is input to the connection determination circuit CDC via the input terminal IT4, and the channel data dx4 in the video data Dv4 is input to the connection determination circuit CDC via the output terminal OT3 and the input terminal IT1. Is input to the connection determination circuit CDC via the output terminal OT4 and the input terminal IT3.
　これにより、接続決定回路ｃｄｃは、出力端子ＯＴ１が入力端子ＩＴ２に接続され、出力端子ＯＴ２が入力端子ＩＴ４に接続され、出力端子ＯＴ３が入力端子ＩＴ１に接続され、出力端子ＯＴ４が入力端子ＩＴ３に接続されていることを認識し、マトリクススイッチｍｓｗに制御信号を送信する。この制御信号を受けて、マトリクススイッチｍｓｗは、入力端子ＩＴ１とポートＰＴ３とを接続し、入力端子ＩＴ２とポートＰＴ１とを接続し、入力端子ＩＴ３とポートＰＴ４とを接続し、入力端子ＩＴ４とポートＰＴ２とを接続する。この結果、第１～第４チャネルの映像データＤｖ１～Ｄｖ４はそれぞれ、第１～第４チャネルのポートＰＴ１～ＰＴ４から映像処理回路ＶＰに入力される。 Thereby, in the connection determination circuit cdc, the output terminal OT1 is connected to the input terminal IT2, the output terminal OT2 is connected to the input terminal IT4, the output terminal OT3 is connected to the input terminal IT1, and the output terminal OT4 is connected to the input terminal IT3. Recognizing that it is connected, a control signal is transmitted to the matrix switch msw. Upon receiving this control signal, the matrix switch msw connects the input terminal IT1 and the port PT3, connects the input terminal IT2 and the port PT1, connects the input terminal IT3 and the port PT4, and connects the input terminal IT4 and the port PT4. Connect PT2. As a result, the video data Dv1 to Dv4 of the first to fourth channels are input to the video processing circuit VP from the ports PT1 to PT4 of the first to fourth channels, respectively.
　映像処理回路ＶＰからは４チャネルの出力があって、それぞれがタイミングコントローラＴＣ１～ＴＣ４に入力される。そして、タイミングコントローラＴＣ１・ＴＣ２は、ソースドライバＳＤ１並びにゲートドライバＧＤ１およびＧＤ２を制御し、タイミングコントローラＴＣ３・ＴＣ４は、ソースドライバＳＤ２並びにゲートドライバＧＤ１およびＧＤ２を制御する。 The video processing circuit VP has 4 channel outputs, which are input to the timing controllers TC1 to TC4. The timing controllers TC1 and TC2 control the source driver SD1 and the gate drivers GD1 and GD2, and the timing controllers TC3 and TC4 control the source driver SD2 and the gate drivers GD1 and GD2.
　これにより、ソースドライバＳＤ１並びにゲートドライバＧＤ１およびＧＤ２は、液晶パネルＬＣＰの左上領域ＡＲ１（画素数２Ｋ１Ｋ）および右上領域ＡＲ２（画素数２Ｋ１Ｋ）を駆動し、ソースドライバＳＤ２並びにゲートドライバＧＤ１およびＧＤ２は、液晶パネルＬＣＰの左下領域ＡＲ３（画素数２Ｋ１Ｋ）および右下領域ＡＲ４（画素数２Ｋ１Ｋ）を駆動する。 Thereby, the source driver SD1 and the gate drivers GD1 and GD2 drive the upper left area AR1 (pixel number 2K1K) and upper right area AR2 (pixel number 2K1K) of the liquid crystal panel LCP, and the source driver SD2 and gate drivers GD1 and GD2 The lower left area AR3 (pixel number 2K1K) and lower right area AR4 (pixel number 2K1K) of the liquid crystal panel LCP are driven.
　なお、液晶パネルＬＣＰの領域分割の仕方は任意であり、各領域を同じサイズとしてもよいし、異なるサイズとしてもよい。 Note that the method of dividing the area of the liquid crystal panel LCP is arbitrary, and each area may have the same size or different sizes.
　また、図５では表示装置３に映像処理回路ＶＰを１個設けているが、複数でもよい。また、表示装置３のタイミングコントーラも４個に限定されず、２個あるいは１個でもよい。 In FIG. 5, one video processing circuit VP is provided in the display device 3, but a plurality of video processing circuits VP may be provided. Further, the number of timing controllers of the display device 3 is not limited to four, and may be two or one.
　また、液晶パネルの画面（およびフレームデータＤｆ）の分割形式についても任意である。例えば、表示装置１を図１１のように構成し、液晶パネルを水平方向に４分割し、４つの領域Ａｒ１～Ａｒ４を横方向（走査方向と直交する方向）に並べてもよい。 Also, the division format of the screen (and frame data Df) of the liquid crystal panel is arbitrary. For example, the display device 1 may be configured as shown in FIG. 11, the liquid crystal panel may be divided into four in the horizontal direction, and the four regions Ar1 to Ar4 may be arranged in the horizontal direction (direction perpendicular to the scanning direction).
　このように、実施例２によっても、ユーザが、映像出力装置側の４つの出力端子と表示装置側の４つの入力端子とをどのように接続しても正しいフレーム表示が得られ、便利である。 As described above, according to the second embodiment as well, a user can connect the four output terminals on the video output device side and the four input terminals on the display device side in any way, so that a correct frame display can be obtained, which is convenient. .
　〔実施例３〕
　図１・５の映像データ生成回路ＶＧＣは、図９に示すように、フレームデータＤｆが４Ｋ２Ｋサイズの単一映像に対応し、第１～第４チャネルの映像データＤｖ１～Ｄｖ４それぞれが２Ｋ１Ｋサイズの低精細全体映像（いわゆる間引き映像）に対応していてもよい。 Example 3
As shown in FIG. 9, the video data generation circuit VGC shown in FIGS. Low-definition whole video (so-called thinned video) may be supported.
　〔まとめ〕
　以上のように、本映像出力装置は、１フレームのフレームデータを分割して第１～第ｎチャネルの映像データを生成する映像データ生成回路と、上記第１～第ｎチャネルの映像データをそれぞれに対応する第１～第ｎチャネルの入力端子で受け付ける表示装置に接続するためのｎ個の出力端子と、第１～第ｎチャネルの入力端子および上記ｎ個の出力端子を介して表示装置から得られるｎ個のチャネルデータ（チャネル情報）に基づいて、第１～第ｎチャネルの映像データをｎ個の出力端子に振り分けるデータ振り分け回路とを備えることを特徴とする。 [Summary]
As described above, the present video output device divides one frame of frame data to generate the first to n-th channel video data and the first to n-th channel video data respectively. N output terminals for connection to display devices that accept at the first to n-th channel input terminals corresponding to, from the display device via the first to n-th channel input terminals and the n output terminals. And a data distribution circuit that distributes video data of the first to n-th channels to n output terminals based on the obtained n channel data (channel information).
　上記構成によれば、映像出力装置側の複数の出力端子と表示装置側の複数の入力端子との接続関係を間違えても正しいフレーム表示が得られ、便利である。 According to the above configuration, even if the connection relationship between the plurality of output terminals on the video output device side and the plurality of input terminals on the display device side is wrong, a correct frame display can be obtained, which is convenient.
　本映像出力装置では、上記１フレームは、高精細度テレビジョン放送の映像規格を超える画素数を含む構成とすることもできる。 In this video output device, the one frame may include a number of pixels exceeding the video standard for high-definition television broadcasting.
　本映像出力装置では、各出力端子がＨＤＭＩ（High-definition Multimedia Interface）規格のコネクタで構成される構成とすることもできる。 In the present video output device, each output terminal may be configured with a connector of HDMI (High-definition Multimedia Interface) standard.
　本映像出力装置では、上記データ振り分け回路はマトリクススイッチを含み、上記マトリクススイッチは映像データ生成回路とｎ個の出力端子とを接続する構成とすることもできる。 In this video output apparatus, the data distribution circuit may include a matrix switch, and the matrix switch may be configured to connect the video data generation circuit and n output terminals.
　本映像出力装置では、上記第１～第ｎチャネルの映像データそれぞれが、上記１フレームの部分映像に対応する構成とすることもできる。 In this video output apparatus, each of the video data of the first to n-th channels may be configured to correspond to the partial video of the one frame.
　本映像出力装置では、上記第１～第ｎチャネルの映像データそれぞれが、上記１フレームの間引き映像に対応する構成とすることもできる。 In the present video output device, each of the video data of the first to nth channels can be configured to correspond to the thinned video of the one frame.
　本映像出力装置では、各チャネルデータは、表示装置内のメモリに格納されたＥＤＩＤ（Extended Display identification Date）に含まれる構成とすることもできる。 In this video output device, each channel data may be included in an EDID (Extended Display Identification Date) stored in a memory in the display device.
　本表示装置は、１フレームのフレームデータを分割して得られる第１～第ｎチャネルの映像データおよび第１～第ｎチャネルの映像データそれぞれに対応するｎ個のチャネルデータを受け付けるｎ個の入力端子と、第１～第ｎチャネルの映像データそれぞれに対応する第１～第ｎチャネルのポートを含む映像処理回路と、上記第１～第ｎチャネルの映像データそれぞれに対応するｎ個のチャネルデータに基づいて、第１～第ｎチャネルの映像データを上記第１～第ｎチャネルのポートに振り分けるデータ振り分け回路とを備えることを特徴とする。 The display apparatus receives n channel data corresponding to the first to n-th channel video data and the first to n-th channel video data obtained by dividing one frame of frame data, respectively. A terminal, a video processing circuit including first to n-th channel ports corresponding to the first to n-th channel video data, and n channel data corresponding to the first to n-th channel video data, respectively. And a data distribution circuit that distributes the first to n-th channel video data to the first to n-th channel ports.
　上記構成によれば、映像出力装置側の複数の出力端子と表示装置側の複数の入力端子との接続関係を間違えても正しいフレーム表示が得られ、便利である。 According to the above configuration, even if the connection relationship between the plurality of output terminals on the video output device side and the plurality of input terminals on the display device side is wrong, a correct frame display can be obtained, which is convenient.
　本表示装置では、上記１フレームは、高精細度テレビジョン放送の映像規格を超える画素数を含む構成とすることもできる。 In the present display device, the one frame may include a number of pixels exceeding the video standard for high-definition television broadcasting.
　本表示装置では、各入力端子がＨＤＭＩ（High-Definition Multimedia Interface）規格のコネクタで構成される構成とすることもできる。 In the present display device, each input terminal may be configured by a connector of HDMI (High-Definition Multimedia Interface) standard.
　本表示装置では、上記データ振り分け回路はマトリクススイッチを含み、上記マトリクススイッチは、ｎ個の入力端子と第１～第ｎチャネルの映像処理回路とを接続する構成とすることもできる。 In the present display device, the data distribution circuit may include a matrix switch, and the matrix switch may be configured to connect n input terminals and first to n-th channel video processing circuits.
　本表示装置では、上記第１～第ｎチャネルの映像データそれぞれが、上記１フレームの部分映像に対応する構成とすることもできる。 In the present display device, each of the video data of the first to n-th channels can be configured to correspond to the partial video of the one frame.
　本表示装置では、上記第１～第ｎチャネルの映像データそれぞれが、上記１フレームの間引き映像に対応する構成とすることもできる。 In the present display device, each of the video data of the first to n-th channels can be configured to correspond to the thinned video of the one frame.
　本発明は上記の実施の形態に限定されるものではなく、上記実施の形態を公知技術や技術常識に基づいて適宜変更したものやそれらを組み合わせて得られるものも本発明の実施の形態に含まれる。また、各実施の形態で記載した作用効果等もほんの例示に過ぎない。 The present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on known techniques and common general knowledge or combinations thereof are also included in the embodiments of the present invention. It is. In addition, the operational effects described in each embodiment are merely examples.
　本発明は、例えば超高精細の液晶表示装置に好適である。 The present invention is suitable for, for example, an ultra-high definition liquid crystal display device.
　１　表示装置
　５・１５　データ振り分け回路
　１０　映像出力装置
　ＬＣＰ　液晶パネル
　ＭＳＷ　ｍｓｗ　マトリクススイッチ
　ＴＣ１～ＴＣ２　タイミングコントローラ
　ＤＲ１～ＤＲ２　ドライバ回路
　ＶＰ　映像処理回路
　ＣＤＣ　ｃｄｃ　接続決定回路
　ＶＴ１～ＶＴ４　映像端子
　ＰＴ１～ＰＴ４　ポート
　ＩＴ１～ＩＴ４　（ＨＤＭＩ規格の）入力端子
　ＯＴ１～ＯＴ４　（ＨＤＭＩ規格の）出力端子
　ＣＡ１～ＣＡ４　（ＨＤＭＩ規格の）ケーブル
　Ｄｖ１～Ｄｖ４　映像データ
　Ｄｆ　フレームデータ
　Ｄｘ１～Ｄｘ４　チャネルデータ
　ｄｘ１～ｄｘ４　チャネルデータ DESCRIPTION OF SYMBOLS 1 Display device 5.15 Data distribution circuit 10 Video output device LCP Liquid crystal panel MSW msw Matrix switch TC1 to TC2 Timing controller DR1 to DR2 Driver circuit VP Video processing circuit CDC cdc Connection determination circuit VT1 to VT4 Video terminal PT1 to PT4 Port IT1 to IT4 (HDMI standard) input terminal OT1 to OT4 (HDMI standard) output terminal CA1 to CA4 (HDMI standard) cable Dv1 to Dv4 Video data Df Frame data Dx1 to Dx4 Channel data dx1 to dx4 Channel data

Claims (13)

  1. 　１フレームのフレームデータを分割して第１～第ｎチャネルの映像データを生成する映像データ生成回路と、
    　上記第１～第ｎチャネルの映像データをそれぞれに対応する第１～第ｎチャネルの入力端子で受け付ける表示装置と接続するためのｎ個の出力端子と、
    　第１～第ｎチャネルの入力端子および上記ｎ個の出力端子を介して表示装置から得られるｎ個のチャネルデータに基づいて、第１～第ｎチャネルの映像データをｎ個の出力端子に振り分けるデータ振り分け回路とを備える映像出力装置。     A video data generation circuit that divides frame data of one frame to generate video data of the first to n-th channels;
    N output terminals for connection to display devices that receive the first to n-th channel video data at the corresponding first to n-th channel input terminals;
    Based on the n channel data obtained from the display device through the first to n-th channel input terminals and the n output terminals, the first to n-th channel video data is distributed to the n output terminals. A video output device comprising a data distribution circuit.
  2. 　上記１フレームは、高精細度テレビジョン放送の映像規格を超える画素数を含む請求項１記載の映像出力装置。 The video output device according to claim 1, wherein the one frame includes a number of pixels exceeding a video standard for high-definition television broadcasting.
  3. 　各出力端子がＨＤＭＩ（High-definition Multimedia Interface）規格のコネクタで構成される請求項１に記載の映像出力装置。 The video output device according to claim 1, wherein each output terminal is configured by a connector of HDMI (High-definition Multimedia Interface) standard.
  4. 　上記データ振り分け回路はマトリクススイッチを含み、
    　上記マトリクススイッチは映像データ生成回路とｎ個の出力端子とを接続する請求項１に記載の映像出力装置。     The data distribution circuit includes a matrix switch,
    2. The video output device according to claim 1, wherein the matrix switch connects a video data generation circuit and n output terminals.
  5. 　上記第１～第ｎチャネルの映像データそれぞれが、上記１フレームの部分映像に対応する請求項１に記載の映像出力装置。 The video output device according to claim 1, wherein each of the video data of the first to n-th channels corresponds to the partial video of the one frame.
  6. 　上記第１～第ｎチャネルの映像データそれぞれが、上記１フレームの間引き映像に対応する請求項１に記載の映像出力装置。 2. The video output device according to claim 1, wherein each of the video data of the first to n-th channels corresponds to the thinned video of the one frame.
  7. 　各チャネルデータは、表示装置内のメモリに格納されたＥＤＩＤ（Extended Display identification Date）に含まれる請求項１に記載の映像出力装置。 The video output device according to claim 1, wherein each channel data is included in an EDID (Extended Display identification Date) stored in a memory in the display device.
  8. 　１フレームのフレームデータを分割して得られる第１～第ｎチャネルの映像データおよび第１～第ｎチャネルの映像データそれぞれに対応するｎ個のチャネルデータを受け付けるｎ個の入力端子と、
    　第１～第ｎチャネルの映像データそれぞれに対応する第１～第ｎチャネルのポートを含む映像処理回路と、
    　上記第１～第ｎチャネルの映像データそれぞれに対応するｎ個のチャネルデータに基づいて、第１～第ｎチャネルの映像データを上記第１～第ｎチャネルのポートに振り分けるデータ振り分け回路とを備える表示装置。     N input terminals for receiving n channel data corresponding to the first to n-th channel video data and the first to n-th channel video data obtained by dividing one frame of frame data;
    A video processing circuit including first to n-th channel ports corresponding to first to n-th channel video data;
    A data distribution circuit for distributing the first to n-th channel video data to the first to n-th channel ports based on n channel data corresponding to the first to n-th channel video data, respectively; Display device.
  9. 　上記１フレームは、高精細度テレビジョン放送の映像規格を超える画素数を含む請求項８記載の表示装置。 The display device according to claim 8, wherein the one frame includes a number of pixels exceeding a video standard for high-definition television broadcasting.
  10. 　各入力端子がＨＤＭＩ（High-Definition Multimedia Interface）規格のコネクタで構成される請求項８に記載の表示装置。 The display device according to claim 8, wherein each input terminal is configured by a connector of HDMI (High-Definition Multimedia Interface) standard.
  11. 　上記データ振り分け回路はマトリクススイッチを含み、
    　上記マトリクススイッチは、ｎ個の入力端子と第１～第ｎチャネルの映像処理回路とを接続する請求項８に記載の表示装置。     The data distribution circuit includes a matrix switch,
    9. The display device according to claim 8, wherein the matrix switch connects n input terminals and first to n-th channel video processing circuits.
  12. 　上記第１～第ｎチャネルの映像データそれぞれが、上記１フレームの部分映像に対応する請求項８に記載の表示装置。 The display device according to claim 8, wherein each of the video data of the first to n-th channels corresponds to the partial video of the one frame.
  13. 　上記第１～第ｎチャネルの映像データそれぞれが、上記１フレームの間引き映像に対応する請求項８に記載の表示装置。 The display device according to claim 8, wherein each of the video data of the first to n-th channels corresponds to the thinned video of the one frame.
PCT/JP2012/079178 2011-11-21 2012-11-09 Video output device and display device WO2013077203A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011254405 2011-11-21
JP2011-254405 2011-11-21

Publications (1)

Publication Number Publication Date
WO2013077203A1 true WO2013077203A1 (en) 2013-05-30

Family

ID=48469651

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/079178 WO2013077203A1 (en) 2011-11-21 2012-11-09 Video output device and display device

Country Status (1)

Country Link
WO (1) WO2013077203A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016038846A1 (en) * 2014-09-08 2016-03-17 Canon Kabushiki Kaisha Image output apparatus, image display apparatus, control method of image output apparatus, and control method of image display apparatus
JP2016057604A (en) * 2014-09-08 2016-04-21 キヤノン株式会社 Image output device, image display device, control method of image output device, and control method of image display device
US20160373685A1 (en) * 2015-02-14 2016-12-22 Boe Technology Group Co., Ltd. Video Controller, Playback Controller and Display System

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10308940A (en) * 1997-05-09 1998-11-17 Fuji Electric Co Ltd Industrial television camera monitor
JP2000341335A (en) * 1999-05-31 2000-12-08 Toshiba Corp Transmission line changeover system
JP2001175230A (en) * 1999-12-21 2001-06-29 Nanao Corp Display device
JP2005301131A (en) * 2004-04-15 2005-10-27 Sony Corp Server device, and display device and method
JP2011040004A (en) * 2009-08-18 2011-02-24 Sony Corp Image processing apparatus and image processing method
JP2011135202A (en) * 2009-12-22 2011-07-07 Sony Corp Video signal processor, and video signal processing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10308940A (en) * 1997-05-09 1998-11-17 Fuji Electric Co Ltd Industrial television camera monitor
JP2000341335A (en) * 1999-05-31 2000-12-08 Toshiba Corp Transmission line changeover system
JP2001175230A (en) * 1999-12-21 2001-06-29 Nanao Corp Display device
JP2005301131A (en) * 2004-04-15 2005-10-27 Sony Corp Server device, and display device and method
JP2011040004A (en) * 2009-08-18 2011-02-24 Sony Corp Image processing apparatus and image processing method
JP2011135202A (en) * 2009-12-22 2011-07-07 Sony Corp Video signal processor, and video signal processing method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016038846A1 (en) * 2014-09-08 2016-03-17 Canon Kabushiki Kaisha Image output apparatus, image display apparatus, control method of image output apparatus, and control method of image display apparatus
JP2016057604A (en) * 2014-09-08 2016-04-21 キヤノン株式会社 Image output device, image display device, control method of image output device, and control method of image display device
CN106687915A (en) * 2014-09-08 2017-05-17 佳能株式会社 Image output apparatus, image display apparatus, control method of image output apparatus, and control method of image display apparatus
EP3191933A4 (en) * 2014-09-08 2018-05-23 Canon Kabushiki Kaisha Image output apparatus, image display apparatus, control method of image output apparatus, and control method of image display apparatus
CN106687915B (en) * 2014-09-08 2019-09-27 佳能株式会社 Image output device, image display and its control method and medium
US10430143B2 (en) 2014-09-08 2019-10-01 Canon Kabushiki Kaisha Image output apparatus, image display apparatus, control method of image output apparatus, and control method of image display apparatus
US20160373685A1 (en) * 2015-02-14 2016-12-22 Boe Technology Group Co., Ltd. Video Controller, Playback Controller and Display System
JP2018512747A (en) * 2015-02-14 2018-05-17 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． Video controller, playback controller and display system
EP3258685A4 (en) * 2015-02-14 2018-10-24 Boe Technology Group Co. Ltd. Video controller, play controller and display system

Similar Documents

Publication Publication Date Title
CN103544130B (en) A kind of windows display equipment and display packing
US10482847B2 (en) Driving method and driving apparatus for display panel, and display device
US9560331B2 (en) Signal processing method, signal processing system and display device
US10629283B2 (en) Display panel and display device
KR20050028816A (en) Using packet transfer for driving lcd panel driver electronics
KR20050022406A (en) Multi screen display device and control method thereof
JPS63163396A (en) Matrix type flat panel display device
US20140198193A1 (en) Head mount display and display control method
CN111868811A (en) Semiconductor device, display device, and in-vehicle display system
WO2013077203A1 (en) Video output device and display device
KR100881142B1 (en) Led display apparatus
CN114267293B (en) Display device and display method thereof
US9350904B2 (en) Video signal processing apparatus configured to display a video having a resolution higher than full HD, video display apparatus, and electronic device
US20170195668A1 (en) Television pcb testing device
US9888223B2 (en) Display processing system, display processing method, and electronic device
KR20090054836A (en) The apparatus for displaying image and the method thereof
JP2009171183A (en) Video display device
CN103856737A (en) Frame rate converter and timing controller and processing apparatus and method thereof
EP2682937A1 (en) Display apparatus and control method thereof
US20190189074A1 (en) Display control device and liquid crystal display device including display control device
JP2014003438A (en) Video display device, video system, and video display method
JP2002040993A5 (en)
WO2013094259A1 (en) Display device
KR20090063702A (en) Signal processing apparatus and control method thereof
KR100951718B1 (en) Display control method and system for multivision

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12851403

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12851403

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP