JP2007324390A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and the manufacturing method of the same having a CMOS (complementary metal oxide semiconductor) transistor whose threshold voltage is reduced and controlled, as a work function is controlled in either one of a p-type or an n-type MOSFET (metal oxide semiconductor field effect transistor). <P>SOLUTION: The semiconductor device 100 includes a semiconductor substrate 101, a first gate electrode 131 formed on the n-type MOSFET in the semiconductor substrate 101, and a second gate electrode 132 formed on the p-type MOSFET in the semiconductor substrate 101. The first gate electrode 131 comprises a silicon layer 107, and a first metal silicide layer 118 formed on the silicon layer 107 and the second gate electrode 132 comprises a second metal silicide layer 119 with excessive metal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device which is a field effect transistor having a metal silicide gate, and a method for manufacturing the same.

  2. Description of the Related Art In accordance with recent technological progress related to higher integration and higher speed of semiconductor devices, MOSFETs (Metal Oxide Semiconductor Feild Effect Transistors) have been miniaturized. Along with this, when the gate insulating film becomes thinner, an increase in the gate leakage current due to the tunnel current becomes obvious.

In order to suppress this problem, the use of a high dielectric constant material that is a metal oxide such as HfO ₂ or ZrO ₂ has been studied as a material for forming a gate insulating film (see, for example, Non-Patent Document 1). . In this way, the equivalent SiO ₂ film thickness can be reduced and the actual physical film thickness can be increased, and as a result, an increase in leakage current can be suppressed.

  On the other hand, metals or metal silicides have begun to be used as electrode materials in place of conventional doped silicon. This is because, in the case of a doped silicon electrode (a silicon electrode doped with impurities), the capacity is reduced due to electrode depletion, whereas in the case of a metal electrode or a metal silicide electrode, such capacity reduction is avoided. This is because it can be done. As a result, the effective gate insulating film can be further thinned.

  In addition, when a gate insulating film made of a high dielectric constant material is used together with a silicon electrode, leakage current increases due to the bond between silicon and metal formed at the interface between the silicon electrode and the gate insulating film. In addition, it is difficult to control the transistor threshold due to Fermi level pinning. However, these can be avoided by using metal electrodes instead of silicon electrodes.

  Next, selection of an electrode material will be considered from the viewpoint of a semiconductor device manufacturing method.

  In the case of the conventional silicon electrode, the n-type and p-type MOSFETs in the CMOSFET could be easily formed by switching the ion implantation species using a resist cover. However, in the case of a metal electrode, since the conductivity type is determined by the work function of the material itself, different materials must be used for forming n-type and p-type MOSFETs. For this reason, the formation process of a metal electrode is more complicated compared with a silicon electrode.

  On the other hand, since the metal silicide electrode is formed by depositing a metal on the silicon electrode and then heat-treating it, there is an advantage that the manufacturing process is simpler than the metal electrode (for example, (Refer nonpatent literature 2).

  Here, the metal silicide also has an inherent work function. Therefore, when forming n-type and p-type MOSFETs having metal silicide electrodes, it is necessary to select a material for obtaining an appropriate threshold value.

  When nickel silicide is considered as one specific example, the work function of nickel silicide corresponds to an intermediate position (mid gap) with respect to the band gap of silicon. For this reason, the threshold voltage generally increases in both n-type and p-type as compared with the case of the doped silicon electrode.

  Such an increase in threshold voltage can be reduced by implanting a dopant having a reverse polarity to the channel portion of the substrate. However, when doping is performed on the channel in this way, carrier mobility is deteriorated, and threshold voltage control becomes more difficult particularly in the case of a short channel region.

  Also in this regard, when the gate insulating film is a silicon oxide film, a certain threshold voltage can be controlled by performing ion implantation on the silicon electrode before silicidation and controlling the ion species and dose (for example, , See Non-Patent Document 3).

  However, when the gate insulating film is a metal oxide film, it is reported that ion implantation into the silicon electrode before silicidation is less effective than when the gate oxide film is a silicon oxide film (also Non-Patent Document 3). See). This is because when the metal oxide film is, for example, a hafnium oxide film, the electrical level formed by the bond between hafnium and silicon is fixed in the vicinity of the conduction band of silicon. Due to this phenomenon called the Fermi level pinning effect, the doping effect on the silicon electrode is small. Further, for the p-type MOSFET, the increase in threshold is larger and does not decrease below about 0.5V.

  Non-Patent Document 4 proposes changing the work function of metal silicide by adjusting the metal composition and crystal phase of metal silicide as a method of changing the threshold voltage.

  In particular, for the high threshold voltage of the p-type MOSFET, the work function is increased and the threshold value is lowered by using metal silicide that contains excess metal (containing metal in excess of silicon). Has succeeded.

  On the other hand, for n-type MOSFETs, it is necessary to reduce the work function as opposed to p-type MOSFETs, so that metal silicide with excess metal cannot be used. In addition, even when the ratio of metal to silicon is close to 1: 1, metal silicide is originally a midgap material, which raises the threshold. From the above, although there is a demerit of capacity reduction due to depletion, it is desirable to use a silicon electrode for n-type MOSFET from the viewpoint of lowering the threshold.

  Further, Patent Document 1 and Non-Patent Document 5 disclose a manufacturing method in which the composition ratio and crystal phase of a metal silicide layer to be formed are set by changing the film thickness of the silicon layer before performing metal silicidation. ing.

  That is, for the n-type MOSFET, the thickness of the silicon layer is increased. As a result, even after the silicon layer reacts with the metal film of a certain thickness formed on it and becomes silicide, the upper part is silicided, but the lower part (near the gate insulating film) is silicided. A gate electrode that is not silicon can be formed.

On the other hand, the silicon film thickness is reduced for the p-type MOSFET. Thus, the silicidation reaction between the silicon layer and the metal film formed thereon reaches the lower part of the electrode (insulating film upper interface), and the gate electrode of the p-type MOSFET can be a metal silicide electrode.
JP 2005-228868 A Journal of Applied Physics. 89, 5243, 2001. GDWilk et al. International Electron Material Meeting, 825 pages, 2001. B.Tavel et al International Electron Material Meeting, 83 pages, 2004. T.Nabatame et al Electron Device Letter, 27, 34 pages. JGKittl et al. International Electron Material Meeting, 95 pages, 2004. T.Aoyama et al.

  However, the conventional semiconductor device has the following problems.

  As described above, it is necessary to control the composition of the metal silicide as the material constituting the gate electrode of the p-type and n-type MOSFETs. The composition of such metal silicide greatly depends on the thickness of the silicon layer before silicidation. For this reason, it is very important to control the film thickness to be constant even for devices having different gate lengths and different gate widths. However, since it is difficult to control the height of the silicon electrode, solving this problem is one of the problems.

  In addition, a p-type MOSFET having an electrode made of an excessive metal silicide has a problem that a defect is formed in the gate insulating film located immediately below the silicon layer when the silicon layer is silicided. That is, since the silicidation reaction of silicon is accompanied by volume expansion, stress is applied to the gate insulating film. For this reason, pinholes or crystal grains may be formed in the gate insulating film depending on conditions, and metal may diffuse through these to react with the silicon substrate under the gate insulating film. When this occurs, a silicide layer is formed on the substrate via the gate insulating film, and the insulating property by the gate insulating film no longer functions. Therefore, the solution of this is one of the problems.

  On the other hand, for the n-type MOSFET, the silicon layer may be thickened so that the metal element does not reach the interface between the silicon layer and the gate insulating film. However, in a silicon layer in which a region is divided as a gate electrode as in the case of forming an actual transistor structure, a metal element is not only a portion of a metal film corresponding to the gate electrode but also a portion outside the portion corresponding to the gate electrode. Is also supplied by surface diffusion. As a result, the metal element tends to be supplied excessively.

  As a result, MOSFETs having different gate lengths exist in actual devices, and therefore, metal silicide is more easily formed in a gate electrode having a short gate length in which a relatively large amount of metal is supplied by surface diffusion. When the metal silicide reaches the gate insulating film, the threshold value of such a gate electrode varies greatly. This is because the work function of the electrode is changed from that of silicon to that of metal silicide.

  As described above, it is necessary to control the thickness of the silicon layer before silicidation for the p-type MOSFET, and the thickness of the metal silicide layer after silicidation for the n-type MOSFET. Need to control. Therefore, it is a problem to perform these reliably.

  In view of the above problems, an object of the present invention is to provide a transistor structure in which a threshold voltage is reduced and controlled by controlling a work function in a CMOSFET having a metal silicide gate electrode. Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of controlling both the thickness of a silicon layer before silicidation in a p-type MOSFET and the thickness of a metal silicide layer after silicidation in an n-type MOSFET.

  In order to reduce and control the threshold voltage of each of the n-type and p-type MOSFETs of the CMOSFET, a silicon electrode is used for the n-type MOSFET and a metal-excess metal silicide electrode is used for the p-type MOSFET. The inventors have conceived that a combination is most desirable.

  Therefore, a semiconductor device of the present invention for achieving the above object includes a semiconductor substrate, a first gate electrode formed on an n-type MOSFET region in the semiconductor substrate, and a p-type MOSFET region in the semiconductor substrate. The first gate electrode includes a silicon layer and a first metal silicide layer formed thereon, and the second gate electrode includes a second metal-excess second electrode. The metal silicide layer.

  Here, the metal silicide having excess metal is a metal silicide in which the proportion of the metal element is larger than the proportion of silicon and the atomic percent exceeds 50%.

  According to the semiconductor device of the present invention, as described below, a low threshold voltage can be realized in both the n-type MOSFET and the p-type MOSFET.

  With respect to the first gate electrode of the n-type MOSFET, a lower threshold voltage is realized because the lower portion in contact with the gate insulating film is a silicon layer. Further, a first metal silicide layer is stacked on the silicon layer. Since the metal silicide layer has a lower resistance than the silicon layer, the gate delay time can be shortened to increase the device operation speed.

  In addition, since the second gate electrode of the p-type MOSFET is a full silicide electrode having a second metal silicide layer with excess metal, a low threshold voltage can be realized even in the p-type MOSFET.

  The second metal silicide layer preferably has a composition in which the metal is 60% or more. Thereby, reduction of the threshold voltage in p-type MOSFET is implement | achieved reliably.

  The metal contained in the first metal silicide layer and the second metal silicide layer preferably contains at least one of nickel, cobalt, titanium, and platinum. By using a metal silicide containing such a metal, the semiconductor device of the present invention can be specifically realized.

  In addition, a gate insulating film that is a metal oxide film is preferably provided between the semiconductor substrate and the first gate electrode and the second gate electrode.

  When the gate insulating film of each MOSFET is a metal oxide film, the control of the threshold voltage by ion implantation into the silicon electrode before silicidation has little effect. On the other hand, the effect of the present invention is remarkably exhibited even when the gate insulating film of the MOSFET is a metal oxide film. However, the effect of the semiconductor device of the present invention also functions when the gate insulating film is a silicon oxide film or a silicon nitride film.

  The metal contained in the metal oxide film preferably contains at least one of hafnium, zirconium, titanium, tantalum, lanthanum, and aluminum. Such a metal oxide film can be used as a gate insulating film in the semiconductor device of the present invention.

  The metal oxide film preferably further contains silicon.

  Since the metal oxide film contains silicon, the crystallization temperature becomes high and the crystallization becomes difficult. Thereby, it is possible to suppress diffusion of metal from the gate electrode to the channel portion through the gate insulating film.

  In addition, it is preferable that a protective film is formed between the gate oxide film and the first gate electrode and the second gate electrode, respectively. In this way, it is possible to prevent a defect from being induced in the gate insulating film when silicidation is performed, and as a result, it is possible to reduce a leakage current caused by the defect and improve a manufacturing yield.

  The first gate electrode preferably includes a barrier layer between the silicon layer and the first metal silicide layer.

  In this case, a silicon layer with a controlled film thickness is realized, so that the threshold voltage in the n-type MOSFET can be controlled more reliably.

  The barrier layer is preferably a silicon oxide film, silicon oxynitride or silicon oxynitride film. Furthermore, the silicon oxide film is preferably a silicon oxide film formed by wet processing.

  In this way, a barrier layer for surely controlling the film thickness of the silicon layer and the first metal silicide layer constituting the first gate electrode is realized.

  Moreover, it is preferable that the film thickness of a barrier layer is 1.0 nm or more and 1.5 nm or less.

  In this case, since the barrier layer is sufficiently thick, the thickness of the silicon layer and the first metal silicide layer can be reliably controlled, and since the barrier layer is sufficiently thin, the silicon layer and the first metal silicide layer Is maintained by the tunnel effect.

  Next, in order to achieve the above object, in the p-type MOSFET included in the CMOSFET, the thickness of the silicon layer to be initially formed is surely controlled to make it thinner, so that the ratio of metal to silicon becomes more metal-excessive. The inventors of this application have come up with an idea. At this time, it is considered that the metal excess can be achieved also by promoting the diffusion of the metal at a high temperature for a long time for the silicidation.

  Therefore, the method for manufacturing a semiconductor device of the present invention includes a step (a) of forming a gate insulating film on a semiconductor substrate, a step (b) of forming a first semiconductor layer on the gate insulating film, A step (c) of forming a barrier layer on the semiconductor layer, a step (d) of forming a second semiconductor layer on the barrier layer, and patterning the first semiconductor layer, the barrier layer, and the second semiconductor layer. A step (e) of forming the first gate electrode and the second gate electrode, a step (f) of removing the second semiconductor layer and the barrier layer in the second gate electrode, A step (g) of forming a metal film on the second semiconductor layer in the gate electrode and the first semiconductor layer in the second gate electrode; and the second semiconductor layer and the second in the first gate electrode The first semiconductor layer in the gate electrode is formed with a metal film and The reaction and a step of silicidation (h) by.

  According to the semiconductor device manufacturing method of the present invention, the threshold voltage is reduced in both the n-type MOSFET having the first gate electrode and the p-type MOSFET having the second gate electrode. The reasons will be explained below.

  First, since the barrier layer is formed when siliciding the first gate electrode in the step (h), the first semiconductor layer located under the barrier layer is prevented from being silicided. It is peeling. That is, only the second semiconductor layer is silicided. As a result, in the first gate electrode, the thickness of both the first semiconductor layer and the metal silicide layer formed thereon can be reliably controlled. In other words, the variation in film thickness can be reduced and the desired film thickness can be reliably obtained.

  For this reason, it is prevented that the metal silicide layer becomes thick and reaches the gate insulating film, and control of the threshold voltage in the n-type MOSFET is realized.

  Next, the second gate electrode will be described. When the second semiconductor layer and the barrier layer are formed of different materials, the step of removing the second semiconductor layer such as etching can be stopped by the barrier layer in the step (f). Furthermore, it is possible to remove the barrier layer while avoiding that the first semiconductor layer is shaved. For this reason, the film thickness of the first semiconductor layer in the second gate electrode can be easily controlled. In other words, a predetermined film thickness can be reliably obtained with small variations.

  As a result, the composition when the first semiconductor layer in the second gate electrode is silicided through steps (g) and (h) can be controlled. This realizes reduction and control of the threshold voltage in the p-type MOSFET.

  As described above, the barrier layer formed between the first semiconductor layer and the second semiconductor layer is used for controlling the progress of silicidation in the first gate electrode, and the second gate electrode. Is used to control the film thickness of the semiconductor layer for silicidation. In the semiconductor device manufactured in this way, as described above, the threshold voltage is reduced and controlled for both the n-type MOSFET and the p-type MOSFET.

  Note that a step of forming a hard mask on the second semiconductor layer is further provided after the step (d) and before the step (e). In the step (e), the first is performed by etching using the hard mask. The gate electrode and the second gate electrode are preferably formed.

  Further, after the step (e) and before the step (f), a step of further forming an interlayer insulating film on the semiconductor substrate so that the upper surfaces of the first gate electrode and the second gate electrode are exposed. It is preferable to provide.

  Through these steps, the manufacture of the semiconductor device can be realized more reliably and specifically.

  In addition, it is preferable to further include a step of performing ion implantation into the first semiconductor layer and the second semiconductor layer. Thereby, the conductivity type of the first and second gate electrodes can be controlled.

  It is preferable that the method further includes a step of forming sidewalls on the side surfaces of the first gate electrode and the second gate electrode after the step (e) and before the step (f).

  In addition, it is preferable that the method further includes a step of forming a p-type well in a region of the semiconductor substrate where the first gate electrode is formed before the step (a).

  In addition, it is preferable that the method further includes a step of forming an n-type well in the region where the second gate electrode is formed in the semiconductor substrate before the step (a).

  Moreover, it is preferable to form an element isolation region in the semiconductor substrate before the step (a).

  Through these steps, a semiconductor device having each component can be manufactured.

  According to the semiconductor device and the manufacturing method thereof of the present invention, in the n-type and p-type MOSFETs, the thickness and composition of the metal silicide layer can be controlled, so that the threshold voltage of each MOSFET can be reduced. At the same time, variations in threshold voltage can be reduced, so that device characteristics can be stabilized and manufacturing yield can be improved.

  Here, since the metal silicide composition constituting the gate electrode of the p-type MOSFET is excessive in metal, the threshold voltage can be reduced even when a high dielectric constant film is used as the gate insulating film.

  Hereinafter, a semiconductor device and a manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.

  First, FIG. 1 schematically shows a semiconductor device 100 according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 is formed using a silicon substrate 101 as a semiconductor substrate. The surface of the silicon substrate 101 is partitioned by element isolation 102. Although the trench type element isolation 102 is used here, for example, a LOCOS isolation technique may be used.

  A p-type well 103 into which boron is ion-implanted and an n-type well 104 into which arsenic or phosphorus is ion-implanted are formed on the silicon substrate 101 partitioned by the element isolation. Further, a gate oxide film 105, which is a hafnium oxide film, is formed as a gate insulating film on the p-type well 103 and the n-type well 104, and a silicon oxide film, a silicon nitride film, or the like is formed thereon. A protective film 106 is formed. That is, both the gate oxide film 105 and the protective film 106 function as a gate insulating film.

  On the p-type well 103, a first silicon layer 107 as a semiconductor layer is formed on the protective film 106, and a barrier layer 108 made of a silicon oxide film or the like is formed thereon. Further, a first metal silicide layer 118 is formed on the barrier layer 108. Here, the first gate layer 131 is constituted by the first silicon layer 107, the barrier layer 108, and the first metal silicide layer 118, and serves as the gate electrode of the n-type MOSFET.

  In addition, on the n-type well 104, a second metal silicide layer 119 containing excessive metal is formed on the protective film 106, and this serves as a p-type as the second gate electrode 132 which is a full silicide electrode. This is the gate electrode of the MOSFET.

Note that the first metal silicide layer 118 is made of, for example, NiSi, that is, a silicide containing each atom at a ratio of 1 Si atom to 1 Ni atom. The second metal silicide layer 119 is made of, for example, Ni ₃ Si, that is, a silicide containing each atom at a ratio of 1 Si atom to 3 Ni atoms.

  A sidewall 112 is formed so as to cover the side surfaces of the first gate electrode 131 and the second gate electrode 132. Further, in the p-type well 103 and the n-type well 104, extension regions 111 are formed in regions on both sides of the first gate electrode 131 and the second gate electrode 132, respectively, and further outside the source / drain regions 113 ( The source region and the drain region are collectively referred to as above).

  Thus, the source / drain region 113, the gate oxide film 105 and the protective film 106, and the first gate electrode 131 constitute an n-type MOSFET, and the source / drain region 113, the gate oxide film 105. The protective film 106 and the second gate electrode 132 constitute a p-type MOSFET.

  A silicide layer 114 is formed on the source / drain region 113. Further, a first interlayer insulating film 115 and a second interlayer insulating film 120 laminated thereon are formed on the silicon substrate 101, and the n-type MOSFET and the p-type MOSFET are covered. Contact plugs 121 are formed in the first interlayer insulating film 115 and the second interlayer insulating film 120, and electrical connection to the source / drain regions 113, the first gate electrode 131, and the second gate electrode 132 is performed. It is.

  As described above, in the first gate electrode 131 which is the gate electrode of the n-type MOSFET formed on the p-type well 103, the first metal silicide layer 118 is stacked on the first silicon layer 107. Structure. As will be described later, the thicknesses of the first silicon layer 107 and the first metal silicide layer 118 are controlled by the barrier layer 108 so that the thickness of the metal silicide layer 118 increases and reaches the protective film 106. This is prevented. As a result, reduction and control of the threshold voltage of the n-type MOSFET are realized.

  The second gate electrode 132 that is the gate electrode of the p-type MOSFET formed on the n-type well 104 is composed of the second metal silicide layer 119 controlled to have an excessive metal composition. Thereby, the reduction and control of the threshold voltage of the p-type MOSFET are also realized.

  The protective film 106 is provided to prevent the metal element from diffusing into the gate oxide film 105 when the second metal silicide layer 119 is formed. When a metal such as nickel used for silicidation diffuses into the gate oxide film 105, the metal may react with the silicon substrate 101 under the gate oxide film 105 to form a metal silicide. When this occurs, the gate oxide film 105 does not function as an insulating film. Therefore, a protective film 106 is formed on the gate oxide film 105 in order to prevent diffusion of the metal element into the gate oxide film 105.

  Here, the diffusion of the metal element with respect to the gate oxide film 105 described above becomes a problem particularly when crystallization occurs in the gate oxide film 105 and a grain boundary (crystal boundary) is easily formed. Specifically, a problem easily occurs when the gate oxide film 105 is formed of a metal oxide film. For this reason, it is desirable to provide the protective film 106 in the case of this embodiment using the haonium oxide film.

  On the other hand, when the gate oxide film 105 is not a metal oxide film, specifically, when a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used, the hownium composition further has a haonium composition of 50% or less. The protective film 106 is not necessary when using nium silicate. This is because a gate insulating film containing silicon is not easily crystallized because of a high crystallization temperature, and a grain boundary is also difficult to be formed.

  Next, the manufacturing process of the semiconductor device 100 will be described. 2 (a)-(d), 3 (a)-(d), 4 (a)-(d), 5 (a)-(d) and 6 (a)-(c). FIG. 6 is a diagram for explaining a method for manufacturing the semiconductor device 100.

  First, as shown in FIG. 2A, a trench type element isolation 102 is formed on a silicon substrate 101 using a known method. In addition to the trench type element isolation used here, LOCOS isolation may be used. One of the regions partitioned by the element isolation 102 is representatively shown as an nMOS region A in which an n-type MOSFET is formed, and the other is represented as a pMOS region B in which a p-type MOSFET is formed.

  Next, ion implantation is performed on the silicon substrate 101 partitioned by the element isolation 102 to form the p-type well 103 and the n-type well 104. For this purpose, after applying a resist on the silicon substrate 101, the resist is removed from the nMOS region A using a known lithography technique, and boron is implanted into the region. Thereby, the p-type well 103 is formed. Next, arsenic or phosphorus is ion-implanted into the pMOS region B using the lithography technique in the same manner to form the n-type well 104. FIG. 2B shows a state where ion implantation for forming the n-type well 104 is performed using the resist 140. Thereafter, the resist 140 is removed.

  Thereafter, the natural oxide film in the active region is removed using, for example, diluted hydrofluoric acid aqueous solution to expose the silicon clean surface. Subsequently, the silicon surface may be nitrided or a silicon oxide film may be formed for the purpose of interface control for improving the mobility of the transistor, initial layer film formation control during CVD deposition, and gate capacitance adjustment. .

  Next, as shown in FIG. 2C, a gate oxide film 105 and a protective film 106 are formed. For this purpose, first, a metal film is formed on the silicon substrate 101 introduced into the deposition chamber using metal atoms (Hf), and then the metal film is oxidized. As a result, a gate oxide film 105 made of a metal oxide film (hafnium oxide film) is formed on the silicon substrate 101.

  Note that a PVD method, for example, a direct current sputtering method can be used for forming the metal film. In addition, the metal film may be formed using a vacuum deposition method, an electron beam deposition method, a laser deposition method, a CVD method, or the like.

  As the gate oxide film 105, a hafnium silicate film or a nitrided hafnium silicate film may be used in addition to the hafnium oxide film used here, or another kind of high dielectric constant film may be used. Further, a silicon oxide film (for example, formed by thermal oxidation) or a silicon oxynitride film (for example, formed by thermal oxynitridation) can be used, and any insulating film may be used.

  Further, a protective film 106 is formed on the gate oxide film 105. As described above, this is formed to prevent diffusion of the metal element into the gate oxide film 105. In this embodiment, since the gate oxide film 105 is a metal oxide film, it is particularly important. The protective film 106 may be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. For this purpose, sputtering, CVD, vacuum vapor deposition, electron beam vapor deposition, laser vapor deposition, or the like can be used. Note that the film thickness (physical film thickness) of the protective film 106 is desirably 1.0 nm or more. Further, the protective film 106 can be omitted when the gate oxide film 105 is formed of a material other than the metal oxide film.

  Next, as shown in FIG. 2D, a first silicon layer 107 is formed on the protective film 106 by deposition using, for example, a CVD method. This film thickness is, for example, about 30 nm.

  The first silicon layer 107 is preferably a polycrystalline silicon layer by setting the deposition temperature to 600 ° C. or higher. If the first silicon layer 107 is amorphous silicon, it changes from amorphous to polycrystalline by heat treatment, and grains are formed at this time. As a result, when the gate oxide film 105 is a metal oxide film as in the present embodiment, the grains penetrate the metal oxide film and induce defects. In order to prevent this, the first silicon layer 107 is desirably a polycrystalline silicon layer.

  Next, as shown in FIG. 3A, a barrier layer 108 made of, for example, a silicon oxide film is formed on the first silicon layer 107. The thickness of the barrier layer 108 is preferably 1.0 nm or more and 1.5 nm or less. With such a film thickness, the function of the barrier layer 108 described later is sufficiently exhibited, and electrical conduction through the barrier layer 108 by the tunnel effect is maintained.

  The material of the barrier layer 108 needs to be a material that does not silicidize first and can stop the silicidation reaction. At the same time, it must be a material that can have a sufficiently large selection ratio with respect to the silicon film when etching and can be used as an etch stop film.

  In order to form a silicon oxide film as an example of such a barrier layer 108, for example, the first silicon layer 107 is immersed in diluted hydrofluoric acid to form a natural oxide film on the surface, washed with water, and then added to a hydrogen peroxide solution. A silicon oxide film is formed by dipping. Instead of hydrogen peroxide water, ozone water can also be used. In addition to an oxide film called a chemical oxide film formed by such wet treatment, a thermal oxide film formed by heat treatment in an oxygen atmosphere after removing the natural oxide film may be used. Furthermore, a silicon oxynitride film may be used instead of the silicon oxide film.

  Next, as shown in FIG. 3B, a second silicon layer 109 is formed on the barrier layer 108. For example, a layer having a thickness of about 70 nm is formed by deposition using a CVD method.

  When the gate length of the transistor is 65 nm or less, the height of the gate electrode is generally about 100 nm. Therefore, the film thickness of the second silicon layer 109 is set to be about 100 nm in total with the film thickness of the first silicon layer 107. In the present embodiment, since the thickness of the first silicon layer 107 is about 30 nm, the thickness of the second silicon layer 109 is about 70 nm. However, this numerical value is only an example.

  Note that the second silicon layer 109 may be polycrystallized or amorphous.

Next, a donor impurity (for example, phosphorus, arsenic, or antimony) is ion-implanted into the nMOS region A, and an acceptor impurity (for example, boron or indium) is ion-implanted into the pMOS region B, respectively. FIG. 3C shows a state in which a donor impurity is implanted above the p-type well 103 using the resist 141. Since the barrier layer 108 made of a silicon oxide film is sufficiently thin, the dopant ion-implanted from above the second silicon layer 109 passes through the barrier layer 108, and not only the second silicon layer 109 but also the first silicon layer 107. Also distributed. The implantation dose is about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² in all cases.

  Next, a silicon oxide film for gate processing is formed on the second silicon layer 109. For this, for example, a TEOS oxide film is deposited to a thickness of about 100 nm by a low pressure CVD method. Next, a resist is applied, and the resist is processed into a gate shape by a lithography technique. Thereafter, the silicon oxide film for gate processing is processed into a gate shape by reactive etching using a gate-shaped resist as a mask. As a result, as shown in FIG. 3D, a hard mask 110 made of a silicon oxide film processed into a gate shape is formed on the second silicon layer 109.

  Next, as shown in FIG. 4A, using the hard mask 110 as a mask, the first silicon layer 107, the barrier layer 108, the second silicon layer 109, and the like are dry-etched and processed into the shape of the gate electrode. To do. At this time, the hard mask 110 which is a silicon oxide film is thinned by etching.

  Thereafter, by ion implantation, an n-type dopant is implanted into the nMOS region A (more specifically, the p-type well 103), and a p-type dopant is implanted into the pMOS region B (more specifically, the n-type well 104). To do. As a result, extension regions 111 are formed on both sides of each gate electrode.

  Next, as shown in FIG. 4B, sidewalls 112 that cover the side surfaces of the first silicon layer 107, the second silicon layer 109, and the like processed into the shape of the gate electrode are formed. For this purpose, for example, after a silicon nitride film covering the silicon substrate 101 is deposited, anisotropic etching is performed. Subsequently, an n-type dopant is implanted into the nMOS region A and a p-type dopant is implanted into the pMOS region B, and a spike annealing process is performed at 1050 ° C. for substantially 0 seconds in order to activate them. Thereby, the source / drain region 113 is formed. Instead of spike annealing, RTA (rapid thermal annealing) or laser annealing may be performed.

  Next, as shown in FIG. 4C, a silicide layer 114 is formed on the source / drain region 113. For this purpose, a Ni film is formed on the silicon substrate 101 by sputtering, and then heat treatment is performed at, for example, about 300 ° C. for 30 seconds. As a result, silicidation proceeds on the source / drain regions 113 where silicon is exposed, and a silicidation layer 114 is formed.

  Thereafter, unreacted Ni is removed by wet using a mixed solution of ammonia, hydrogen peroxide solution and water. Subsequently, the resistance of the silicidation layer 114 is stabilized by performing heat treatment again at, for example, 500 ° C. for 30 seconds.

  In this step, since the second silicon layer 109 is covered with the hard mask 110, silicidation is prevented. Moreover, metals other than Ni, for example, cobalt, titanium, platinum, etc. can also be used.

  Next, as shown in FIG. 4D, a first interlayer insulating film 115 is formed on the silicon substrate 101 so as to cover the sidewalls 112, the second silicon layer 109, and the like. For example, a silicon oxide film, more specifically, a TEOS oxide film, a plasma TEOS oxide film, a silicon oxide film formed by high-density plasma, or the like can be used.

  Next, as shown in FIG. 5A, the first interlayer insulating film 115 is uniformly polished using a known CMP (Chemical Mechanical Polishing) technique to expose the hard mask 110.

Next, as shown in FIG. 5B, the hard mask 110 which is a silicon oxide film is removed by dry etching using a fluorine-based gas such as CF ₄ or C ₄ F ₈ to remove the second silicon layer 109. To expose. At this time, the first interlayer insulating film 115, which is the same silicon oxide film, is also removed and the film thickness is reduced.

  Next, as shown in FIG. 5C, a resist 116 is formed and protected in the nMOS region A, and then the second silicon layer 109 is removed by performing etch back using HBr gas. At this time, since the selection ratio between the silicon oxide film (barrier layer 108) and the silicon layer (second silicon layer 109) etched by HBr gas is sufficiently high, the barrier layer 108 functions as an etch stop film, and the second Only the silicon layer 109 is etched. That is, the first silicon layer 107 is left without being etched.

  Thus, due to the presence of the barrier layer 108 sandwiched between the first silicon layer 107 and the second silicon layer 109, a silicon electrode (here, the first electrode) for performing silicidation later in the pMOS region B. The height of one silicon layer 107) can be made constant without variation. This can be realized without depending on the gate size and layout.

  Next, as shown in FIG. 5D, after removing the resist 116, the resist 116 is transferred to, for example, a sputtering chamber, and reverse sputtering using argon gas is performed. As a result, the natural oxide film formed on the surface of the second silicon layer 109 in the nMOS region A and the barrier layer 108 in the pMOS region B are removed, and a clean silicon surface is exposed.

  Subsequently, as shown in FIG. 6A, a Ni film 117 covering the first interlayer insulating film 115, the second silicon layer 109 in the nMOS region A, the first silicon layer 107 in the pMOS region B, and the like is formed. It is formed by sputtering. The film thickness of the Ni film 117 is, for example, about 100 nm.

  Next, for example, heat treatment in a nitrogen atmosphere is performed at 500 ° C. for 30 seconds to promote silicidation. FIG. 6B shows a state where the unreacted Ni film 117 is removed thereafter.

  In the nMOS region A, the second silicon layer 109 is silicided by the heat treatment, but the barrier layer 108 inhibits the silicidation reaction and stops here. That is, the first silicon layer 107 located under the barrier layer 108 is not silicided but remains silicon. As a result, a first gate electrode 131 having a metal silicide / silicon structure is formed in the nMOS region A. More specifically, the first metal silicide layer 118 is stacked on the first silicon layer 107 with the barrier layer 108 interposed therebetween.

  Therefore, since the first silicon layer 107 is located on the gate oxide film 105 in the nMOS region A, a threshold suitable for an n-type MOSFET can be obtained. By stopping silicidation using the barrier layer 108, such a structure is realized without depending on the gate size, layout, or the like. Since the composition of the portion of the first gate electrode 131 on the gate oxide film 105 can be made constant, the threshold voltage can be reduced and its variation can be suppressed.

  Since the barrier layer 108 is a silicon oxide film, it is an insulating film. However, since the film thickness is sufficiently thin, for example, about 1.5 nm, the electrical conduction between the first silicon layer 107 and the first metal silicide layer 118 is maintained by the tunnel current.

  On the other hand, in the pMOS region B, the first silicon layer 107 reacts with the Ni film 117 to become the second metal silicide layer 119.

  Here, as described with reference to FIG. 5C, the thickness of the first silicon layer 107 to be silicided is reliably controlled. This film thickness is thin, and the second metal silicide layer 119 is a metal silicide layer having a large metal composition and a reliably controlled composition. Since such a second metal silicide layer 119 becomes the second gate electrode 132 which is a full silicide electrode, it has a threshold suitable for the p-type MOSFET and the variation of the threshold is suppressed.

  In the p-type MOSFET, the first silicon layer 107 is silicided up to the portion in contact with the gate insulating film (the gate oxide film 105 and the protective film 106 formed thereon). Defects will not be introduced.

  Since the thickness of the second silicon layer 109 is about 70 nm, which is larger than that of the first silicon layer 107, the metal composition of the first metal silicide layer 118 is the second metal silicide. Low compared to layer 119. Further, even when the thickness of the second silicon layer 109 is smaller and the first metal silicide layer 118 has a metal-excess composition, the first silicon layer 107 under the barrier layer 108 has a gate insulating film ( Since it is in contact with the protective film 106) on the gate oxide film 105, the threshold value of the n-type MOSFET is not affected.

  Here, the silicidation reaction is performed by a single heat treatment. However, as shown in the method for forming the source / drain regions 113 (see FIG. 4B), the silicidation reaction is divided into two heat treatments. May be. In this case, the volume of the metal film, the first heat treatment, the removal of the unreacted metal film, and the second heat treatment are performed in this order.

  Finally, as shown in FIG. 6C, a second interlayer insulating film 120 is formed. This is formed by depositing a silicon oxide film by, for example, the CVD method. In addition, a TEOS oxide film, a plasma TEOS oxide film, a silicon oxide film formed by high density plasma, or the like may be used.

  Further, contact holes are opened in the source / drain regions 113, the first gate electrode 131, and the second gate electrode 132, respectively, using a lithography technique. Further, after forming a Ti / TiN barrier film in the contact hole, a contact plug 121 is formed by embedding W by a CVD method.

  As described above, the semiconductor device 100 in which the p-type MOSFET and the n-type MOSFET are formed is manufactured.

  According to the present invention, it is possible to realize a semiconductor device in which the threshold value is reduced and the variation is suppressed in both the p-type and n-type MOSFETs, and is particularly useful in a semiconductor device that has been miniaturized.

FIG. 1 is a schematic cross-sectional view illustrating the structure of a semiconductor device 100 according to an embodiment of the present invention. FIGS. 2A to 2D are diagrams for explaining a process for manufacturing the semiconductor device 100, and show the process up to the formation of the first silicon layer 107. FIGS. 3A to 3D are diagrams for explaining a process for manufacturing the semiconductor device 100, and show the process up to the formation of the hard mask 110. FIG. 4A to 4D are views for explaining a process for manufacturing the semiconductor device 100, and show the process up to the formation of the first interlayer insulating film 115. FIG. 5A to 5D are views for explaining a process for manufacturing the semiconductor device 100. In particular, FIG. 5B shows a process in which the second silicon layer 109 is selectively etched by the barrier layer 108 in the pMOS region B. 6A to 6D are diagrams for explaining a process of manufacturing the semiconductor device 100. FIG. In particular, FIG. 6B shows that the second silicon layer 109 is selectively silicided by the barrier layer 108 in the nMOS region A.

Explanation of symbols

101 silicon substrate 102 element isolation 103 p-type well 104 n-type well 105 gate oxide film 106 protective film 107 first silicon layer 108 barrier layer 109 second silicon layer 110 hard mask 111 extension region 112 sidewall 113 source / drain region 114 Silicided layer 115 First interlayer insulating film 116 Resist 117 Ni film 118 First metal silicide layer 119 Second metal silicide layer 120 Second interlayer insulating film 121 Contact plug 131 First gate electrode 132 Second Gate electrode 140 resist 141 resist

Claims (19)

A semiconductor substrate;
A first gate electrode formed on the n-type MOSFET region in the semiconductor substrate;
A second gate electrode formed on the p-type MOSFET region in the semiconductor substrate;
The first gate electrode includes a silicon layer and a first metal silicide layer formed thereon,
The semiconductor device according to claim 1, wherein the second gate electrode is made of a second metal silicide layer containing excess metal. In claim 1,
The semiconductor device according to claim 2, wherein the second metal silicide layer has a composition in which a metal is 60% or more. In claim 1 or 2,
The metal contained in the first metal silicide layer and the second metal silicide layer includes at least one of nickel, cobalt, titanium, and platinum. In any one of Claims 1-3,
A semiconductor device, wherein a gate insulating film which is a metal oxide film is provided between the semiconductor substrate and the first gate electrode and the second gate electrode. In claim 4,
The metal contained in the metal oxide film includes at least one of hafnium, zirconium, titanium, tantalum, lanthanum, and aluminum. In claim 4 or 5,
The semiconductor device, wherein the metal oxide film further contains silicon. In any one of Claims 4-6,
A semiconductor device, wherein a protective film is formed between the gate oxide film and the first gate electrode and the second gate electrode, respectively. In any one of Claims 1-7,
The semiconductor device according to claim 1, wherein the first gate electrode includes a barrier layer between the silicon layer and the first metal silicide layer. In claim 8,
The semiconductor device, wherein the barrier layer is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In claim 9,
2. The semiconductor device according to claim 1, wherein the silicon oxide film is a silicon oxide film formed by a wet process. In any one of Claims 8-10,
The thickness of the barrier layer is 1.0 nm or more and 1.5 nm or less. A step (a) of forming a gate insulating film on the semiconductor substrate;
Forming a first semiconductor layer on the gate insulating film (b);
Forming a barrier layer on the first semiconductor layer (c);
Forming a second semiconductor layer on the barrier layer (d);
(E) forming a first gate electrode and a second gate electrode by patterning the first semiconductor layer, the barrier layer, and the second semiconductor layer;
Removing the second semiconductor layer and the barrier layer in the second gate electrode;
Forming a metal film on the second semiconductor layer in the first gate electrode and the first semiconductor layer in the second gate electrode;
And (h) siliciding the second semiconductor layer in the first gate electrode and the first semiconductor layer in the second gate electrode by reaction with the metal film, respectively. A method for manufacturing a semiconductor device. In claim 12,
A step of forming a hard mask on the second semiconductor layer after the step (d) and before the step (e);
In the step (e), the first gate electrode and the second gate electrode are formed by etching using the hard mask. In claim 12 or 13,
After the step (e) and before the step (f), forming an interlayer insulating film on the semiconductor substrate so that the upper surfaces of the first gate electrode and the second gate electrode are exposed. A method for manufacturing a semiconductor device, further comprising: In any one of Claims 12-14,
A method for manufacturing a semiconductor device, further comprising the step of implanting ions into the first semiconductor layer and the second semiconductor layer. In any one of Claims 12-15,
A step of forming a sidewall on side surfaces of the first gate electrode and the second gate electrode after the step (e) and before the step (f) is further provided. Production method. In any one of Claims 12-16,
A method of manufacturing a semiconductor device, further comprising a step of forming a p-type well in a region of the semiconductor substrate where the first gate electrode is formed before the step (a). In any one of Claims 12-17,
A method of manufacturing a semiconductor device, further comprising a step of forming an n-type well in a region of the semiconductor substrate where the second gate electrode is formed before the step (a). In any one of Claims 12-18,
Before the step (a), an element isolation region is formed in the semiconductor substrate.

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