JP2007324187A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form an Ni silicide layer having excellent heat resistance on an n-type silicon layer. <P>SOLUTION: After an Al film 8 and an Ni film 9 are sequentially deposited on a gate electrode 4 and a source/drain diffusing layer 7, the heat treatment is conducted to form an Ni silicide layer 10 including Al at the upper part of the n-type silicon layer forming the gate electrode 4 and source/drain diffusing layer 7. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure of a silicide layer and a method for forming the same.

  In general, in a metal-oxide semiconductor (MOS) transistor, reducing parasitic resistance such as contact resistance and wiring resistance is an important factor for improving the operation speed. The parasitic resistance of these transistors is generally reduced by siliciding the upper portions of the source / drain regions and the gate electrode.

  In order to increase the degree of integration of a large-scale semiconductor integrated circuit device (LSI), it is necessary not only to reduce the horizontal dimension but also to reduce the vertical dimension. As one of the reductions in the vertical dimension, it is necessary to reduce the junction depth of the impurity diffusion layer in the source / drain region. However, when the thickness of the diffusion layer in the semiconductor substrate is reduced, there is a problem that the resistance of the diffusion layer increases and the operation speed of the semiconductor device decreases. For this, it is effective to form a metal silicide layer on the surface layer of the diffusion layer, thereby reducing the source / drain resistance. As a method of forming a metal silicide layer, a metal film is deposited on a silicon substrate and polysilicon to be a gate electrode, and heat treatment is applied to the metal film to cause silicon and metal to react with each other. A method of silicidizing the upper portions of the drain region and the gate electrode has been conventionally used. When the impurity diffusion layers in the source / drain regions are shallow junctions, it is necessary to use a material that can reduce the silicon consumption during the silicidation reaction as a material for forming the silicide layer.

  A silicide forming technique using nickel (Ni) that forms low-resistance monosilicide as a material capable of reducing silicon consumption has been developed.

However, NiSi ₂ , which is the disilicide phase of Ni silicide, has a lattice constant very close to that of silicon, and forms an inverted pyramid-like interface due to high-temperature heat treatment in the subsequent process and inappropriate process conditions. It is known to do. It is also known that the resistance of the silicide film is increased by aggregation. Therefore, there is a need for a method of improving the resistance (heat resistance) to the temperature of the high-temperature heat treatment in the subsequent process, thereby stably forming Ni silicide. As such a method, a method of alloying silicide has been proposed (see, for example, Patent Document 1). In this prior art, Ge, Ti, Re, Ta, N, V, Ir, Cr, and Zr are listed as elements that have the effect of stabilizing NiSi by adding to NiSi, which is a low-resistance monosilicide phase. (For example, refer nonpatent literature 1). There has also been a report suggesting that the same effect can be obtained for Hf, which is an element exhibiting physicochemical properties very similar to Zr (see, for example, Non-Patent Document 2). Furthermore, reports have been made to suggest that similar effects can be obtained for Mo, Ir, Co, Pt, and the like (see, for example, Non-Patent Documents 3 to 5).
US Pat. No. 6,689,688 (“Method And Device Using Silicide Contacts For Semiconductor Processing”, Paul Raymond Besser, 2004 / Feb / 10) Min-Joo Kim, Hyo-Jick Choi, Dae-Hong Ko, Ja-Hum Ku, Siyoung Choi, Kazuyuki Fujihara, and Cheol-Woong Yang, “High Thermal Stability of Ni Monosilicide from Ni-Ta Alloy Films on Si (100) ”, Electrochem. Solid-State Lett. 6, 2003, G122 Fei Nakata (Tokyo Institute of Technology), “Formation of Ni silicide doped with Hf”, The 65th Annual Conference of the Japan Society of Applied Physics-Proceedings of Lectures, September 1-4, 2004, p.708 2P-M-10) Young-Woo Ok, Chel-Jong Choi, and Tae-Yeon Seong, “Effect of a Mo Interlayer on the Electrical and Structural Properties of Nickel Silicides”, J. Electrochem. Soc. 150, 2003, G385 Jer-shen Maa, Yoshi Ono, Douglas J. Tweet, Fengyan Zhang, and Sheng Teng Hsu, “Effect of durable on thermal stability of nickel silicides”, J. Vac. Sci. Technol. A 19, 2001, p.1595 D. Mangelinck, JY Dai, JS Pan, and SK Lahiri, “Enhancement of thermal stability of NiSi films on (100) Si and (111) Si by Pt addition”, Appl. Phys. Lett. 75, 1999, p. 1736 E. Horach, JE Fischer, and J. Von. Der Spiegel, “Nb / Ni and Ni / Nb bilayers on Si: Rapid thermal processing, phase separation, and ternary phase formation”, J. Appl. Phys. 69, 1991 , p.7029 RN Wang and JY Feng, “Comparison of the thermal stabilities of NiSi films in Ni / Si, Ni / Pd / Si and Ni / Pt / Si Systems”, J. Phys.:Condens. Matter 15, 2003, p.1935

  The inventors of the present application have studied the effects of using elements described in the above-mentioned various documents for the purpose of improving the heat resistance of Ni silicide.

  First, regarding a method of forming a laminated film of an Ni metal film and another metal film shown in Non-Patent Documents 6 and 7 and alloying them, the other metal film is made of Hf, Zr, Pt, Ta and As a result of examining the effect when it is constituted by V or the like, an element showing a remarkable improvement in heat resistance could not be found. Further, as a method of laminating the metal film, a method of inserting another metal film into the interface between the Ni metal film and the silicon layer, a method of depositing another metal film on the surface of the Ni metal film, or a first Ni metal film Attempts were made to insert another metal film between the first Ni metal film and the second Ni metal film, but no heat resistance improvement effect was obtained in either case.

  Further, as a result of further experiments by the inventors of the present application, a Ni silicide layer formed using a Ni single layer film or a Ni film and another metal film such as Hf, Zr, Pt, Ta or V are deposited. In the other metal-containing silicide layer formed in this manner, the heat resistance of Ni silicide differs depending on the implanted impurity species (N-type impurity, P-type impurity) of the underlying substrate. If the implanted impurity of the underlying substrate is N-type, the impurity is P As compared with the case of the mold, the present inventors have found a new problem that the heat resistance is greatly deteriorated. Specifically, as described in detail below, in the experiment, there is a difference of about 100 ° C. or more in heat resistance between the case where the implanted impurity of the base substrate is N-type and the case where the impurity is P-type. confirmed.

  FIG. 6 shows a cross-sectional configuration of a MOS transistor as an example of a conventional semiconductor device. As shown in FIG. 6, the silicon substrate 101 is provided with an isolation insulating film 102 that electrically isolates the MOS transistors. On the transistor formation region surrounded by the isolation insulating film 102 in the silicon substrate 101, a gate electrode 104 made of a polysilicon film is formed via a gate insulating film 103. LDD (lightly doped drain) layers 105 are formed on both sides of the gate electrode 104 in the silicon substrate 101. Sidewall insulating films 106 are formed on both side surfaces of the gate electrode 104. A source / drain diffusion layer 107 is formed outside the sidewall insulating film 106 when viewed from the gate electrode 104 in the silicon substrate 101. A Ni silicide layer 111 is formed on each of the gate electrode 104 and the source / drain diffusion layer 107.

  In general, when an LSI (large scale integrated circuit) is formed, a complementary metal-oxide semiconductor (CMOS) structure is used, and therefore both an N-type MOS transistor and a P-type MOS transistor are formed as MOS transistors. FIG. 6 shows a cross-sectional structure of an N-type MOS transistor which is a part of the CMOS structure.

  The Ni silicide layer 111 of the MOS transistor shown in FIG. 6 is a Ni silicide layer obtained by performing low-temperature heat treatment after depositing a Ni single layer film. In general, Ni silicide formed by low-temperature heat treatment at about 500 ° C. is Ni monosilicide (NiSi).

By the way, the Ni silicide layer 111 shown in FIG. 6 formed by the low-temperature heat treatment as described above is also subjected to the heat treatment in the subsequent steps. At this time, if the heat treatment temperature in the post process is high, the Ni silicide layer 111 changes to a disilicide phase (NiSi ₂ ) or agglomerates and breaks. The sheet resistance value of the formed silicide layer becomes very large.

FIG. 7 is a diagram showing the heat resistance of the Ni silicide layer formed on the silicon layer in the conventional semiconductor device (specifically, the heat resistance temperature dependence of the sheet resistance). In FIG. 7, the gate is formed on an N ⁺ type source / drain diffusion layer (corresponding to the source / drain diffusion layer 107 in FIG. 6) in which an N type impurity is introduced into a silicon substrate or an N ⁺ type polysilicon. The heat treatment temperature dependence of the sheet resistance of the Ni silicide layer formed on the electrode (corresponding to the gate electrode 104 in FIG. 6) and the P ⁺ -type source / drain diffusion layer formed by introducing P-type impurities into the silicon substrate The graph shows a comparison of the heat resistance temperature dependence of the sheet resistance of the Ni silicide layer formed on the gate electrode made of P ⁺ type polysilicon. Here, each Ni silicide layer is formed using a Ni single layer film having a thickness of 12 nm.

  As shown in FIG. 7, in the conventional semiconductor device, the heat resistance of the Ni silicide layer formed on the N-type silicon layer is compared with the heat resistance of the Ni silicide layer formed on the P-type silicon layer. The temperature is lowered by about 100 ° C., and it is expected that a problem will occur in a high-temperature heat treatment exceeding 500 ° C. in a manufacturing process of a future memory / logic mixed type semiconductor device. In addition, the inventors of the present application, simultaneously with the above various studies, have formed a method of forming a laminated film of a Ni metal film and another metal film and alloying them with other metals Hf, Zr, Pt, Ta and As V and the like, it was applied to the formation of the Ni silicide layer on the N-type silicon layer, but an element capable of improving the heat resistance of the Ni silicide layer on the N-type silicon layer could not be found.

  In view of the above, the present invention is P-type when the heat resistance of Ni silicide differs depending on the implanted impurity species (N-type impurity, P-type impurity) such as the base substrate, and the implanted impurity such as the base substrate is N-type. The object is to solve the problem that the heat resistance is greatly deteriorated as compared with the case, that is, to form a Ni silicide layer having excellent heat resistance on the N-type silicon layer.

  In order to achieve the above object, a semiconductor device according to the present invention comprises a transistor having a gate electrode formed on a semiconductor substrate and source / drain regions formed on both sides of the gate electrode in the semiconductor substrate. In the semiconductor device, at least one of the gate electrode and the source / drain region is an N-type silicon-containing layer into which a group V element is introduced as an impurity, and an aluminum, A nickel silicide layer containing a group III element that is at least one of gallium or thallium is formed.

  In the semiconductor device of the present invention, when the group III element is aluminum, the aluminum in the nickel silicide layer may be distributed mainly on the surface portion of the nickel silicide layer, or in the nickel silicide layer Aluminum may also be distributed in the vicinity of the interface between the nickel silicide layer and the silicon-containing layer.

  In the semiconductor device of the present invention, the group III element in the nickel silicide layer may be distributed also in the grain boundary of the nickel silicide layer.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a gate electrode formed on a semiconductor substrate, and source / drain regions formed on both sides of the gate electrode in the semiconductor substrate. And at least one of the gate electrode and the source / drain region is an N-type silicon-containing layer into which a group V element is introduced as an impurity. Forming a first film containing a group III element that is at least one of aluminum, gallium, or thallium on the containing layer; and a second film containing nickel on the first film And heat-treating the first film and the second film, whereby the group III element is formed on the silicon-containing layer. And a step of forming a nickel silicide layer having. Here, the method for manufacturing a semiconductor device according to the present invention includes a step of forming an isolation insulating film for separating transistors, a step of forming a sidewall insulating film on the side surface of the gate electrode, and an N serving as a gate electrode or a source / drain region. A step of cleaning the surface of the silicon-containing layer, and a step of removing the unreacted first film (group III element-containing film) and second film (nickel-containing film) after the silicide layer is formed. It may be.

  In the method of manufacturing a semiconductor device according to the present invention, when the first film is an aluminum film and the second film is a nickel film, the ratio of the thickness of the aluminum film to the thickness of the nickel film is 2. It is preferably 5% or more and 25% or less.

  In the conventional semiconductor device, the heat resistance of the Ni silicide layer formed on the N-type silicon layer is about 100 ° C. lower than the heat resistance of the Ni silicide layer formed on the P-type silicon layer. However, according to the present invention, the heat resistance of the Ni silicide layer formed on the N-type silicon layer is approximately the same as the heat resistance of the Ni silicide layer formed on the P-type silicon layer. An excellent effect that it can be improved is obtained. Therefore, even when a high-temperature process is required in a subsequent process after forming the Ni silicide layer, it is possible to prevent the heat resistance of the semiconductor device from deteriorating.

(First embodiment)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a MOS transistor as an example of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the silicon substrate 1 is provided with an isolation insulating film 2 that electrically isolates the MOS transistors. On the transistor formation region surrounded by the isolation insulating film 2 in the silicon substrate 1, a gate electrode 4 made of, for example, a polysilicon film is formed via a gate insulating film 3. LDD layers 5 are formed on both sides of the gate electrode 4 in the silicon substrate 1. Sidewall insulating films 6 are formed on both side surfaces of the gate electrode 4. A source / drain diffusion layer 7 is formed outside the sidewall insulating film 6 when viewed from the gate electrode 4 in the silicon substrate 1. A Ni silicide layer 10 is formed on each of the gate electrode 4 and the source / drain diffusion layer 7.

  The feature of this embodiment is that aluminum which is a group III element is added to the Ni silicide layer 10.

In general, when an LSI is formed, since a CMOS structure is used, both an N-type MOS transistor and a P-type MOS transistor are formed as MOS transistors. Also in this embodiment, FIG. 1 shows a cross-sectional structure of an N-type MOS transistor which is a part of the CMOS structure. That is, the gate electrode 4 is made of a high-concentration N-type (N ⁺ -type) polysilicon film into which a group V element such as phosphorus (P) or arsenic (As) is introduced as an impurity. It consists of a high-concentration N-type (N ⁺ -type) silicon layer formed by introducing a group V element such as P or As as an impurity into the silicon substrate 1.

  2 shows the Al-containing Ni silicide layer 10, the source / drain diffusion layer 7, and the silicon substrate 1 in the semiconductor device shown in FIG. 1 in an arrow direction (a direction from A to A ′) in FIG. Electron spectroscopy) shows the profile of each element obtained by analysis. Note that the horizontal axis of FIG. 2 represents the elapsed time of sputtering for surface peeling, and the vertical axis represents the energy intensity of Auger electrons. Here, the Al-containing Ni silicide layer 10 is obtained by sequentially depositing an Al film having a thickness of 1.2 nm and an Ni film having a thickness of 11 nm and performing heat treatment. The results shown in FIG. 2 were obtained by performing a heat treatment at 650 ° C. in a later step after the formation of the Al-containing Ni silicide layer 10.

  As shown in FIG. 2, after the heat treatment at 650 ° C., which is a subsequent process, is performed, the aluminum contained in the Ni silicide layer 10 is distributed mainly on the outermost surface portion of the Ni silicide layer 10.

  That is, in the Ni silicide layer 10 of the present embodiment, an Al film having a thickness of 1.2 nm is first deposited on the source / drain diffusion layer 7, an Ni film having a thickness of 11 nm is deposited, and then heat treatment is performed. In spite of being silicidized by this, Al is redistributed (contained) in the outermost surface portion.

FIG. 3 shows the heat treatment temperature dependence of the sheet resistance in the Al-containing Ni silicide layer of the present embodiment, with the N ⁺ type silicon layer (N ⁺ substrate in the figure) and the p ⁺ type silicon layer (P ⁺ substrate in the figure). 2) are shown in comparison with pure Ni silicide layers that do not contain Al. Here, a pure Ni silicide layer is silicided by depositing a 12 nm thick Ni film on a silicon substrate and then performing a heat treatment.

As shown in FIG. 3, the sheet resistance (■ in the figure) of the Ni silicide layer on the p ⁺ substrate in the first conventional example increases after exceeding 700 ° C., whereas in the second conventional example, The sheet resistance (▲ in the figure) of the Ni silicide layer on a certain N ⁺ substrate increases from about 625 ° C., which is about 100 ° C. lower than that. That is, the heat resistance of the Ni silicide layer on the N ⁺ substrate according to the second conventional example is worse than the heat resistance of the Ni silicide layer on the p ⁺ substrate according to the first conventional example. On the other hand, the sheet resistance (● in the figure) of the Al-containing Ni silicide layer (Al-containing Ni silicide layer on the N ⁺ substrate) of this embodiment is the Ni silicide layer on the p ⁺ substrate according to the first conventional example. The resistance of the Al-containing Ni silicide layer of this embodiment is improved to the same level as that of the Ni silicide layer on the p ⁺ substrate. I understand that.

  By inserting the Al film between the Ni film and the silicon layer, the inventors of the present application prevent the diffusion of Ni into the silicon due to the heat treatment, thereby causing phase change to Ni silicide and aggregation of Ni silicide. The delay is presumed to be the reason why the heat resistance of the Al-containing Ni silicide layer of this embodiment is improved. In addition, when the present inventors applied a heat treatment in the range of 600 ° C. to 725 ° C. to the Al-containing Ni silicide layer of the present embodiment, as described above, Al finally becomes the Ni silicide layer. It has been confirmed that it is distributed on the outermost surface part of.

  As described above, according to this embodiment, the Ni silicide layer on the N-type silicon layer contains Al, which is a group III element, so that the heat resistance of the Ni silicide layer on the N-type silicon layer (specifically, Specifically, the heat resistance of the post-silicide formation process (on the process) (hereinafter the same), that is, the heat resistance of the N-type MOS transistor, the heat resistance of the Ni silicide layer on the P-type silicon layer, that is, the P-type MOS transistor The excellent effect that it can be improved to the same level as the heat resistance of the is obtained. Therefore, even when a high-temperature process is required in a subsequent process after forming the Ni silicide layer, it is possible to prevent deterioration of heat resistance of a semiconductor device such as an LSI using a CMOS structure.

  In this embodiment, the Ni silicide layer on the N-type silicon layer contains aluminum as a group III element. Instead, other group III elements other than boron (B) and In (indium) are used. For example, gallium (Ga) or thallium (Tl) may be contained. Of course, two or more group III elements other than B and In may be contained. In addition, as long as at least one group III element excluding B and In is contained, at least one of B and In may be contained together with the element.

  Further, when the CMOS structure is adopted in the present embodiment, the Ni silicide layer (Ni silicide layer on the P-type silicon layer) included in the P-type MOS transistor may contain a group III element such as Al. Or may not be included.

  Further, in the present embodiment, it has been described that Al is distributed on the outermost surface portion of the Ni silicide layer after the heat treatment in the range from 600 ° C. to 725 ° C. However, after the heat treatment in the other temperature range, In some cases, Al is also distributed in the vicinity of the interface between the Ni silicide layer and the silicon layer. Further, when viewed microscopically, when a group III element such as Al is contained in the Ni silicide layer, the element is also distributed in the grain boundary (crystal grain boundary) of the Ni silicide layer. The inventors of the present application speculate that the aggregation of the Ni silicide layer is thereby suppressed, and as a result, the heat treatment temperature dependency of the sheet resistance is improved.

  In this embodiment, the Ni silicide layer is formed on the silicon layer to be the source / drain regions and the gate electrode. However, if Ni silicide can be formed, instead of the silicon layer, for example, a silicon germanium layer or the like is used. A silicon-containing layer may be used as a base for the Ni silicide layer. Further, a Ni silicide layer may be formed only on one of the source / drain regions and the gate electrode.

(Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention, specifically, a method for forming a MOS transistor as an example of the semiconductor device according to the first embodiment will be described with reference to the drawings. .

  FIG. 4A to FIG. 4H are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the second embodiment. 4A to 4H show cross-sectional structures of the N-type MOS transistor in the CMOS structure having both the N-type MOS transistor and the P-type MOS transistor, respectively.

  First, as shown in FIG. 4A, an isolation insulating film 2 that electrically isolates MOS transistors is formed on a silicon substrate 1. Next, as shown in FIG. 4B, a gate insulating film 3 and, for example, a polysilicon film are sequentially deposited on the transistor formation region surrounded by the isolation insulating film 2 in the silicon substrate 1, and then the polysilicon is formed. The film is patterned to form the gate electrode 4.

  Next, as shown in FIG. 4C, LDD layers 5 are formed on both sides of the gate electrode 4 in the silicon substrate 1 by performing ion implantation using the gate electrode 4 as a mask. Here, instead of the LDD layer 5, an extension diffusion layer may be formed. Subsequently, an insulating film is deposited on the silicon substrate 1 including the gate electrode 4, and then the insulating film is dry-etched to form sidewall insulating films 6 on both side surfaces of the gate electrode 4. .

Next, as shown in FIG. 4D, ion implantation is performed using the gate electrode 4 and the side wall insulating film 6 as a mask, so that the gate electrode 4 on the silicon substrate 1 is outside the side wall insulating film 6 as viewed from the gate electrode 4. A source / drain diffusion layer 7 is formed. Here, the element implanted to form the source / drain diffusion layer 7 is, for example, As. Regarding the implantation conditions, the energy is, for example, 30 keV, and the dose is, for example, 4 × 10 ¹⁵ cm ⁻² . This is 5 × 10 ²⁰ cm ⁻³ in terms of concentration, and generally a concentration of 1 × 10 ²⁰ cm ⁻³ or higher is set as a high concentration. That is, the source / drain diffusion layer 7 is a high concentration N type (N ⁺ type) diffusion layer. Also, the polysilicon film constituting the gate electrode 4 becomes N ⁺ type by the ion implantation.

  Next, the silicon exposed surfaces of the gate electrode 4 and the source / drain diffusion layer 7 are cleaned using, for example, diluted hydrofluoric acid, and then the gate electrode 4 as shown in FIG. An Al film 8 having a thickness of about 1.2 nm is deposited on the silicon substrate 1 including the top 4 using a sputtering apparatus, for example. Subsequently, as shown in FIG. 4F, a Ni film 9 having a thickness of about 11 nm is deposited on the Al film 8.

  Next, the Al film 8 and the Ni film 9 are annealed in a temperature range from about 300 ° C. to about 500 ° C. using, for example, an RTP (rapid thermal processing) apparatus. As a result, a silicidation reaction occurs at a location where the Ni film 9 is in contact with the silicon layer (that is, the gate electrode 4 and the source / drain diffusion layer 7) with the Al film 8 interposed therebetween, as shown in FIG. Then, an Al-containing Ni silicide layer 10 is formed. At this time, the unreacted Al film 8 and Ni film 9 that are not silicided remain in the metal state on the isolation insulating film 2 and the sidewall insulating film 6. Therefore, thereafter, the unreacted metal on the isolation insulating film 2 and the sidewall insulating film 6 is removed by using, for example, selective wet etching.

  By the way, in the present embodiment, the formation of the MOS transistor is temporarily completed by the steps shown in FIGS. 4A to 4H, and only low-temperature heat treatment of, for example, about 400 ° C. or less is performed as the heat treatment in the subsequent steps. In some cases, an LSI can be completed using However, depending on the manufacturing process, it may be necessary to complete the LSI using a high-temperature heat treatment in the subsequent process, and it is desired to improve the heat resistance of the Ni silicide layer 10 in the subsequent process.

  2 shows the Al-containing Ni silicide layer 10, the source / drain diffusion layer 7 and the silicon substrate 1 in the semiconductor device shown in FIG. 1 formed by the manufacturing method shown in FIGS. 4 (a) to 4 (h). FIG. 1 shows the profile of each element obtained by Auger analysis in the direction of the arrow in FIG. 1 (direction from A to A ′). Note that the horizontal axis of FIG. 2 represents the elapsed time of sputtering for surface peeling, and the vertical axis represents the energy intensity of Auger electrons. The results shown in FIG. 2 were obtained by performing a heat treatment at 650 ° C. in a later step after the formation of the Al-containing Ni silicide layer 10.

  As shown in FIG. 2, after the heat treatment at 650 ° C. is performed in the subsequent process, the aluminum contained in the Ni silicide layer 10 is distributed mainly on the outermost surface portion of the Ni silicide layer 10.

FIG. 5 shows the heat treatment temperature dependency (heat resistance) of the sheet resistance in the Al-containing Ni silicide layer of the present embodiment, which is represented by an N ⁺ type silicon layer (N ⁺ substrate in the figure) and a p ⁺ type silicon layer (in the figure). FIG. 2 is a diagram showing comparison with a pure Ni silicide layer not containing Al formed on each of the P ⁺ substrates. In FIG. 5, as the Al-containing Ni silicide layer of the present embodiment, Al films having thicknesses of 0.3 nm, 0.6 nm, 1.2 nm, and 2.4 nm are respectively provided between the N ⁺ substrate and the Ni film. The heat resistance of the Al-containing Ni silicide layer obtained by the deposition is shown (the thickness of the Al film is set to 1.2 nm in the step shown in FIG. 4E). Here, the thickness of the Ni film is adjusted so that the total thickness of the Ni film and the Al film is about 12 nm. However, when the thickness of the Al film was as thin as 0.3 nm or 0.6 nm, the thickness of the Ni film was set to 12 nm.

As shown in FIG. 5, the sheet resistance (■ in the figure) of the Ni silicide layer on the p ⁺ substrate in the first conventional example rises after exceeding 700 ° C., whereas in the second conventional example, The sheet resistance (▲ in the figure) of the Ni silicide layer on a certain N ⁺ substrate increases from about 625 ° C., which is about 100 ° C. lower than that. That is, the heat resistance of the Ni silicide layer on the N ⁺ substrate according to the second conventional example is worse than the heat resistance of the Ni silicide layer on the p ⁺ substrate according to the first conventional example.

On the other hand, as shown in FIG. 5, the sheet resistance (● in the figure) of the Al-containing Ni silicide layer (Al ⁺ Ni silicide layer on the N ⁺ substrate) of this embodiment is the second conventional example N ⁺ The sheet resistance of the Ni silicide layer on the substrate is suppressed to be lower than (▲ in the figure). That is, the heat resistance of the Al-containing Ni silicide layer of this embodiment is very close to the heat resistance of the Ni silicide layer on the p ⁺ substrate.

Further, as can be seen from the results shown in FIG. 5, the heat resistance of the Al-containing Ni silicide layer of this embodiment is improved as the thickness of the Al film inserted between the N ⁺ substrate and the Ni film is increased. , Closer to the heat resistance of the Ni silicide layer on the p ⁺ substrate. However, when the thickness of the Al film is 2.4 nm, the sheet resistance at around 600 ° C. is about 12 Ω / □, and the sheet resistance is about 7 Ω / □ for other Al film thicknesses. It is higher than That is, if the thickness of the Al film is larger than about 2.5 nm, a normal Ni silicide layer may not be formed.

  From the above, in order to reliably obtain the heat resistance improvement effect by the Al-containing Ni silicide layer of the present embodiment, the ratio of the Al film thickness to the Ni film thickness is about 2.5% (for example, Ni film) = 12 nm, Al film = 0.3 nm) or more and preferably about 25% (for example, Ni film = 10 nm, Al film = 2.5 nm) or less.

  As described above, according to this embodiment, the Ni silicide layer on the N-type silicon layer contains Al, which is a group III element, so that the heat resistance of the Ni silicide layer on the N-type silicon layer (specifically, Specifically, the heat resistance of the post-silicide formation process (on the process) (hereinafter the same), that is, the heat resistance of the N-type MOS transistor, the heat resistance of the Ni silicide layer on the P-type silicon layer, that is, the P-type MOS transistor The excellent effect that it can be improved to the same level as the heat resistance of the is obtained. Therefore, even when a high-temperature process is required in a subsequent process after forming the Ni silicide layer, it is possible to prevent deterioration of heat resistance of a semiconductor device such as an LSI using a CMOS structure.

  In this embodiment, the Ni silicide layer on the N-type silicon layer contains aluminum as a group III element. Instead, other group III elements other than boron (B) and In (indium) are used. For example, gallium (Ga) or thallium (Tl) may be contained. Of course, two or more group III elements other than B and In may be contained. In addition, as long as at least one group III element excluding B and In is contained, at least one of B and In may be contained together with the element.

  That is, in the present embodiment, an Al film is inserted between the silicon layer serving as the source / drain regions and the gate electrode and the Ni film for forming the silicide, but instead of this, for example, Al and Ga or Tl A group III element-containing film such as an alloy film may be inserted. Moreover, instead of the silicon layer, a silicon-containing layer such as a silicon germanium layer may be used as the base of the silicide layer. Further, instead of the Ni film, for example, an alloy film of Hf, Zr, Pt, Ta, V, or the like and Ni may be used as the metal film for forming the silicide.

  In this embodiment, the Ni silicide layer is formed on the silicon layer to be the source / drain region and the gate electrode. Instead, the Ni silicide layer is formed only on either the source / drain region or the gate electrode. A layer may be formed.

  Further, when the CMOS structure is adopted in the present embodiment, the Ni silicide layer (Ni silicide layer on the P-type silicon layer) included in the P-type MOS transistor may contain a group III element such as Al. Or may not be included. That is, in the P-type MOS transistor formation region, a group III element-containing film such as an Al film may be formed between the silicon layer that becomes the source / drain region or the gate electrode and the Ni film for forming the silicide. Or need not be formed.

  The present invention is very useful as a semiconductor device having a silicide layer and a manufacturing method thereof.

FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a diagram showing a result of Auger analysis of the Ni silicide layer, the source / drain diffusion layer, and the silicon substrate in the AA ′ direction in the semiconductor device shown in FIG. 1. FIG. 3 is a diagram showing an effect of improving heat resistance by the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing each step of the semiconductor device manufacturing method according to the second embodiment of the present invention. FIG. 5 is a diagram showing an effect of improving heat resistance by the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view of a conventional semiconductor device. FIG. 7 is a diagram showing the heat resistance of a conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Isolation insulating film 3 Gate insulating film 4 Gate electrode 5 LDD layer 6 Side wall insulating film 7 Source / drain diffused layer 8 Al film 9 Ni film 10 Al content Ni silicide layer

Claims (8)

A semiconductor device comprising a transistor having a gate electrode formed on a semiconductor substrate and source / drain regions formed on both sides of the gate electrode in the semiconductor substrate,
At least one of the gate electrode and the source / drain region is an N-type silicon-containing layer into which a group V element is introduced as an impurity,
A nickel silicide layer containing a group III element which is at least one of aluminum, gallium or thallium is formed on the silicon-containing layer. The semiconductor device according to claim 1,
A semiconductor device characterized in that the group III element is aluminum. The semiconductor device according to claim 1 or 2,
Aluminum in the nickel silicide layer is distributed mainly on a surface portion of the nickel silicide layer. The semiconductor device according to claim 1 or 2,
The aluminum in the nickel silicide layer is also distributed in the vicinity of the interface between the nickel silicide layer and the silicon-containing layer. The semiconductor device according to claim 1,
A group III element in the nickel silicide layer is also distributed in the grain boundary of the nickel silicide layer. A method of manufacturing a semiconductor device comprising a transistor having a gate electrode formed on a semiconductor substrate and source / drain regions formed on both sides of the gate electrode in the semiconductor substrate,
At least one of the gate electrode and the source / drain region is an N-type silicon-containing layer into which a group V element is introduced as an impurity,
Forming a first film containing a group III element that is at least one of aluminum, gallium, or thallium on the silicon-containing layer;
Forming a second film containing nickel on the first film;
Performing a heat treatment on the first film and the second film, thereby forming a nickel silicide layer containing the group III element on the silicon-containing layer. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 6,
The first film is an aluminum film;
The method of manufacturing a semiconductor device, wherein the second film is a nickel film. In the manufacturing method of the semiconductor device according to claim 7,
A method of manufacturing a semiconductor device, wherein a ratio of a thickness of the aluminum film to a thickness of the nickel film is 2.5% or more and 25% or less.

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