JP2007317918A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can change the resistance of a specific resistive element without modifying a design pattern and also without affecting the resistive value of an another resistive element, and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device comprises a resistive element 12 formed on an insulating film 10. The resistive element 12 has first and second regions 12a and 12b arranged in a semiconductor pattern in series or in parallel. The first region 12a has a first concentration of an impurity introduced therein, and the second region 12b has a second concentration of an impurity introduced therein and of the same conduction type as the first region 12a. With this semiconductor device, the resistance of the resistive element 12 can be changed by changing a surface ratio between the first and second regions 12a and 12b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a semiconductor device manufacturing method and a semiconductor device. In particular, the present invention relates to a method of manufacturing a semiconductor device and a semiconductor device that can change the resistance of a specific resistance element without changing the design pattern and without affecting the resistance value of another resistance element.

Resistive elements are incorporated in various forms in circuits inside the semiconductor device. This resistance element is formed, for example, by introducing impurities into a silicon substrate or a polysilicon pattern. The resistance value of such a resistance element is determined by the pattern shape of the resistance element and the amount of impurities introduced. Among these, the amount of impurities is determined for each layer in which the resistance element is formed. For this reason, when a plurality of resistance elements are formed in the same layer, the resistance values of the resistance elements are set to different values by making the pattern shapes of the resistance elements different from each other (see, for example, Patent Document 1). .
Japanese Patent Laid-Open No. 3-201555

When a semiconductor device is manufactured according to a design, the resistance value of a specific resistance element may show a value different from the design value. In this case, it is necessary to change the resistance value of a specific resistance element so as not to affect the resistance values of other resistance elements. As described above, the resistance value of the resistance element is determined by the pattern shape of the resistance element and the amount of impurities. If the amount of impurities is changed, the resistance values of other resistance elements located in the same layer are also changed. For this reason, conventionally, it has been necessary to change the pattern shape of the resistance element. However, in general, the design pattern of a semiconductor device is designed so as to use space efficiently, that is, with no gaps. In order to change the pattern shape of a resistive element, it is necessary to change the entire design pattern. There were many.

In addition, there is a technique for adjusting the resistance value of the resistance element by forming a plurality of fuses in parallel in an electric circuit and cutting a part of these fuses. The required area is increased, the chip size is increased, and a process for cutting the fuse is required. For this reason, it is practically difficult to use a fuse to solve the above problem.

The present invention has been made in view of the above circumstances, and its purpose is to change the resistance of a specific resistance element without changing the design pattern and without affecting the resistance values of other resistance elements. A semiconductor device manufacturing method and a semiconductor device are provided.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor pattern on an insulating film,
Performing a first impurity introduction into the semiconductor pattern;
Covering a part of the semiconductor pattern with a mask film, and introducing a second impurity into a region of the semiconductor pattern exposed from the mask film;
Measuring a resistance value of the semiconductor pattern;
Changing the area of the region covered with the mask film in the semiconductor pattern based on the measurement result of the resistance value.

According to this method for manufacturing a semiconductor device, the resistance value of the semiconductor pattern can be changed by changing the area of the region covered with the mask film in the semiconductor pattern. At this time, if the region covered with the mask film in the other semiconductor pattern is not changed, the resistance value of the other semiconductor pattern is not changed. Therefore, the resistance value of a specific semiconductor pattern can be changed without changing the design pattern and without affecting the resistance value of another semiconductor pattern.

Another method for manufacturing a semiconductor device according to the present invention includes a step of separating a resistance region of the semiconductor substrate from another region by forming an element isolation film on the semiconductor substrate.
Performing a first impurity introduction into the resistance region;
Covering a part of the resistance region with a mask film, and introducing a second impurity into a region of the resistance region exposed from the mask film;
Measuring a resistance value of the resistance region;
And a step of changing an area of the resistance region covered with the mask film based on the measurement result of the resistance value.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming first and second semiconductor patterns on an insulating film,
Performing a first impurity introduction into the first and second semiconductor patterns;
A portion of the first semiconductor pattern and a portion of the second semiconductor pattern are each covered with a mask film, and a second of the first and second semiconductor patterns is exposed to the region exposed from the mask film. A step of introducing impurities,
Measuring a resistance value of the first semiconductor pattern;
Changing the area of the region covered with the mask film in the first semiconductor pattern based on the measurement result of the resistance value.

According to this semiconductor device, the resistance value of the first semiconductor pattern can be changed by changing the area of the region covered with the mask film in the first semiconductor pattern. At this time, if the region covered with the mask film in the second semiconductor pattern is not changed, the resistance value of the second semiconductor pattern is not changed. Therefore, the resistance value of the first semiconductor pattern can be changed without changing the design pattern and without affecting the resistance value of the second semiconductor pattern.

Another method of manufacturing a semiconductor device according to the present invention includes a step of separating each of the first and second resistance regions of the semiconductor substrate from other regions by forming an element isolation film on the semiconductor substrate.
Performing a first impurity introduction into the first and second resistance regions;
A part of the first resistance region and a part of the second resistance region are covered with a mask film, and a second of the first resistance region and the second resistance region exposed to the mask film is a second region. A step of introducing impurities;
Measuring a resistance value of the first resistance region;
Changing the area of the region covered with the mask film in the first resistance region based on the measurement result of the resistance value.

In the step of introducing the second impurity, an impurity having the same conductivity type as that of the first impurity introduction may be introduced, or an impurity having a conductivity type different from that of the first impurity introduction may be introduced. .

A semiconductor device according to the present invention is a semiconductor device comprising a resistance element formed on an insulating film,
The resistance element includes a first region in which impurities are introduced at a first concentration in a semiconductor pattern;
A second region in which impurities having the same conductivity type as the first region are introduced at a second concentration different from the first concentration is arranged in series or in parallel.

Another semiconductor device according to the present invention is a semiconductor device including a resistance element formed by introducing an impurity into a semiconductor substrate,
The resistor element has a first region in which impurities are introduced at a first concentration and an impurity having the same conductivity type as that of the first region is introduced into the semiconductor substrate at a second concentration different from the first concentration. The second region is arranged in series or in parallel.

  The resistance element is a part of an oscillation circuit, for example.

Another semiconductor device according to the present invention includes first and second resistance elements formed on an insulating film and having substantially the same planar shape.
Each of the first and second resistance elements includes a first region in which impurities are introduced at a first concentration in a semiconductor pattern, and an impurity having the same conductivity type as the first region. A second region introduced at a different second concentration, and arranged in series or in parallel;
The area ratio of the second region to the first region is different between the first and second resistance elements.

Another semiconductor device according to the present invention is formed by introducing impurities into a semiconductor substrate,
Comprising first and second resistance elements having substantially the same planar shape;
Each of the first and second resistance elements includes a first region in which impurities are introduced at a first concentration, and a second concentration in which impurities having the same conductivity type as the first region are different from the first concentration. The second region introduced in (1) is arranged in series or in parallel in the semiconductor substrate,
The area ratio of the second region to the first region is different between the first and second resistance elements.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each figure of FIG. 1 is the first of the present invention.
It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on this embodiment. The semiconductor device manufactured according to this embodiment has a polysilicon resistor. This polysilicon resistor constitutes, for example, an oscillation circuit. In this case, since the oscillation frequency varies depending on the resistance value of the polysilicon resistor, it is necessary to strictly manage the resistance value.

First, as shown in FIG. 1A, a semiconductor element (for example, a transistor: not shown) is formed on a silicon substrate (not shown), and an interlayer insulating film 10 is formed on the transistor by a CVD method. Next, a polysilicon film is formed on the interlayer insulating film 10 by the CVD method. Then
A resist pattern is formed on the polysilicon film, and the polysilicon film is etched using the resist pattern as a mask. Thereby, a resistance element 12 made of a polysilicon pattern is formed in the interlayer insulating film 10. Thereafter, the resist pattern is removed.
Next, impurities are introduced into the entire surface of the resistance element 12 (both the regions 12a and 12b).

Next, as shown in FIG. 1B, a photoresist film is applied over the entire surface including the resistance element 12, and this photoresist film is exposed using a reticle and then developed. This
A resist pattern 50 is formed on the resistance element 12. The resist pattern 50 covers the region 12 a of the resistance element 12. Next, impurities are introduced again into the resistance element 12 using the resist pattern 50 as a mask. As a result, impurities are again introduced into the region 12b of the resistance element 12.

Thereafter, as shown in FIG. 1C, the resist pattern 50 is removed. Then, an interlayer insulating film 17 is formed on the entire surface including the resistance element 12. Next, a resist pattern (not shown) is formed on the interlayer insulating film 17, and the interlayer insulating film 17 is etched using this resist pattern as a mask. As a result, two connection holes located on the resistance element 12 are formed in the interlayer insulating film 17.
Formed. Thereafter, the resist pattern is removed.

Next, an Al alloy film is formed by sputtering in the two connection holes and on the interlayer insulating film 17. Next, a resist pattern (not shown) is formed on the Al alloy film, and the Al alloy film is etched using the resist pattern as a mask. As a result, Al alloy wirings 18 a and 18 b connected to the resistance element 12 through the connection holes are formed on the interlayer insulating film 17.

In the example shown in this figure, the regions 12a and 12b of the resistance element 12 are electrically arranged in series. The region 12a is connected to the Al alloy wiring 18a, and the region 12b is connected to the Al alloy wiring 18b.
Connected to.

The resistance element 12 formed in this way has different impurity concentrations and different sheet resistance values in the regions 12a and 12b. Specifically, when impurities of the same conductivity type are introduced in the impurity introduction step shown in FIG. 1A and the impurity introduction step shown in FIG. 1B, the sheet resistance value of the region 12a is the region 12b. Higher than the sheet resistance value. In the impurity introduction step shown in FIG. 1B, when an impurity having a conductivity type opposite to that of the impurity introduction step shown in FIG. 1A is introduced, the sheet resistance value of the region 12a is the sheet resistance value of the region 12b. Lower than the value. Note that in the case of introducing a reverse conductivity type impurity, the amount of impurities introduced in the step shown in FIG. 1B needs to be smaller than the amount of impurities introduced in the step shown in FIG. .

When the region 12a and the region 12b are electrically arranged in series, the resistance value of the resistance element 12 is the sum of the resistance values of the region 12a and the region 12b, and the region 12a and the region 12b are electrically arranged in parallel. In this case, it is the reciprocal of the sum of the reciprocal of the resistance value of the region 12a and the reciprocal of the resistance value of the region 12b.

Thereafter, the resistance value of the resistance element 12 is measured to check whether it is within the allowable range. When it is outside the allowable range, the area covered by the resist pattern 50 in the resistance element 12 is changed to change the area ratio of the area 12a and the area 12b. Thus, the resistance value of the resistance element 12 can be changed without changing the impurity introduction amount in the impurity introduction step shown in FIGS. 1 (A) and 1 (B).

Therefore, the resistance value of the resistance element 12 can be changed without changing the design pattern of the semiconductor device and without affecting the resistance values of other resistance elements.

Let me give you an example. For example, the resistance element 1 when the region 12a occupies the entire surface of the resistance element 12
When the resistance value of 2 is 10 kΩ, the resistance value of the resistance element 12 is 1 kΩ when the region 12 b occupies the entire surface of the resistance element 12, and the regions 12 a and 12 b are electrically arranged in series, the resistance element The resistance value of 12 can be adjusted in the range of 1 to 10 kΩ. For example, when the region 12a occupies 1/2 of the resistance element 12, the resistance value of the resistance element 12 is 5.5 kΩ, and the region 12a
Occupies 3/4 of the resistance element 12, the resistance value of the resistance element 12 is 7.75 kΩ.

As described above, according to the present embodiment, the area ratio of the region 12a having the first impurity concentration and the region 12b having the second impurity concentration is changed by changing the region covered with the resist pattern 50 in the resistance element 12. And the resistance value of the resistance element 12 can be changed.

Therefore, when the resistance value of the resistance element 12 falls outside the allowable range, the resistance when the resist pattern 50 is formed is changed, and only the area covered by the resist pattern 50 in the resistance element 12 is changed. The resistance value of the element 12 can be adjusted. In addition, the resistance value of the resistance element 12 can be changed without affecting the resistance values of other resistance elements.

When the resistance element 12 constitutes an oscillation circuit, the oscillation frequency of the oscillation circuit can be changed by changing the region covered with the resist pattern 50 in the resistance element 12. That is, by preparing a plurality of types of reticles for forming the resist pattern 50, a semiconductor device having oscillation circuits having different oscillation frequencies can be manufactured based on one design pattern.

Each drawing in FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment. The semiconductor device manufactured according to the present embodiment has a diffusion resistor formed on the silicon substrate 1.

First, as shown in FIG. 2A, a groove is formed in the silicon substrate 1, and an element isolation film 2 is formed in the groove.
Embed. As a result, the element region (not shown) where the transistor is formed and the resistance region 20 where the diffusion resistance is formed are separated from the other regions.
Next, impurities are introduced into the entire surface of the resistance region 20 (both the regions 20a and 20b).

Next, as shown in FIG. 2B, a photoresist film is applied over the entire surface including the resistance region 20, and this photoresist film is exposed using a reticle and then developed. This
A resist pattern 51 is formed on the resistance region 20. The resist pattern 51 covers the region 20 a of the resistance region 20. Next, impurities are introduced again into the resistance region 20 using the resist pattern 51 as a mask. Thereby, impurities are again introduced into the region 20b of the resistance region 20.

Thereafter, as shown in FIG. 2C, the resist pattern 51 is removed. Then, an interlayer insulating film 24 is formed on the entire surface including the resistance region 20. Next, a resist pattern (not shown) is formed on the interlayer insulating film 24, and the interlayer insulating film 24 is etched using this resist pattern as a mask. As a result, two connection holes located on the resistance region 20 are formed in the interlayer insulating film 24.
Formed. Thereafter, the resist pattern is removed.

Next, an Al alloy film is formed by sputtering in the two connection holes and on the interlayer insulating film 24. Next, a resist pattern (not shown) is formed on the Al alloy film, and the Al alloy film is etched using the resist pattern as a mask. As a result, Al alloy wirings 26 a and 26 b connected to the resistance region 20 through the connection holes are formed on the interlayer insulating film 24. In the example shown in this figure, the regions 20a and 20b of the resistance region 20 are electrically arranged in series, the region 20a is connected to an Al alloy wiring 26a, and the region 20b is an Al alloy wiring 26b.
Connected to.

The resistance region 20 formed in this manner has different impurity concentrations and different sheet resistance values between the region 20a and the region 20b. Specifically, when impurities of the same conductivity type are introduced in the impurity introduction step shown in FIG. 2A and the impurity introduction step shown in FIG. 2B, the sheet resistance value of the region 20a is the region 20b. Higher than the sheet resistance value. 2B, when an impurity having a conductivity type opposite to that of the impurity introduction step shown in FIG. 2A is introduced, the sheet resistance value of the region 20a is the sheet resistance value of the region 20b. Lower than the value.

The resistance value of the resistance region 20 is the sum of the resistance values of the region 20a and the region 20b when the region 20a and the region 20b are electrically arranged in series.
When b is electrically arranged in parallel, it is the reciprocal of the sum of the reciprocal of the resistance value of the region 20a and the reciprocal of the resistance value of the region 20b.

Thereafter, the resistance value of the resistance region 20 is measured to check whether it is within the allowable range. If it is outside the allowable range, the area ratio of the area 20a and the area 20b is changed by changing the area covered with the resist pattern 51 in the resistance area 20. Accordingly, the resistance value of the resistance region 20 can be changed without changing the impurity introduction amount in the impurity introduction step shown in FIGS. 2 (A) and 2 (B).
Therefore, the resistance value of the resistance region 20 can be changed without changing the design pattern of the semiconductor device and without affecting the resistance values of other resistance elements.

As described above, according to the present embodiment, the area ratio of the region 20a having the first impurity concentration and the region 20b having the second impurity concentration is changed by changing the region covered with the resist pattern 51 in the resistance region 20. And the resistance value of the resistance region 20 can be changed.
Therefore, when the resistance value of the resistance region 20 falls outside the allowable range, the resistance value of the resistance region 20 can be adjusted only by changing the reticle when forming the resist pattern 51. In addition, the resistance value of the resistance region 20 can be changed without affecting the resistance values of other resistance elements.

Each drawing in FIG. 3 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment. In the semiconductor device according to the present embodiment, the resistance element 1 is provided in each of the different regions 1a and 1b.
4,16.

First, as shown in FIG. 3A, a transistor (not shown) is formed in each of regions 1a and 1b of a silicon substrate (not shown), and an interlayer insulating film 10 is formed on the transistor by a CVD method. Next, a resistive element 14 made of a polysilicon pattern on the interlayer insulating film 10,
16 is formed. The formation method of the resistance elements 14 and 16 is the same as that of the resistance element 1 in the first embodiment.
This is the same as the method of forming 2.
Next, impurities are introduced into the entire surface of each of the resistance elements 14 and 16 (all of the regions 14a, 14b, 16a, and 16b).

Next, as shown in FIG. 3B, a photoresist film is applied on the entire surface including the resistance elements 14 and 16, and this photoresist film is exposed using a reticle and then developed. Thus, resist patterns 52a and 52b are formed on the resistance elements 14 and 16, respectively. The resist pattern 52 a covers the region 14 a of the resistive element 14, and the resist pattern 52 b covers the region 16 a of the resistive element 16. Next, impurities are again introduced into the resistance elements 14 and 16 using the resist patterns 52a and 52b as masks.
Thereby, as in the first embodiment, impurities are again introduced into the regions 14b and 14b of the resistance elements 14 and 16, respectively.

Thereafter, as shown in FIG. 3C, the resist patterns 52a and 52b are removed. Then, an interlayer insulating film 17 is formed on the entire surface including the resistance elements 14 and 16. Next, two connection holes located on the resistance element 14 and two connection holes located on the resistance element 16 are formed in the interlayer insulating film 17. These forming methods are the same as the method of forming connection holes in the interlayer insulating film 17 in the first embodiment.

Next, the Al alloy wiring 1 connected to the resistance element 14 through the connection hole on the interlayer insulating film 17.
9a, 19b, and Al alloy wirings 19c, 19d connected to the resistance element 16 through the connection holes
Form. These forming methods are the same as those in the first embodiment in the Al alloy wirings 18a and 18b.
It is the same as the method of forming. In the example shown in this figure, the regions 14a and 14b of the resistive element 14 are electrically arranged in series, and the regions 16a and 16b of the resistive element 16 are electrically arranged in series. The regions 14a and 16a are connected to the Al alloy wirings 19a and 19c, and the regions 14b and 16b are connected to the Al alloy wirings 19b and 19d.

The resistance elements 14 and 16 formed in this way are the resistance element 1 in the first embodiment.
2, the impurity concentrations are different and the sheet resistance values are different between the regions 14 a and 14 b and between the regions 16 a and 16 b. However, the regions 14a and 16a have the same impurity concentration and sheet resistance value. The regions 14b and 16b have the same impurity concentration and sheet resistance value.

Similarly to the first embodiment, the resistance value of the resistance element 14 can be changed by changing the area ratio of the regions 14a and 14b. Further, the resistance value of the resistance element 16 can be changed by changing the area ratio of the regions 16a and 16b. The area ratio of the regions 14a and 14b and the area ratio of the regions 16a and 16 can be changed independently by changing the regions of the resistance elements 14 and 16 that are covered with the resist patterns 52a and 52b.

Therefore, according to the present embodiment, when the resistance value of the resistance element 14 (or 16) falls outside the allowable range, the region covered with the resist pattern 52a (or 52b) in the resistance element 14 (or 16) is defined. By changing, without changing the resistance value of the resistance element 16 (or 14),
In addition, the resistance value of the resistance element 14 can be corrected without changing the design pattern of the semiconductor device.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment. In the semiconductor device according to this embodiment, the regions 1a and 1b are formed in the same process on the same silicon substrate (not shown). The configurations of the regions 1a and 1b are the same as each other. Hereinafter, the same components as those of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG. 4A, an element isolation film 2 is embedded in a silicon substrate 1, and element regions (not shown) in which transistors are formed and resistance regions 21 and 22 in which diffused resistors are formed, Separate from other areas. The planar shapes of the resistance regions 21 and 22 are the same.
Next, impurities are introduced into the entire surface of the resistance regions 21 and 22 (all of the regions 21a, 21b, 22a, and 22b).

Next, as shown in FIG. 4B, a photoresist film is applied over the entire surface including the resistance regions 21 and 22, and this photoresist film is exposed using a reticle and then developed. As a result, resist patterns 53a and 53b are formed on the resistance regions 21 and 22, respectively. The resist pattern 53 a covers the region 21 a in the resistance region 21, and the resist pattern 53 b covers the region 22 a in the resistance region 22. Next, impurities are again introduced into the resistance regions 21 and 22 using the resist patterns 53a and 53b as masks.
As a result, as in the second embodiment, impurities are introduced again into the regions 21b and 22b of the resistance regions 21 and 22, respectively.

Thereafter, as shown in FIG. 4C, the resist patterns 53a and 53b are removed. Then, an interlayer insulating film 24 is formed on the entire surface including the resistance regions 21 and 22. Next, two connection holes located on the resistance region 21 and two connection holes located on the resistance region 22 are formed in the interlayer insulating film 24. These forming methods are the same as the method of forming connection holes in the interlayer insulating film 24 in the second embodiment.

Next, the Al alloy wiring 2 connected to the resistance region 21 through the connection hole on the interlayer insulating film 24.
7a and 27b, and Al alloy wirings 27c and 27d connected to the resistance region 22 through the connection holes
Form. These formation methods are the same as those of the second embodiment in the Al alloy wirings 26a and 26b.
It is the same as the method of forming. In the example shown in this figure, the regions 21a and 21b of the resistance region 21 are electrically arranged in series, and the regions 22a and 22b of the resistance region 22 are electrically arranged in series. The regions 21a and 22a are connected to the Al alloy wires 27a and 27c, and the regions 21b and 21b are connected to the Al alloy wires 27b and 27d.

The resistance regions 21 and 22 formed in this way are the resistance regions 2 in the second embodiment.
Similar to 0, the impurity concentration and the sheet resistance value are different between the regions 21a and 21b and between the regions 22a and 22b. However, the regions 21a and 22a have the same impurity concentration and sheet resistance value, and the regions 21b and 22b have the same impurity concentration and sheet resistance value.

Further, the resistance value of the resistance region 21 can be changed by changing the area ratio of the regions 21a and 21b. Further, the resistance region 2 can be obtained by changing the area ratio of the regions 22a and 22b.
The resistance value of 2 can be changed. The area ratio of the regions 21a and 21b, and the regions 22a,
The area ratio of 22b can be adjusted independently by changing the regions of the resistance regions 21 and 22 that are covered with the resist patterns 53a and 53b.

For this reason, according to this embodiment, when the resistance value of the resistance region 21 (or 22) falls outside the allowable range, the region covered with the resist pattern 53a (or 53b) in the resistance region 21 (or 22). By changing, without changing the resistance value of the resistance region 22 (or 21),
In addition, the resistance value of the resistance region 21 can be corrected without changing the design pattern of the semiconductor device.

Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

Each drawing is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment. Each drawing is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment. Each drawing is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment. Each drawing is a sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 1a, 1b ... area | region 10, 17, 24 ... Interlayer insulation film, 12, 14, 1
6... Resistance element, 20, 21, 22... Resistance region (diffusion resistance), 18a, 18b, 19a to 1.
9d, 26a, 26b, 27a-27d ... Al alloy wiring, 50, 51, 52a, 52b,
53a, 53b ... resist pattern

Claims (11)

Forming a semiconductor pattern on the insulating film;
Performing a first impurity introduction into the semiconductor pattern;
Covering a part of the semiconductor pattern with a mask film, and introducing a second impurity into a region of the semiconductor pattern exposed from the mask film;
Measuring a resistance value of the semiconductor pattern;
Changing the area of the region covered with the mask film in the semiconductor pattern based on the measurement result of the resistance value;
A method for manufacturing a semiconductor device comprising: Separating the resistance region of the semiconductor substrate from other regions by forming an element isolation film on the semiconductor substrate;
Performing a first impurity introduction into the resistance region;
Covering a part of the resistance region with a mask film, and introducing a second impurity into a region of the resistance region exposed from the mask film;
Measuring a resistance value of the resistance region;
Based on the measurement result of the resistance value, the step of changing the area of the resistance region covered by the mask film,
A method for manufacturing a semiconductor device comprising: Forming first and second semiconductor patterns on the insulating film;
Performing a first impurity introduction into the first and second semiconductor patterns;
A portion of the first semiconductor pattern and a portion of the second semiconductor pattern are each covered with a mask film, and a second of the first and second semiconductor patterns is exposed to the region exposed from the mask film. A step of introducing impurities,
Measuring a resistance value of the first semiconductor pattern;
Changing the area of the region covered with the mask film in the first semiconductor pattern based on the measurement result of the resistance value;
A method for manufacturing a semiconductor device comprising: Separating each of the first and second resistance regions of the semiconductor substrate from other regions by forming an element isolation film on the semiconductor substrate;
Performing a first impurity introduction into the first and second resistance regions;
A part of the first resistance region and a part of the second resistance region are covered with a mask film, and a second of the first resistance region and the second resistance region exposed to the mask film is a second region. A step of introducing impurities;
Measuring a resistance value of the first resistance region;
Changing the area of the region covered with the mask film in the first resistance region based on the measurement result of the resistance value;
A method for manufacturing a semiconductor device comprising: 5. The method of manufacturing a semiconductor device according to claim 1, wherein an impurity having the same conductivity type as that of the first impurity introduction is introduced in the step of introducing the second impurity. 5. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of introducing the impurity again, an impurity having a conductivity type different from that of the first impurity introduction is introduced. A semiconductor device comprising a resistance element formed on an insulating film,
The resistance element includes a first region in which impurities are introduced at a first concentration in a semiconductor pattern;
A semiconductor device in which a second region into which an impurity having the same conductivity type as that of the first region is introduced at a second concentration different from the first concentration is arranged in series or in parallel. A semiconductor device comprising a resistance element formed by introducing impurities into a semiconductor substrate,
The resistor element has a first region in which impurities are introduced at a first concentration and an impurity having the same conductivity type as that of the first region is introduced into the semiconductor substrate at a second concentration different from the first concentration. A semiconductor device in which the second regions are arranged in series or in parallel.   The semiconductor device according to claim 7, wherein the resistance element is a part of an oscillation circuit. First and second resistance elements formed on an insulating film and having substantially the same planar shape are provided,
Each of the first and second resistance elements includes a first region in which impurities are introduced at a first concentration in a semiconductor pattern, and an impurity having the same conductivity type as the first region. A second region introduced at a different second concentration, and arranged in series or in parallel;
A semiconductor device in which an area ratio of the second region to the first region differs between the first and second resistance elements. Comprising first and second resistance elements formed by introducing impurities into a semiconductor substrate and having substantially the same planar shape;
Each of the first and second resistance elements includes a first region in which impurities are introduced at a first concentration, and a second concentration in which impurities having the same conductivity type as the first region are different from the first concentration. The second region introduced in (1) is arranged in series or in parallel in the semiconductor substrate,
A semiconductor device in which an area ratio of the second region to the first region differs between the first and second resistance elements.

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