JP3109492B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a resistance element incorporated therein.

[0002]

2. Description of the Related Art When forming a resistance element in a semiconductor device,
FIG. 9 shows two conventional methods generally used.
This will be described below with reference to the schematic configuration diagram of the semiconductor device shown in FIG.

In the first method, as shown in FIG. 9A, a first interlayer insulating film 220 is formed on a silicon substrate 210, and then a diffusion region 910 of the opposite conductivity type is provided by ion implantation or the like. , After covering it with the second interlayer insulating film 240, the first interlayer insulating film 220 on both ends of the diffusion region 910 is formed.
Then, two contact through holes 250 are formed in the second interlayer insulating film 240, and the contact holes 25 are formed.
0, a conductor 260 is buried, a wiring layer 270 is further formed, and a reverse bias is applied to both the silicon substrate 210 and the diffusion region 910, thereby forming a diffusion resistor in the silicon substrate 210.

In a second method, as shown in FIG. 9B, a polycrystalline silicon layer 230 doped with impurities is formed on a first interlayer insulating film 220 by a method such as ion implantation. After the upper part is covered with the second interlayer insulating film 240, a contact through hole 250 is provided, a conductor 260 is embedded in the contact through hole 250, and the contact through hole 250 is covered with a wiring layer 270 to form a resistor.

In each of the above methods, the resistance value R of the resistance element
(Ω) indicates the diffusion region 910 shown in FIG.
It is determined by the resistance length L (interval of the contact through-holes 250) and the resistance width W of the polycrystalline silicon layer 230 shown in (b), and from the sheet resistance ρs (Ω / □) and the contact resistance Rc (Ω),

[Formula 1] R = 2 × Rc + ρs (L / W) Therefore, in order to obtain a desired resistance value R, it is common to adjust the layout of the resistance elements, that is, the resistance length and the resistance width. In other words, the width of the diffusion region 910 or the polycrystalline silicon layer 230,
It is common to adjust the distance between the contact through holes to a desired resistance value.

In forming a contact through hole, a lithography technique using a photoresist is generally applied. Therefore, when fabricating a photoresist mask 110 as shown in FIG.
The desired resistance value is obtained by adjusting the interval between the ten.

[0007]

However, when manufacturing a plurality of resistance elements having different resistance values, it is necessary to design and manufacture a photoresist mask each time, which is inefficient.

Conventionally, for the purpose of finely adjusting the resistance value of a resistance element, a plurality of contact through holes are formed in advance in one resistance element, and wiring is performed so as to have a value closest to a desired resistance value. The method is disclosed in JP-A-59-827.
No. 59. According to this method, a plurality of resistance elements manufactured using the same photoresist mask can have a certain degree of resistance.

However, in this case, it is sufficient to use one photoresist mask, but it is necessary to manufacture a plurality of masks used when forming the wiring layer, which is also inefficient. Was.

It is an object of the present invention to efficiently manufacture a semiconductor device in which a plurality of resistance elements having different resistance values are incorporated by using only the same mask when forming a contact through hole and a wiring layer. Is to provide a way to

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: contacting an insulating layer provided above a resistor on a semiconductor substrate with a contact penetrating the resistor; In the step of forming a through hole,
Using a mask having a pair of openings with a fixed spacing, and one or more sub-openings located in each opening close to each other in the direction from the opening to the other opening Patterning the photoresist, and adjusting the exposure time at that time, determines the remaining or non-residual of the photoresist between the opening and the sub-opening, and adjusts the resistance value. I do. Thus, a plurality of semiconductor devices having different contact hole intervals, that is, a plurality of semiconductive devices incorporating resistance elements having different resistance values can be manufactured using the same mask. Further, since the resistance value is already determined at the stage of forming the contact hole, the subsequent wiring layout may be the same.

Further, in the method of manufacturing a semiconductor device according to the present invention, a mask having a plurality of sub-openings arranged in each opening such that the interval is gradually increased in the direction of the other opening. It is characterized by doing. Thus, a plurality of semiconductor devices having different contact hole intervals, that is, a plurality of semiconductor devices incorporating resistance elements having different resistance values can be manufactured using the same mask. Also,
Since the resistance value is already determined at the stage of forming the contact hole, the subsequent wiring layouts may be all the same.

According to the present invention, in a photoresist patterning step for forming a contact through hole, a plurality of resistance elements having different resistance values are incorporated with the same mask by adjusting the shape of a mask to be used and the photoresist exposure time. A semiconductor element is formed.

Conventionally, in a mask used in this step, as shown in FIG. 10, a pair of openings 110 having a fixed interval are formed, and the resistance value is determined by the interval. It is. In the present invention, as shown in FIG.
For each, the sub-opening 120 is provided close to the position facing the other opening.

After the application of the photoresist, the mask 1
Using 00, patterning by exposure is performed. At this time, by adjusting the exposure time, (1) In the case of performing short-time exposure, the photoresist in the gap remains, and the opening and the sub-opening are independent from each other. In the case of performing exposure for a long time, the photoresist in the gaps disappears, and a shape in which the opening portion and the sub-opening portion are integrated and a shape different from each other are patterned. Therefore, in a subsequent step, that is, a step of forming a contact through hole with this photoresist to bury a conductor and further forming a wiring layer, a plurality of resistance elements having different resistance values while maintaining the same wiring layer layout. Is what you get.

As shown in FIG. 1, the mask may have a single sub-opening, or a plurality of sub-openings. At this time,
The sub-openings are arranged such that the gap gradually increases toward the other opening. In this way, as the exposure time is lengthened, the photoresist in the gaps gradually disappears, the resistance length gradually decreases, and it is possible to sequentially form resistance elements having lower resistance values. is there.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below. As a typical example for facilitating understanding, the manufacturing process of the above-described resistive element of a type in which a polycrystalline silicon layer doped with impurities by a method such as ion implantation is formed on the first insulating layer is described. It will be described in order while following.

First, as shown in FIG. 2, a first interlayer insulating film 220 having a thickness of 500 to 1000 nm is formed on a silicon substrate 210. Next, a polycrystalline silicon layer 230 having a thickness of 200 to 300 nm is formed, and impurities are doped to obtain a desired sheet resistance. Thereafter, a second interlayer insulating film 240 is formed on the entire surface. Here, in order to facilitate understanding, the width W of the polycrystalline silicon layer 230 is set to 2.5 μm, and the sheet resistance ρs is set to 500Ω / □.

Next, a photoresist is applied on the second interlayer insulating film 240 and is patterned by exposure. At this time, the mask 100 shown in FIG. 1 is used. The mask 100 has an opening 110 and a sub-opening 120. Here, the width of both the opening and the sub-opening is 0.1 mm.
5 μm, and the interval between them is 0.3 μm.

The exposure time is adjusted in the patterning step. FIG. 3 shows an example of the relationship between the exposure time and the dimensions of the opening and the gap. If such a correlation is grasped in advance, different shapes are patterned by adjusting the exposure time. For example, FIG. 3 shows that the opening portion and the sub-opening portion have independent shapes when the exposure time is 350 ms or less, while they have an integrated shape when the exposure time is 350 ms or more. Therefore, (1) the exposure time is set to 300 ms and the shape is the same as that of the mask 100. (2) The exposure time is set to 350 ms and the portion of the opening 110 and the portion of the sub-opening 120 are integrated. Think assuming.

After completion of the patterning process, formation of the contact through hole 250, removal of the photoresist, embedding of the conductor 260, and formation of the wiring layer 270 are performed in this order. The cross section and upper surface after the formation of the wiring layer 270 are shown in FIG. 4 for (1) and in FIG. 5 for (2).

The layout of the wiring layer 270 is common to (1) and (2). However, the resistance length L is different from (1) L1 = 4 + 2 × (0.5 + 0.3) = 5.6 (2) L2 = 4-2 × (0.15) = 3.7

Here, the resistance length in the case (2) will be described. In the case of (2), the portion of the opening 110 and the portion of the sub-opening 120 are widened by 0.15 μm on each side due to long-time exposure of the photoresist, and the distance between the openings in the mask ( 4 μm).

The resistance value R1 in the above (1) and (2)
And R2 are

## EQU1 ## where R = 2 × Rc + ρs (L / W), L1, L2, W (2.5 μm) and ρs (50
0 Ω / □), and (1) R1 = 2 × Rc + 1120 (Ω) (2) R2 = 2 × Rc + 740 (Ω), which are obviously different values. That is, it is possible to obtain a semiconductor device in which a plurality of resistance elements having different resistance values are incorporated by using only the same mask when forming the contact through hole and the wiring.

Next, a second embodiment of the present invention will be described. In the present embodiment, as shown in FIG. 6, a mask 100 provided with a plurality of sub-openings is used. In this case, the sub-openings are arranged such that the distance between the openings gradually increases toward the other opening.
Here, a case is considered where the distance between the opening 110 and the sub-opening 120A is 0.3 μm, and the distance between the sub-opening 120A and the blowing opening 120B is 0.5 μm.

Using such a mask 100, the steps up to the application of the photoresist are completed in exactly the same manner as in the first embodiment. In the subsequent steps, as in the first embodiment, (1) the exposure time is 280 ms, and the shape is the same as that of the mask 100 (FIG. 7A). (2) The exposure time is 350 ms, The part and the part of the sub-opening 120A are formed into an integral shape (FIG. 7).
(B)) It is possible, however, to further lengthen the exposure time so that the photoresist between the sub-opening 120A and the sub-opening 120B also disappears, and as shown in FIG. 11
It is also possible to form an integral shape from 0 to the sub-opening 120B. By doing so, the resistance length L3 is further reduced, and a resistance element having a smaller resistance value can be obtained.

Although two sub-openings are provided for each opening here, more sub-openings may be provided as necessary. In this way, by adjusting the exposure time, it is possible to obtain a semiconductor device incorporating a plurality of resistance elements having different resistance values.

Although the width of the opening and the width of the sub-opening are the same, they are not essential and may be different. Furthermore, the size of the gap portion only needs to be gradually increased toward the other opening, and is not limited to the size described in the present embodiment. The sub-openings do not necessarily have to have the same dimensions. However, when a large number of sub-openings are provided as described above, all the sub-openings have the same dimensions in order to determine an exposure time for obtaining a desired resistance value. It is easier and preferred.

Further, for example, after forming the polycrystalline silicon layer 230 and the second interlayer insulating film 240, further forming a second polycrystalline silicon layer 830 and a third interlayer insulating film 840 as shown in FIG. In the element having the structure, even when the contact through hole 250 is formed on the third interlayer insulating film 840, the present invention can be similarly applied, and the exposure time is adjusted as shown in FIG. Resistance elements having different resistance values as shown in FIG. 8C can be obtained.

Although the embodiment of the semiconductor device of the type in which the polycrystalline silicon layer is formed has been described above, the present invention can be applied to the semiconductor device of the type in which a diffusion region is provided on a silicon substrate. .

[0031]

As described above, according to the present invention, when forming a contact through hole and a wiring layer, only the same mask is used, and a plurality of resistance elements having different resistance values are incorporated. Can be manufactured efficiently.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the shape of a photoresist mask used in the present invention.

FIG. 2 is a diagram illustrating a first embodiment of the present invention.

FIG. 3 is a view for explaining an effect of a photoresist exposure time in the present invention.

FIG. 4 is a diagram illustrating a first embodiment of the present invention.

FIG. 5 is a diagram illustrating a first embodiment of the present invention.

FIG. 6 is a diagram illustrating the shape of a photoresist mask used in a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a second embodiment of the present invention.

FIG. 8 is a diagram illustrating still another embodiment of the present invention.

FIG. 9 is a diagram illustrating a conventional method of manufacturing a semiconductor device.

FIG. 10 is a view for explaining the shape of a photoresist mask used in a conventional semiconductor device manufacturing method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 mask 110 opening 120 sub-opening 210 silicon substrate 220 first interlayer insulating film 230 polycrystalline silicon layer 240 second interlayer insulating film 250 contact through hole 260 conductor 270 wiring layer 830 second polycrystalline silicon layer 840 third interlayer Insulating film 910 Diffusion area

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822

Claims (2)

(57) [Claims] In a step of forming a contact through hole penetrating through a resistor in an insulating layer provided on a resistor on a semiconductor substrate, a pair of openings having a constant interval; Patterning the photoresist using a mask having at least one sub-opening disposed in each opening in the direction from the opening to the other opening, and an exposure time at that time; A method for determining the residual or non-residual photoresist remaining between the opening and the sub-opening by adjusting the resistance, and adjusting the resistance value. 2. The method according to claim 1, wherein a mask having a plurality of sub-openings is used in each of the openings so that the distance between the openings increases in the direction of the other openings. 5. The method for manufacturing a semiconductor device according to claim 1.