JP2007317892A - Multilayered inductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a structure of low profile improved in DC superposition characteristics and reduced in AC loss. <P>SOLUTION: A coil that circulates in spiral while overlapping in stacking direction within an electric insulator is formed by alternately stacking a magnetic layer 22 of an electrically insulated body, and a sequentially connected internal conductor pattern 20. The both ends of the coil are drawn out of the laminate chip outside surface, through a drawing-out conductor pattern 24, and connected to an external electrode. 0.5<SU/SI≤1 and 0.2≤SI/SA are satisfied, where SI is the cross-sectional area of the internal magnetic path vertical to the stacking direction inside the coil, SU is the crosssectional area of the external magnetic path parallel to the stacking direction outside the coil end, and SA is the total cross-sectional area vertical to the stacking direction of the laminate chip. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a chip inductor having a multilayer structure. More specifically, the present invention relates to a multilayer inductor having improved direct current superposition characteristics by optimizing the shape of an internal conductor pattern. This multilayer inductor is particularly suitable for power inductors for mobile applications.

  In the past, power inductors used in power circuits such as DC-DC converters were generally configured by winding a coil around a magnetic core. However, in recent years, there has been a demand for smaller and thinner power circuit components. Along with this, chip components with a laminated structure have been developed and put into practical use. Multilayer power inductors are often used for mobile power supplies, and are the largest components among DC-DC converter components, albeit small. Up to now, chips with a height of about 1 mm have been frequently used. Recently, however, there is an increasing demand for further reduction in height, such as 0.8 mm or 0.5 mm.

  Multilayer inductors have a magnetic layer that is an electrical insulator made of a magnetic material and internal conductor patterns that are alternately stacked, and the internal conductor patterns are sequentially connected to form a spiral while overlapping in the stacking direction in the electrical insulator. In this structure, a coil that circulates is formed, and both ends of the coil are led out to the outer surface of the multilayer chip through lead conductor patterns and connected to external electrodes. That is, the coil is embedded in the magnetic chip. The magnetic layer and the internal conductor pattern are formed and stacked by using, for example, a screen printing technique. Such a multilayer inductor is characterized in that since the coil is surrounded by a magnetic material, there is little magnetic leakage, and a necessary inductance can be obtained with a relatively small number of turns, which is suitable for downsizing and thinning.

  By the way, a multilayer inductor often forms a coil by laminating and sequentially connecting internal conductor patterns of less than one turn per layer (for example, 1/2 turn or 3/4 turn) (for example, see Patent Document 1). ). However, with such a configuration, the number of times of printing increases and the number of printed layers increases, so when trying to reduce the height of the laminated chip, the magnetic material on both outer sides of the coil must be very thin. This causes deterioration of the DC superimposition characteristics (abrupt decrease in inductance due to magnetic saturation of the magnetic material). Further, the increase in the number of layers increases the magnetic flux passing between the internal conductor patterns, and the AC resistance increases because the change in inductance at the time of low DC bias is abrupt. This means that the loss due to the standby current becomes large, which is a big problem particularly in mobile applications.

On the other hand, as a chip inductor, there is also a form in which a coil is formed by multiple winding (spiral shape) in one layer (see, for example, Patent Document 2). Although this structure has an advantage that the height can be reduced, the magnetic material inside the coil is reduced, so that the direct current superimposition characteristic is deteriorated and is not suitable for a power inductor.
Japanese Patent Publication No. 6-56812 JP 2000-114043 A

  The problem to be solved by the present invention is to realize a structure suitable for a power inductor that can improve DC superposition characteristics and reduce AC loss and can be reduced in height.

  In the present invention, magnetic layers that are electrical insulators and internal conductor patterns are alternately stacked, and the internal conductor patterns are sequentially connected to form a coil that spirals around the electrical insulator while overlapping in the stacking direction. In the multilayer inductor having a structure in which both ends of the coil are drawn to the outer surface of the multilayer chip via the lead conductor pattern and connected to the external electrode, the internal magnetic path cross-sectional area perpendicular to the stacking direction inside the coil is represented by SI. , Where SU is the cross-sectional area of the external magnetic path parallel to the laminating direction outside the coil end, and SA is the total cross-sectional area perpendicular to the laminating direction of the multilayer chip, 0.5 <SU / SI ≦ 1 and 0. A multilayer inductor characterized by satisfying a relationship of 2 ≦ SI / SA.

  Here, the inner conductor pattern may be less than one turn per layer, but in order to reduce the height, it is preferable that the number of turns is not less than 1 turn and not more than 3 turns per layer. In addition, it is preferable that most of the electrical insulator constituting the multilayer chip is made of a magnetic material, and a nonmagnetic layer is disposed between all layers of the internal conductor pattern. This multilayer inductor is particularly suitable for a power inductor for mobile use used in a power supply circuit such as a DC-DC converter.

  The multilayer inductor according to the present invention can optimize the DC superposition characteristics on the high bias side by balancing the magnetic path inside and outside the coil by optimizing the coil shape inside the multilayer chip. In particular, when the number of turns per layer is set to 1 to 3, it is possible to simultaneously achieve both a reduction in the number of printing times and a reduction in height while maintaining excellent direct current superposition characteristics. In addition, when the non-magnetic layer is arranged between the inner conductor patterns, it is possible to prevent the occurrence of a minute magnetic circuit loop surrounding the inner conductor pattern and reduce the AC loss on the low bias side.

  An example of the multilayer inductor according to the present invention is shown in FIG. In FIG. 1, A shows an appearance, B shows a state where a conductor pattern is seen through from the upper surface, and C shows a longitudinal section.

  This multilayer inductor 10 is a surface-mounted chip component having a substantially rectangular parallelepiped shape, and a coil is embedded in almost all of a magnetic material, and both ends of the coil are formed at both ends of the chip. The structure is electrically connected to the electrode 12 (see A in FIG. 1).

  The internal coil structure is formed by printing a substantially annular inner conductor pattern 20 (one turn per layer) and an electrically insulating magnetic layer 22 by screen printing or the like and alternately laminating them. The internal conductor patterns 20 are sequentially connected to form a coil in a magnetic body by the magnetic layer 22 so as to circulate in a spiral shape while being superimposed in the stacking direction. Electrical connection between the internal conductor patterns is performed using a well-known via hole or the like. Here, as shown in FIG. 1B, the inner conductor pattern is wound in a rectangular shape while being bent at a right angle. Both ends of the coil are respectively drawn out to opposite end faces of the outer surface of the multilayer chip via the lead conductor pattern 24 and connected to the external electrode 12.

  In the multilayer inductor according to the present invention, the internal magnetic path cross-sectional area perpendicular to the stacking direction inside the coil is SI (= xx), and the external magnetic path cross-sectional area parallel to the stacking direction outside the coil end is SU ( = (X + y) × 2 × z), where SA (= L × W) is the total cross-sectional area perpendicular to the stacking direction of the stacked chips, 0.5 <SU / SI ≦ 1, and 0. It is designed to satisfy the relationship 2 ≦ SI / SA. Here, x and y are vertical and horizontal dimensions of the coil inner magnetic path, z is a length in the stacking direction from the coil end to the surface of the multilayer chip, and L and W are vertical and horizontal dimensions of the multilayer chip.

  FIG. 2 is a modified example thereof, and B is an enlarged view of a main part. Between the layer of the internal conductor pattern 20 and another layer of the internal conductor pattern 20 that overlaps with the space, not the magnetic layer but the electrically insulating nonmagnetic layer 26. Such a nonmagnetic layer 26 has a ring shape (square frame shape) that is substantially the same as the inner conductor pattern 20, and is preferably slightly wider than the inner conductor pattern 20. By making the pattern slightly wider, when the internal conductor pattern 20 is printed, it is possible to prevent the occurrence of a short circuit due to the inflow of the conductor paste, and to suppress the reduction of the magnetic path cross section as much as possible. It is most preferable that the entire portion between the layers of the inner conductor pattern 20 is the nonmagnetic layer 26, but only a part may be a nonmagnetic layer.

  Another example of the multilayer inductor according to the present invention is shown in FIG. This is an example in which the inner conductor pattern forming the coil has approximately two turns per layer. The manufacturing method is the same as in the case of one turn. The internal conductor pattern 20 and the electrically insulating magnetic layer 22 are printed by a screen printing method or the like and are alternately stacked. The inner conductor pattern 20 is connected in a magnetic body by the magnetic layer 22 so as to circulate spirally while being superimposed in the stacking direction to form a coil. Electrical connection between the internal conductor patterns is performed using a well-known via hole or the like. Both ends of the coil are respectively drawn out to opposite end surfaces of the outer surface of the multilayer chip via the lead conductor pattern 24 and connected to the external electrodes.

  Also in the case of this structure, in the present invention, the internal magnetic path cross-sectional area perpendicular to the stacking direction inside the coil is SI (= xx), and the external magnetic path cross-sectional area parallel to the stacking direction is outside the coil end. SU (= (x + y) × 2 × z), where SA (= L × W) is the total cross-sectional area perpendicular to the stacking direction of the stack chip, 0.5 <SU / SI ≦ 1, and It is designed to satisfy the relationship of 0.2 ≦ SI / SA. X and y are the vertical and horizontal dimensions of the coil internal magnetic path surrounded by the innermost internal conductor pattern.

  FIG. 4 shows a modification thereof, and B is an enlarged view of a main part. Between the layer of the internal conductor pattern 20 and another layer of the internal conductor pattern 20 that overlaps with the space, not the magnetic layer but the electrically insulating nonmagnetic layer 26. Such a nonmagnetic layer 26 has a rectangular frame shape that just covers the double-wrapped inner conductor pattern (substantially coincides with the outermost and innermost edges of the coil formed by the inner conductor pattern).

  The inner conductor pattern may be less than one turn per layer, but as described above, it is preferable that the number of turns be not less than 1 turn and not more than 3 turns per layer. If the number of turns is less than 1 turn per layer, the number of layers increases to achieve the required inductance, which is disadvantageous for multilayer inductors with a height of 1 mm or less. On the other hand, if the number of turns exceeds 3 turns, This is because since the total cross-sectional area perpendicular to the stacking direction of the multilayer chip cannot be increased, the cross-sectional area of the magnetic path inside the coil is reduced, which is disadvantageous in terms of improving DC superposition characteristics.

  Specifically, a multilayer power inductor having an outer dimension of 3.2 mm × 2.5 mm × 0.5 mm and having a coil of 4.5 turns will be described as an example. When the number of internal conductor patterns is less than one turn, the total number of internal conductor patterns is at least 5 and the number of layers is 4 layers. If the number of turns is 2.5 per internal conductor pattern, a coil can be formed with a total of two layers, with one layer between layers. In order to make the DC resistance the same in both cases, it is necessary to compensate for the printing thickness by the amount that the line width of the internal conductor pattern is reduced by half and the space between the lines is secured in the latter. For example, when the former printing thickness is 20 μm, the interlayer is 15 μm, the latter printing thickness is 35 μm, and the interlayer is 15 μm, the structural differences shown in Table 1 occur. Here, the increase in the thickness of the magnetic layer above and below the coil in the latter directly leads to an improvement in the DC superposition characteristics.

  Further, as shown in FIG. 2 or FIG. 4, it is preferable that the electrical insulator of the multilayer chip is made of a magnetic material and a nonmagnetic layer is disposed between all the layers of the internal conductor pattern. This is because the occurrence of a minute magnetic path loop surrounding the inner conductor pattern can be prevented and an increase in AC loss can be suppressed.

  The DC superposition characteristics were determined for several types of samples with the same outer dimensions of the multilayer chip and different coil shapes embedded therein. The results will be described below.

Example 1
The chip outer dimensions were all 2.5 mm × 2.0 mm × 0.5 mm (L × W × H), and the internal conductor pattern was formed so that the DC resistance of the coil was constant. There are six types of samples shown in Table 2. Samples a to c are one turn or less per layer (specifically, a U-shaped pattern of approximately 3/4 turns is adopted), and samples df are cases where one layer is two turns. The internal magnetic path cross-sectional area SI perpendicular to the stacking direction inside the coil and the external magnetic path cross-sectional area SU parallel to the stacking direction outside the coil end are changed. Note that a nonmagnetic layer is inserted at a substantially central position in the stacking direction of the chips.

  FIG. 5 shows the DC superposition characteristics of these multilayer inductors. A in FIG. 5 represents a change in inductance with respect to a DC bias. Samples a, b, and d have a large deterioration in DC superimposition characteristics, and samples c and f have greatly reduced inductance (represented by L @ 0A) at DC bias current 0A. FIG. 5B plots the relationship of L @ 0A to SI / SA and the relationship of DC bias (represented by L30% reduction) with a 30% reduction in inductance to SU / SI. It can be seen that L @ 0A rapidly decreases when SI / SA is 0.2 or less. It can also be seen that when SU / SI is less than 0.5, the L30% reduction is very small.

  From this result, it can be seen that in the case of a low profile type with a chip height of 0.5 mm, it is extremely difficult to develop a good DC superposition characteristic with one turn or less per layer.

(Example 2)
The chip outer dimensions were all 2.5 mm × 2.0 mm × 1.0 mm (L × W × H), and the internal conductor pattern was formed so that the DC resistance of the coil was constant. There are six types of samples shown in Table 3. Samples g to i are 1 turn or less per layer (specifically, a U-shaped pattern of approximately 3/4 turns is adopted), and samples j to l are cases where 1 layer is 2 turns. The internal magnetic path cross-sectional area SI perpendicular to the stacking direction inside the coil and the external magnetic path cross-sectional area SU parallel to the stacking direction outside the coil end are changed. Also here, a nonmagnetic layer is inserted at a substantially central position in the stacking direction of the chips.

  In these multilayer inductors, DC superposition characteristics are shown in FIG. A in FIG. 6 represents a change in inductance with respect to a DC bias. In the samples j, k, and l, the inductance (represented by L @ 0A) at the DC bias current 0A is greatly reduced. FIG. 6B plots the relationship of L @ 0A to SI / SA and the relationship of DC bias (represented by L30% reduction) with a 30% reduction in inductance to SU / SI. It can be seen that L @ 0A rapidly decreases when SI / SA is 0.2 or less.

  When the chip height is relatively high, such as 1.0 mm, it can be seen that good DC superposition characteristics can be exhibited even with one turn or less per layer. However, the direct current superimposition characteristic is better in the sample j (1 layer 2 turns) than in the samples g and h (both 1 layer 1 turn or less).

Explanatory drawing which shows an example of the multilayer inductor which concerns on this invention. The longitudinal cross-sectional view of the modification. Explanatory drawing which shows the other example of the multilayer inductor which concerns on this invention. The longitudinal cross-sectional view of the modification. The graph which shows an example of a direct current superposition characteristic. The graph which shows the other example of a direct current | flow superimposition characteristic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Multilayer inductor 12 External electrode 20 Internal conductor pattern 22 Magnetic layer 24 Leader conductor pattern 26 Nonmagnetic layer

Claims (3)

A magnetic layer and an internal conductor pattern which are electrical insulators are alternately stacked and the internal conductor patterns are sequentially connected to form a coil that spirals around the electrical insulator in the stacking direction. In the multilayer inductor having a structure in which both ends of each are drawn to the outer surface of the multilayer chip through the lead conductor pattern and connected to the external electrode,
The internal magnetic path cross-sectional area perpendicular to the stacking direction inside the coil is SI, the external magnetic path cross-sectional area parallel to the stacking direction outside the coil end is SU, and the total cross-sectional area perpendicular to the stacking direction of the multilayer chip is SA. The multilayer inductor is characterized in that the relationship of 0.5 <SU / SI ≦ 1 and 0.2 ≦ SI / SA is satisfied.   The multilayer inductor according to claim 1, wherein internal conductor patterns of 1 turn or more and 3 turns or less are laminated per layer. 3. The multilayer inductor according to claim 1, wherein most of the electrical insulator constituting the multilayer chip is made of a magnetic material, and a nonmagnetic layer is disposed between layers of the internal conductor pattern.

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