JP2007310438A - Interruption processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the request of interruption processing to a CPU in the order of the generation of interruption requests when a plurality of interruption requests are made. <P>SOLUTION: This interruption processing circuit is provided with a generation order storage circuit 3 for assigning and storing priority orders to a plurality of interrupting inputs having the same priority order according to the generation order of the interruption requests. The generation order storage circuit 3 requests interruption processing to a CPU about the interrupting input whose priority order is the highest, and each time the interruption processing about the interrupting input whose priority order is the highest is completed, the generation order storage circuit 3 updates the storage content so that the priority order about the residual interrupting inputs whose interruption requests have been made can be advanced by one. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an interrupt processing circuit that requests an interrupt process according to an interrupt input from a CPU according to the order of generation of the interrupt request when an interrupt request is made to a plurality of interrupt inputs having the same priority. .

  An interrupt processing circuit (interrupt controller) is interposed between the CPU and the peripheral device, and when there is an interrupt request from the peripheral device, an interrupt request to an interrupt input with a high priority based on a preset priority order The CPU requests interrupt processing sequentially from the CPU. When an interrupt process is requested to the CPU, the CPU interrupts the currently executing process and executes the interrupt process, and the interrupted original process is resumed after the interrupt process is completed.

  A conventional interrupt processing circuit has a plurality of interrupt inputs, as represented by an interrupt controller 8259 made by Intel, for example, and given a priority order determined in advance for each interrupt input.

  Using such an interrupt processing circuit, if you want to process multiple interrupt requests with the same priority in the order in which the interrupt requests are generated, it will be in a predetermined priority order. There was a problem that interrupt processing was not executed in order. This is a remarkable example when multiple interrupts occur (when another interrupt request is generated during execution of a certain interrupt process).

  FIG. 4 is a block diagram showing the configuration of a conventional interrupt processing circuit, and FIG. 5 is an explanatory diagram of processing at the time of multiple interrupts using this interrupt processing circuit. In FIG. 4, 1 is an interrupt request register (IRR) for receiving four interrupt inputs IR0 to IR3, 6 is a priority assignment in which the highest priority is assigned to the interrupt input IR0 and the lower priority is assigned in the order of IR1, IR2, IR3. Circuit 4 is an in-service register (ISR) indicating an interrupt input for which interrupt processing is currently being performed, 5 is a command exchange with the CPU, interrupt request register 1, priority allocation circuit 6, in-service register 4 is a control circuit for controlling 4.

  When there is an interrupt request for any one of the interrupt inputs IR0 to IR3, the interrupt request register 1 sets a flag “1” on the output corresponding to the interrupt input and sends it to the priority assignment circuit 6 and the control circuit 5. . When there is no other interrupt input, the control circuit 5 outputs an interrupt request (INT) to the CPU based on this input, and upon receiving an interrupt permission (inversion of INTA) from the CPU, the corresponding “1” in the interrupt request register 1 Is reset to “0” so that the next interrupt request can be accepted. The in-service register 4 sets the content corresponding to the interrupt input to “1” during the interrupt processing of the CPU by the control circuit 5 and indicates which interrupt input the current processing is. When 5 receives an interrupt processing completion (EOI) from the CPU, the control circuit 5 resets the corresponding content to “0”.

  When the user constructs a system using the interrupt processing circuit having such a configuration, it is necessary to grasp in advance the priority order of interrupt requests to be used and assign them to the interrupt inputs IR0 to IR3. In this example, IR0 to IR3 are used as interrupt inputs, but it is assumed that the user assumes that the interrupt inputs IR1, IR2, and IR3 have the same functional priority.

  In this case, as shown in FIG. 5, first, when an interrupt request is generated at the first interrupt input IR0 while the CPU is executing the main routine, the processing is interrupted from the main routine to the interrupt routine corresponding to the interrupt input IR0. Fly to. Even if an interrupt request is generated in the interrupt input IR3 during execution of the interrupt routine corresponding to the interrupt input IR0, the interrupt input IR0 has the highest priority, so that the processing of the interrupt input IR3 is not skipped. After that, even if an interrupt request is generated at the interrupt input IR2, the routine corresponding to the interrupt input IR0 continues to be executed as before. Thereafter, even if an interrupt request is further generated at the interrupt input IR1, the execution of the interrupt routine corresponding to the interrupt input IR0 continues.

  When the processing of the interrupt routine corresponding to the interrupt input IR0 is completed, the interrupt processing circuit reads the flag of the interrupt request register 1 storing the status of the interrupt input waiting for service, and the interrupt inputs IR1, IR2, and IR3 process them. Recognize that you are waiting. In such a case, since the user connected an interrupt request with the same priority to the interrupt inputs IR1, IR2, and IR3, the interrupts are processed in the order of IR3, IR2, and IR1 according to the original generation order. I hope that.

  However, in practice, the interrupt processing circuit of FIG. 4 refers to the priority order assignment of the priority order assignment circuit 6 and determines to service the interrupt input IR1 having the highest priority among them. If no request is generated for the interrupt input IR0 during the execution of the interrupt routine corresponding to the interrupt input IR1, the interrupt input IR2 of the next priority is completed when the processing of the interrupt routine corresponding to the interrupt input IR1 is completed. The process proceeds to the interrupt routine corresponding to. Thereafter, if a request is not generated for the interrupt inputs IR0 and IR1 during the execution of the interrupt routine corresponding to the interrupt input IR2, the next priority is given when the processing of the interrupt routine corresponding to the interrupt input IR2 is completed. The process proceeds to the interrupt routine corresponding to the interrupt input IR3.

  As described above, in the interrupt processing circuit shown in FIG. 4, interrupt processing may not be performed in the order expected by the user. That is, there is a case where a long time is required before execution even though it occurs early, like IR3 in FIG.

Conventionally, as a proposal for detecting the order in which interrupt requests are generated, there is a method of writing interrupt request generation time information in a memory (Patent Document 1). In addition, there is an interrupt order setting sense register for setting an interrupt order, which recognizes the interrupt generation order based on the contents thereof and processes them in the order of generation (Patent Document 2).
JP-A-11-338712 Japanese Patent Laid-Open No. 08-212082

  However, the method described in Patent Document 1 is intended to enable tracing of the exact order of occurrence of interrupt requests when a failure occurs, and there is no description about determining the priority according to the order of occurrence. The technique described in Patent Document 2 recognizes the generation order of interrupt requests and processes them in that order. However, since the contents of the interrupt order setting sense register are read and processed, the interrupt to be processed next is processed. A special software process that performs comparison and decision processing is required to determine which one will be.

  An object of the present invention is to enable interrupt processing requests to the CPU in the order in which interrupt requests are generated without requiring special software processing when there are a plurality of interrupt requests. An interrupt processing circuit is provided.

In order to achieve the above object, the interrupt processing circuit according to the first aspect of the present invention is configured such that when there are interrupt requests for a plurality of interrupt inputs having the same priority, the interrupt processing circuit is configured according to the order of generation of the interrupt requests. An interrupt processing circuit for requesting an interrupt process according to an input to a CPU, comprising: an occurrence order storage means for allocating and storing a priority order according to the occurrence order of the interrupt request for each of the plurality of interrupt inputs; The generation order storage means requests the CPU for interrupt processing for the highest priority interrupt input, and each time the interrupt processing for the highest priority interrupt input is completed, the remaining interrupt input for which an interrupt request has been made The stored contents are updated so that the priorities are incremented one by one.
According to a second aspect of the present invention, in the interrupt processing circuit according to the first aspect, a flag is individually set for an interrupt input for which an interrupt request has been made, and the flag is reset for an interrupt input for which interrupt processing has been completed. An interrupt request accepting unit that does not accept a new interrupt request for an interrupt input that is standing, and the occurrence order storage unit is configured to receive a current interrupt request accepting unit when there is a new interrupt request for a specific interrupt input. A priority order is assigned to the specific interrupt input by referring to the number of flags that are present.
According to a third aspect of the present invention, in the interrupt processing circuit according to the second aspect of the present invention, the interrupt processing circuit includes a rising edge detecting unit that detects a rising edge of the flag of the interrupt request receiving unit, and the generation order storage unit includes: A new interrupt request for the specific interrupt input is known from the detection output.

  According to the present invention, the contents stored in the generation order storage means are updated so that the priority order is incremented by one for the remaining interrupt inputs for which an interrupt request has been made each time the interrupt processing for the highest priority interrupt input is completed. Therefore, the interrupt input with the highest priority is updated sequentially, and even if there are multiple interrupt requests without requiring special software processing, interrupt processing is performed in the order in which the interrupt requests are generated. Can be done.

  FIG. 1 is a block diagram showing the configuration of an interrupt processing circuit according to one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an interrupt request register (IRR) (corresponding to the interrupt request receiving means in the claims), which is the same as described in FIG. 4, and is one of the four interrupt inputs IR0 to IR3. When an interrupt request is received, the corresponding one of the outputs IRA0 to IRA3 is set to “1” and a flag is set.

  Reference numeral 2 denotes an IRR rising edge detection circuit (corresponding to the rising detection means in claims). As shown in FIG. 2, for each output IRA0 to IRA3 from the interrupt request register 1, a combination of FF21 and AND circuit 22 is used. When the outputs IRA0 to IRA3 of the interrupt request register 1 rise to “1”, the rising edge is detected and a “1” pulse is output to the corresponding one of the outputs IRB0 to IRB3.

  Reference numeral 3 denotes a generation order storage circuit (corresponding to the generation order storage means in the claims), which inputs the outputs IRA0 to IRA3 of the interrupt request register 1 and the pulse outputs IRB0 to IRB3 of the IRR rising edge detection circuit 2, With reference to the number of “1” of the outputs IRA0 to IRA3, there is an occurrence order storage register (ISQ) for storing the order of rising of the interrupt inputs IR0 to IR3. The values of the four outputs corresponding to the interrupt inputs IR0 to IR3 of the generation order storage register (ISQ) are ranked according to any one of “0”, “1”, “2”, “3”, and “4”. Indicates. “0” is no interrupt request, “1” is the highest priority, “2” is the next priority,..., “4” is the lowest priority.

  When the system is reset, the generation order storage circuit 3 sets the four outputs of the generation order storage register (ISQ) to “0”. Further, when a “1” pulse is generated in any of the outputs IRB0 to IRB3 of the IRR rising detection circuit 2, the outputs (flags) of the outputs IRA0 to IRA3 of the interrupt request register 1 are checked and if there is “1” there. Then, “+1” is set to the maximum value of the output of the generation order storage register (ISQ) corresponding to the output IRB0 to IRB3 which has already become “1”, and is stored in the generation order storage register (ISQ).

  For example, when a “1” pulse is generated at the output IRB0 of the IRR rising edge detection circuit 2, if the number of “1” s of the outputs IRA0 to IRA3 of the interrupt request register 1 is one in total, the highest priority is given. If there are two “1” s, “2” of the next priority is assigned to the interrupt input IR0. Remember.

  Further, when the interrupt processing is completed and the interrupt processing completion (EOI) issued by the CPU is received by the control circuit 5, the generation sequence storage circuit 3 outputs each output other than “0” in the generation sequence storage register (ISQ). Then, “−1” is performed. That is, when the interrupt processing for the interrupt input with the highest priority “1” is completed, the priority is “0”, the priority is “2”, the priority is “1”, and the priority is “3”. Is updated to “2” and “4”, and the priority is updated to “3”.

  Reference numeral 4 denotes an in-service register (ISR), which is the same as that described with reference to FIG. 4, and when the value corresponding to the interrupt inputs IR0 to IR3 is “1”, the current CPU processes the interrupt input. Indicates that

  The control circuit 5 is the same as that described with reference to FIG. 4, and outputs an interrupt request (INT) to the CPU, accepts an interrupt permission (INTA inversion) from the CPU, and completes an interrupt from the CPU (EOI). ) To control the interrupt request register 1, the generation order storage circuit 3, and the in-service register 4.

  Hereinafter, a specific example will be described with reference to FIG. Here, it is assumed that the interrupt inputs IR0 to IR3 all have the same priority. In FIG. 3, IRR indicates the flag (binary value) of the register of the interrupt request register 1, and ISQ indicates the contents (decimal number) of the generation order storage register of the generation order storage circuit 3. FIG. 3A shows a case where an interrupt request has not yet been made after the system reset is released.

  When an interrupt request is generated at the interrupt input IR2, the output corresponding to IR2 is "1" in the interrupt request register 1 (IRR) as shown in FIG. In response to this, a “1” pulse rises at the output corresponding to IR2 of the IRR rising edge detection circuit 2, and the output of the generation order storage register (ISQ) corresponding to IR2 becomes “ 1 ”is set.

  Subsequently, when an interrupt request is generated at the interrupt input IR3, as shown in FIG. 3 (d), the interrupt request register 1 (IRR) outputs "1" corresponding to IR3. This is detected by the IRR rising edge detection circuit 2, and the output corresponding to IR3 of the generation order storage register (ISQ) is set to a rank of “2”.

  Subsequently, when interrupt requests are sequentially generated in the interrupt inputs IR1 and IR0, as shown in FIG. 3E, the interrupt request register 1 (IRR) outputs "1" corresponding to IR1 and IR0. This is detected by the IRR rising edge detection circuit 2, and the outputs corresponding to IR1 and IR0 of the generation order storage register (ISQ) are set in the order of “3” and “4”, respectively.

  Thereafter, when an interrupt request (INT) from the control circuit 5 to the CPU is received by the CPU, an interrupt permission (INTA inversion) is input from the CPU, and an interrupt process corresponding to the interrupt input IR2 is started. As shown in FIG. 3 (f), the flag of the output IRA2 corresponding to IR2 of the interrupt request register 1 (IRR) is cleared from “1” to “0”. This makes it possible to re-accept the interrupt request to IR2.

  When the interrupt processing corresponding to the interrupt input IR2 is completed and the control circuit 5 receives the interrupt processing completion (EOI) issued by the CPU, the control circuit 5 corresponds to IR2 of the generation order storage register (ISQ). The value is cleared to “0”. At the same time, the other output of the generation order storage register (ISQ) is updated to "-1" as shown in FIG. 3 (g). That is, the stored contents are updated so that the priority order is incremented one by one for the remaining interrupt inputs for which there has been an interrupt request. As a result, the next request to receive the interrupt service is an interrupt request to the interrupt input IR3 in which the value of the generation order storage register (ISQ) is “1”. Similarly, by requesting the CPU to perform interrupt processing corresponding to the interrupt input whose value of the occurrence order storage register (ISQ) is “1”, and updating the storage contents of the occurrence order storage register (ISQ) Interrupt processing can be executed in the order in which interrupt requests are generated.

It is a block diagram which shows the structure of the interrupt processing circuit of the Example of this invention. It is a specific circuit diagram of an IRR rising edge detection circuit. It is explanatory drawing of the interruption process of a present Example. It is a block diagram which shows the structure of the conventional interrupt processing circuit. It is explanatory drawing of the conventional interruption process.

Explanation of symbols

1: Interrupt request register 2: IRR rising edge detection circuit 3: Generation order storage circuit 4: In-service register 5: Control circuit 6: Priority assignment circuit

Claims (3)

An interrupt processing circuit that requests an interrupt process according to the interrupt input to the CPU according to the order of generation of the interrupt request when there is an interrupt request to a plurality of interrupt inputs having the same priority,
For each of the plurality of interrupt inputs, it comprises generation order storage means for allocating and storing priorities according to the generation order of the interrupt requests,
The generation order storage means requests the CPU to perform interrupt processing for the highest-priority interrupt input, and each time the interrupt processing for the highest-priority interrupt input is completed, the remaining interrupt input for which an interrupt request has been made The interrupt processing circuit is characterized in that the stored contents are updated so as to increment the priorities one by one. The interrupt processing circuit according to claim 1,
An interrupt request accepting means that individually sets a flag for an interrupt input having an interrupt request, resets the flag for an interrupt input for which interrupt processing has been completed, and does not accept a new interrupt request for an interrupt input having a flag. Prepared,
The occurrence order storage means assigns a priority to the specific interrupt input by referring to the number of flags currently set in the interrupt request reception means when there is a new interrupt request for the specific interrupt input. An interrupt processing circuit. The interrupt processing circuit according to claim 2,
Rising edge detection means for detecting the rising edge of the flag of the interrupt request receiving means is provided, and the generation order storage means knows a new interrupt request for the specific interrupt input by a detection output of the rising edge detection means. An interrupt processing circuit.

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