JP2007305855A - Semiconductor integrated circuit and method of evaluating pressure resistance of semiconductor circuit trench - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for allowing easy evaluation of insulation pressure resistance when a multiple trench structure is employed. <P>SOLUTION: The semiconductor integrated circuit comprises an FET 22 disposed between a trench field region 14 located between double trenches 12, 13 that encircle a device 3 and a field region 11. If, after the FET 22 is brought into an OFF state and the pressure resistance of the trenches 12, 13 is evaluated, a power VCC is supplied to a semiconductor circuit 21 by connecting a pad 9(2) connected to the field region 14 to a pin 7(1), then the FET 22 is caused to turn on and the field regions 11, 14 are set to a field ground potential FG. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention is a semiconductor integrated circuit employing a structure in which an element forming region on an SOI (Silicon On Insulator) substrate is insulated and separated by multiple trenches, and a structure capable of easily evaluating a withstand voltage, The present invention relates to a trench breakdown voltage evaluation method for a semiconductor integrated circuit.

Patent Document 1 discloses a method for evaluating whether or not the withstand voltage of a trench structure portion is secured for a semiconductor device employing a trench isolation structure. Here, FIG. 6 shows a case where the technique of Patent Document 1 is applied to a semiconductor integrated circuit employing a double trench structure in a part of the element formation region. Although the semiconductor integrated circuit 1 does not show a cross-sectional view, the devices 3 to 6 are formed on the SOI substrate 2, and these devices 3 to 6 are all formed in regions separated by trenches.
Of these, the device 3 is an element that handles a relatively large amount of power, such as a power MOSFET, and is formed in a region adopting a double trench structure in order to ensure a high withstand voltage. When the trench structure is multiplexed in this way, it is possible to improve the withstand voltage, for example, about several hundred volts. A pad (lead frame) 7 serving as an external terminal and a pad 9 for connection by a bonding wire 8 are disposed on the outer peripheral portion of the substrate 2. A wiring 10 is provided on 2.

A field region 11 to be a background of each element formation region in the substrate 2 and to which a field ground potential FG is applied during the operation of the semiconductor integrated circuit 1 is connected to the pad 9 (1). The formation region of the device 3 is surrounded by two trenches 12 and 13 on the outer peripheral side and the inner peripheral side, respectively. The “trench” mentioned here is actually constituted by filling an insulating material such as SiO ₂ in the trench groove formed so as to reach the insulating layer from the surface of the substrate 2.
These trenches 12 and 13 are surrounded by an inter-trench field region 14 sandwiched between the two trenches 12 and 13 and the inner peripheral trench 13 in order to evaluate whether or not the necessary withstand voltage is secured. The field region 15 in the element formation region is connected to the pads 9 (1) and 9 (3), respectively. For the other devices 4 to 6, the ground region in each device is commonly connected via the wiring 10 (7), and they are collectively connected to the pad 9 (4). Since the SOI substrate structure and the trench isolation structure itself are well-known techniques, the details thereof are omitted.

In the above configuration, when the dielectric strength of each trench is evaluated before wire bonding, the single trenches 16 to 18 in the devices 4 to 6 are between the pads 9 (1) and 9 (3). Evaluate all at once by applying voltage. On the other hand, when evaluating the withstand voltage of the outer trench 12 in the region where the device 3 is formed, a voltage is applied between the pads 9 (1) and 9 (2) to evaluate the withstand voltage of the inner trench 13. In the case of evaluation, a voltage is applied between the pads 9 (2) and 9 (3) for evaluation.
JP-A-8-83830

However, after the dielectric breakdown voltage is evaluated as described above, both the field region 11 and the inter-trench field region 14 are set to the field ground potential, so that the pads 9 (1) and 9 (2) It is necessary to perform wire bonding so that the pin 7 (1): common to the FG is connected (the field ground potential is not necessarily set to the same potential as the ground potential: GND). .
That is, when the device 3 includes only a single trench (for example, the inner peripheral trench 13) as in the other devices 4 to 6, the pad 9 (2) is unnecessary. On the other hand, when the trench structure is multiplexed, the number of times of wire bonding increases accordingly.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit capable of easily evaluating withstand voltage when a multi-trench structure is employed, and the semiconductor integrated circuit. It is to provide a trench breakdown voltage evaluation method.

According to the semiconductor integrated circuit of claim 1, a transistor is provided between a field region arranged around the element formation region and an inter-trench field region surrounded by a trench located at the outermost periphery of the multiple trench, The transistor is formed so as to be conductive when an operation power supply is turned on to the semiconductor integrated circuit. That is, when evaluating the withstand voltage of a trench located on the outermost periphery of the element formation region (outermost periphery trench), a voltage is applied between the two field regions while the transistor is in a non-conductive state. Just do it.
When the power supply for operation is turned on to the semiconductor integrated circuit, the transistor is turned on so that the field region around the formation region and the field region between trenches have the same potential. Therefore, if only one of the field regions is wire-bonded and connected to the external terminal, both can be set to the field ground potential, so that an increase in the number of wire bondings can be suppressed.

  According to the semiconductor integrated circuit of claim 2, when the multiple trenches are composed of triple or more, the field region and the inter-trench field region located on the inner peripheral side by one from the outermost inter-trench field region are provided. Connect in common. If comprised in this way, it can evaluate simultaneously withstand voltage of the outermost periphery trench and the trench located in the one inner periphery side similarly to Claim 1.

  According to the semiconductor integrated circuit of claim 3, when the multiple trench is formed of four or more layers, the inter-trench field region located on the inner peripheral side, and the inter-trench field region located further on the inner peripheral side, Are connected in common to one measure, and the field region between the outermost peripheral trenches and the field region between trenches located on the inner peripheral side thereof are connected in common to one measure. If comprised in this way, it can evaluate simultaneously the withstand voltage of all the trenches except the thing arrange | positioned in innermost periphery similarly to Claim 1,2.

  5. The semiconductor integrated circuit according to claim 4, wherein when the transistor is a MOSFET, the transistor formation region has a double trench structure, and the inter-trench field region in the region is the outermost inter-trench field region of the element formation region. Connect to. That is, since the substrate potential of the MOSFET is connected so as to be the same potential as that of the source, with the above configuration, the breakdown voltage evaluation of the outer peripheral side and inner peripheral side trenches of the transistor formation region can be performed simultaneously.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. Note that the same parts as those in FIG. 6 are denoted by the same reference numerals, description thereof is omitted, and different parts will be described below. In the semiconductor integrated circuit 21 of this embodiment, an N-channel MNOSFET (transistor) 22 is arranged between pads 9 (1) and 9 (2) with respect to the semiconductor integrated circuit 1 shown in FIG. The source and drain of the FET 22 are connected to the pads 9 (1) and 9 (2) via the wirings 10 (1) and 10 (2), respectively, and the gate operates from the outside with respect to the semiconductor integrated circuit 21. The power supply VCC is connected to the pad 9 (6) via the wiring 10 (6).

  FIG. 2 shows the FET 22 in a state close to a semiconductor actual configuration. The FET 22 is formed in a region separated by a single trench 23 as in the devices 4 to 6 (complicated). In order to avoid this, some of the symbols are omitted). Note that the wirings shown to intersect each other are actually multilayer wirings. 1 and 2 show a state in which wire bonding is performed between the pad 9 and the pin 7, but only the pad 9 (2) is connected to the pin 7 (1). No wire bonding is performed for 9 (1).

  Next, the operation of this embodiment, that is, a method of evaluating the dielectric strength of the double trenches 12 and 13 surrounding the device 3 before wire bonding to the semiconductor integrated circuit 21 will be described. First, the FET 22 is turned off by setting the pad 9 (6) to the ground potential. In this state, a voltage is applied between the pads 9 (2) and 9 (3) for the inner trench 13 and the pads 9 (1) and 9 (2) for the outer trench 12 are applied. The withstand voltage is evaluated by applying a voltage between them.

  After performing the breakdown voltage evaluation as described above, if wire bonding is performed on the semiconductor integrated circuit 21 as shown in FIG. 1, the pad 9 (6) is connected to the pad 9 (6) via the pin 7 (5) when the semiconductor integrated circuit 21 is operated. Since the power supply VCC is supplied from the outside, the gate potential becomes high level and the FET 22 is turned on. Accordingly, the field region 11 of the semiconductor integrated circuit 21 is set to the same potential FG as the inter-trench field region 14 via the FET 22 by applying the field ground potential FG to the pin 7 (1).

  As described above, according to the present embodiment, the field region 11 and the inter-trench field region 14 located between the double trenches 12 and 13 surrounding the device 3 are made conductive when the operation power supply VCC is turned on. The FET 22 is disposed in the first, and the FET 22 is turned off to evaluate the withstand voltage of the trenches 12 and 13. After that, if the pad 9 (2) connected to the inter-trench field region 14 is connected to the pin 7 (1) and the power supply VCC is supplied to the semiconductor integrated circuit 21, the FET 22 is turned on to turn on the field regions 11, 14 Can be set to the field ground potential FG. Accordingly, it is possible to suppress an increase in the number of times that wire bonding is performed on the semiconductor integrated circuit 21.

(Second embodiment)
3 and 4 show a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted. Hereinafter, different parts will be described. In the semiconductor integrated circuit 24 of the second embodiment, the formation region of the FET 22 has a double trench structure similar to that of the device 3. That is, the trench 25 is formed on the outer peripheral side of the trench 23, and a region sandwiched between both is an inter-trench field region 26. The field region 26 is connected to the pad 9 (2) together with the drain of the FET 22, and is connected to the inter-trench field region 14 on the device 3 side. FIG. 4 schematically shows the cross-sectional structure of the region where the FET 22 is formed (however, the gate portion is not shown).

  Next, the operation of the second embodiment will be described. In the second embodiment, it is possible to evaluate the withstand voltage of the trenches 23 and 25 by forming the FET 22 in the double trench structure. That is, as in the case of evaluating the outer peripheral side trench 12 of the device 3 described in the first embodiment, the pads 9 (1) and 9 (2) with the FET 22 turned off before wire bonding is performed. A voltage is applied between them. Then, a voltage is applied between the field region 11 and the substrate SUB (back gate) of the FET 22 and the field region 26.

  Thereby, the withstand voltage of the outer peripheral side trench 25 separating the field regions 11 and 26 can be evaluated. Further, since the semiconductor composition of the substrate SUB of the FET 22 is substantially the same as that of the field region 11, the withstand voltage can be simultaneously evaluated for the inner peripheral trench 23 that separates the substrate SUB and the field region 26. For example, in the case of a single trench structure including only the trench 23 as in the first embodiment, the breakdown voltage cannot be evaluated for the trench 23 because the field region 11 and the substrate SUB are connected.

  As described above, according to the second embodiment, the FET 22 formation region has a double trench structure, and the inter-trench field region 26 in the region is connected to the inter-trench field region 14 in the device 3 formation region. The breakdown voltage evaluation of the outer peripheral side and inner peripheral side trenches 23 and 25 on the FET 22 side can be performed simultaneously.

(Third embodiment)
FIG. 5 shows a third embodiment of the present invention, and different parts from the second embodiment will be described. In the semiconductor integrated circuit 27 of the third embodiment, the formation region of the device 3 has a triple trench structure, and a trench 28 is formed on the outer peripheral side of the trench 12. The portion sandwiched between the two is an inter-trench field region 29.
In this case, the inter-trench field region 14 on the inner peripheral side is connected to the pad 9 (1) together with the field region 11 (FG1), and the inter-trench field region 29 on the outer peripheral side is connected to the field region 26 ( It is connected to the pad 9 (2) together with FG2).

Next, the operation of the third embodiment will be described. As in the first and second embodiments, the FET 22 is turned off, and the withstand voltage of the innermost trench 13 is evaluated by applying a voltage between the pads 9 (1) and 9 (3). With respect to the trench 12 and the outermost periphery trench 28, the voltage resistance can be simultaneously evaluated by applying a voltage between the pads 9 (1) and 9 (2).
As described above, according to the third embodiment, when the formation region of the device 3 adopts the triple trench structure, between the field region 11 and the trench located on the inner peripheral side from the outermost inter-trench field region 29. Since the field region 14 is commonly connected, it is possible to simultaneously evaluate the withstand voltage of the outermost peripheral trench 28 and one of the trenches 12 located on the inner peripheral side.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
The present invention may be applied to a quadruple or more multiple trench structure. For example, in the case of a quadruple trench structure, the configuration of the third embodiment may be expanded so that the connection is made so that the inter-trench field region which is the innermost periphery is FG2. That is, if the field region 11 is FG1, the inter-trench field region formed by the multiple trenches is connected to each other so as to become FG2, FG1, FG2,. Just do it. With this configuration, the dielectric strength of all trenches except those arranged on the innermost periphery can be evaluated simultaneously as in the third embodiment.

The transistor may be a P-channel MOSFET or a bipolar transistor.
The element formed by the multiple trench structure may be, for example, a power transistor or an IGBT.
Two or more elements formed by the multiple trench structure may be arranged on one semiconductor substrate.
The field ground potential FG is not limited to the ground potential. A potential that is turned on when the semiconductor integrated circuit operates when power is turned on may be appropriately applied to the transistor according to the type of the element, the level of the field ground potential FG, and the like.

The top view which is 1st Example of this invention and shows the layout of a semiconductor integrated circuit roughly 1 equivalent diagram showing the configuration of the FET more realistically FIG. 1 equivalent view showing a second embodiment of the present invention The figure which shows typically the cross-sectional structure of the area | region part in which FET is formed FIG. 3 equivalent view showing a third embodiment of the present invention. 1 equivalent diagram showing the prior art

Explanation of symbols

  In the drawing, 11 is a field region, 12 and 13 are trenches, 14 is a field region between trenches, 21 is a semiconductor integrated circuit, 22 is an N-channel MNOSFET (transistor), 23 is a trench, 24 is a semiconductor integrated circuit, 25 is a trench, 26 is a field region between trenches, 27 is a semiconductor integrated circuit, 28 is a trench, and 29 is a field region between trenches.

Claims (8)

In a semiconductor integrated circuit adopting a structure in which at least one element formation region on an SOI (Silicon On Insulator) substrate is insulated and separated by multiple trenches,
Transistor arranged to conduct between the field region between trenches surrounded by the trench located at the outermost periphery of the multiple trenches and the field region arranged around the element formation region when operating power is turned on A semiconductor integrated circuit comprising: When the multiple trench is composed of more than triple,
2. The semiconductor integrated circuit according to claim 1, wherein the field region and the inter-trench field region located one inner peripheral side from the outermost inter-trench field region are connected in common. When the multiple trench is composed of four or more layers,
The inter-trench field region located on the inner peripheral side and the inter-trench field region located further on the inner peripheral side are commonly connected in one measure,
3. The semiconductor integrated circuit according to claim 2, wherein the field region between the outermost peripheral trenches and the field region between the trenches located on the inner peripheral side thereof are commonly connected in one measure. When the transistor is configured as a MOSFET, the region for forming the transistor has a double trench structure,
4. The semiconductor integrated circuit according to claim 1, wherein a field region between trenches in the transistor formation region is connected to a field region between outermost trenches in the element formation region. In a method for evaluating the withstand voltage of a trench portion of a semiconductor integrated circuit adopting a structure in which at least one element forming region on an SOI (Silicon On Insulator) substrate is insulated and separated by multiple trenches,
A transistor is disposed in advance between an inter-trench field region surrounded by a trench located on the outermost periphery of the multiple trench and a field region disposed around the element formation region,
A method for evaluating the withstand voltage of a semiconductor integrated circuit, wherein the withstand voltage of the outermost periphery trench is evaluated by applying a voltage between the two field regions while the transistor is turned off. When the multiple trench is composed of more than triple,
The field region and the inter-trench field region located on the inner peripheral side of the outermost inter-trench field region are commonly connected in advance,
6. The trench breakdown voltage evaluation method for a semiconductor integrated circuit according to claim 5, wherein the transistor is made non-conductive, and an evaluation voltage is applied between the field region and the field region between the outermost peripheral trenches. When the multiple trench is composed of four or more layers,
The inter-trench field region located on the inner peripheral side and the inter-trench field region located further on the inner peripheral side are connected in common to one measure,
7. The trench breakdown voltage evaluation method for a semiconductor integrated circuit according to claim 6, wherein the field region between the outermost peripheral trenches and the field region between the trenches located on the inner peripheral side thereof are connected in common with one measure. . When the transistor is a MOSFET, the region where the transistor is formed has a double trench structure,
The trench breakdown voltage of the semiconductor integrated circuit according to claim 5, wherein a field region between trenches in the transistor formation region is connected to a field region between outermost trenches in the element formation region. Evaluation methods.

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