JP7117260B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device and its manufacturing method, and can be suitably applied to, for example, a semiconductor device having a power MOSFET and its manufacturing method.

When a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is turned off, the source-drain voltage rises and exceeds the breakdown voltage, resulting in a large loss. A snubber circuit is provided between the source and the drain to reduce this loss.

Japanese Patent Application Laid-Open No. 2017-163107 (Patent Document 1) discloses a power MOSFET with a built-in snubber circuit, and an additional capacitance C1 (corresponding to snubber capacitance Csnu of the snubber circuit, which will be described later) is provided in the element region ER. It is formed between the first conductive film FCL and the second conductive film SCL.

JP 2017-163107 A

The inventor of the present application performs a screening process to ensure the reliability of the snubber capacitor, but the screening process must be performed before the snubber capacitor is connected between the source and drain of the power MOSFET. This is because the screening voltage is applied to the snubber capacitance without being restricted by the breakdown voltage between the source and drain of the power MOSFET.

Although the details will be described later, in the semiconductor device under study by the inventors of the present application, bonding wires are used in the process of mounting the semiconductor chip in a package after performing a screening process on the semiconductor chip with a built-in snubber capacitor. , a snubber capacitor is connected between the source and the drain of the power MOSFET. As a result, it has been found that the connection area of the snubber capacitance is enlarged, and the performance of the power MOSFET is degraded.

In a semiconductor device in which a snubber capacitor and a power MOSFET are built in a semiconductor chip, it is desired to improve the reliability of the snubber capacitor and the performance of the power MOSFET.

Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

A semiconductor device according to one embodiment has a power MOSFET and a snubber capacitor connected between its drain and source. 2 capacitive electrodes. The first capacitive electrode and the second capacitive electrode extend in the Y direction on the main surface of the semiconductor substrate and are connected at their ends to the first wiring and the second wiring extending in the X direction, respectively. . Furthermore, a first pad electrode is connected to the first wiring, and a second pad electrode is connected to the second wiring. The first pad electrode is connected to the drain by a third wiring arranged on the first pad electrode, and the second capacitor electrode is connected to the source electrode arranged on the second capacitor electrode.

According to one embodiment, the performance of a semiconductor device can be improved.

2 is an equivalent circuit diagram of the semiconductor device of Embodiment 1; FIG. 1 is a plan perspective view of a semiconductor device in related art; FIG. 1 is a plan perspective view of the semiconductor device of Embodiment 1; FIG. 1 is a fragmentary cross-sectional view of a semiconductor chip according to a first embodiment; FIG. 5 is a cross-sectional view along line X0-X0 of FIG. 4; FIG. 5 is a cross-sectional view along line X1-X1 in FIG. 4; FIG. FIG. 5 is a cross-sectional view taken along line Y1-Y1 in FIG. 4; 1 is a fragmentary cross-sectional view of a semiconductor chip according to a first embodiment; FIG. FIG. 9 is a cross-sectional view along line X2-X2 of FIG. 8; FIG. 9 is a cross-sectional view along line Y2-Y2 of FIG. 8; 3 is a flow chart showing manufacturing steps of the semiconductor device of the first embodiment; FIG. FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment; FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment; FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment; FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment; FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment; FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment; FIG. 11 is a plan view of a main part of a semiconductor chip according to a second embodiment; FIG. 11 is a plan view of a main part of a semiconductor chip according to a second embodiment; FIG. 14 is a cross-sectional view showing a manufacturing process of the semiconductor device of Embodiment 2; FIG. 11 is a plan view of a main part of a semiconductor chip according to a third embodiment; FIG. 11 is a cross-sectional view of a main part of a semiconductor chip according to a third embodiment; FIG. 11 is a plan view of a main part of a semiconductor chip according to a fourth embodiment; FIG. 14 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment; FIG. 14 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment; FIG. 12 is a plan view of a main part of a semiconductor chip according to a fifth embodiment;

For the sake of convenience, the following embodiments are divided into a plurality of sections or embodiments when necessary, but unless otherwise specified, they are not independent of each other, and one There is a relationship of part or all of the modification, details, supplementary explanation, etc. In addition, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), when it is particularly specified, when it is clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., unless otherwise specified or in principle clearly considered otherwise, the shape is substantially the same. It shall include things that are similar or similar to, etc. This also applies to the above numerical values and ranges.

Hereinafter, embodiments will be described in detail based on the drawings. In addition, in all the drawings for explaining the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

In addition, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views in order to make the drawings easier to see. Also, even a plan view may be hatched to make the drawing easier to see.

(Embodiment 1)
The semiconductor device of Embodiment 1 includes a power MOSFET and a snubber capacitor formed on a semiconductor chip. A power MOSFET has a source, a drain and a gate, and a snubber circuit including a snubber capacitor is connected between the source and the drain of the power MOSFET. Here, a trench gate type MOSFET is used as an example of the power MOSFET for explanation, but the power MOSFET is not limited to the trench gate type.

FIG. 1 is an equivalent circuit diagram of the semiconductor device of Embodiment 1. FIG. As shown in FIG. 1, the power MOSFET 1 has a source S, a drain D and a gate G. The source S corresponds to the source electrode ES and the source region SR which will be described later, and the gate G corresponds to the gate electrode EG, the gate wiring WLG and the trench gate electrode GE which will be described later. Also, the drain D corresponds to a drain electrode ED, a drift region DR, and a substrate region SUBR, which will be described later. A snubber circuit composed of a snubber capacitance Csnu and a parasitic resistance Rsnu connected in series is connected between the source S and the drain D of the power MOSFET 1 . The snubber capacitance Csnu includes capacitance electrodes CE1 and CE2, the capacitance electrode CE1 is connected to the drain D, and the capacitance electrode CE2 is connected to the source S.

<Related technology>
First, a semiconductor device having a power MOSFET in related art will be described. A semiconductor device incorporates a snubber circuit. Here, the related technology is the technology examined by the inventor of the present application, and does not mean the known technology.

FIG. 2 is a plan perspective view of a semiconductor device SD0 in related art. Note that FIG. 2 does not show a snubber capacitor Csnu and capacitor electrodes CE1 and CE2, which will be described later. The semiconductor device SD0 includes a semiconductor chip CHP0, and the power MOSFET 1 and snubber capacitance Csnu shown in FIG. 1 are formed in the cell formation region CFR of the semiconductor chip CHP0. Although not shown, the capacitance electrodes CE1 and CE2 forming the snubber capacitance Csnu are arranged in the cell formation region CFR, and the capacitance electrode CE1 is connected to the pad electrode SNP1 arranged in the drain connection region R1. . Also, the capacitance electrode CE2 is connected to the source electrode ES. A pad electrode SNP1 and a drain pad electrode EDP connected to the drain of the power MOSFET 1 are provided in the drain connection region R1. The drain connection region R1 is a region for connecting the capacitive electrode CE1 to the drain of the power MOSFET1.

The pad electrode SNP1, the source electrode ES and the drain pad electrode EDP are covered with a protective film PRO, and the protective film PRO is provided with pad openings OPSN, OPS and OPD. Pad electrode SNP1, source electrode ES and drain pad electrode EDP have regions exposed from pad openings OPSN, OPS and OPD.

In the snubber capacitance Csnu screening process, a test terminal TND, which will be described later, is applied to the pad electrode SNP1 and the source electrode ES, and a screening voltage is applied between the capacitance electrodes CE1 and CE2. Then, the semiconductor chip SD0 is sorted into a non-defective product or a defective product. Next, as shown in FIG. 2, a wire bonding process is performed on the non-defective semiconductor chip CHP0. In a wire bonding process, the pad electrode SNP1 and the drain pad electrode EDP are connected with a bonding wire BWd. Through this wire bonding process, the capacitance electrode CE1 of the snubber capacitance Csnu is connected to the drain of the power MOSFET1. In other words, the snubber capacitance Csnu is connected between the drain and source of the power MOSFET1.

In other words, the pad electrode SNP1 to which the capacitance electrode CE1 is connected must be of a size sufficient for contacting the test terminal TND in the screening process and for connecting the bonding wire BWd in the wire bonding process. The size of the pad electrode SNP1 required in the wire bonding process is much larger than the size of the pad electrode SNP1 required in the screening process. In the wire bonding process, for example, if the wire diameter of the bonding wire BWd is 75 μm, the size of the pad electrode SNP1 is approximately 300 μm×300 μm. Incidentally, the tip diameter of the test terminal TND is about 10 μm, and the size of the pad electrode SNP1 required in the screening process is about 50 μm×50 μm.

The drain pad electrode EDP arranged in the drain connection region R1 also has the same size as the pad electrode SNP1. In order to connect the pad electrode SNP1 and the drain pad electrode EDP with the bonding wire BWd, it is necessary to provide a desired space between the pad electrode SNP1 and the drain pad DP. Therefore, a region of approximately 300 μm×900 μm is required as the drain connection region R1.

Therefore, in the main surface of the semiconductor chip CHP0, the occupancy of the drain connection region R1 increases, and the occupancy of the source electrode ES of the power MOSFET1 decreases. That is, the on-resistance of the power MOSFET 1 increases and the performance of the semiconductor device SD0 deteriorates.

According to the studies of the inventors, it has been found that there is room for improvement in the related technology semiconductor device SD0. This room for improvement is described below.

<Structure of semiconductor device>
FIG. 3 is a plan perspective view of the semiconductor device SD1 of the first embodiment. FIG. 3 does not show a snubber capacitor Csnu and capacitor electrodes CE1 and CE2, which will be described later. The semiconductor device SD1 includes a semiconductor chip CHP1, a sealing body MR that seals the semiconductor chip CHP1, and a drain terminal DT, a source terminal ST, and a gate terminal GT, which are external terminals of the semiconductor device SD1. The drain terminal DT is integrated with the die pad DIP on which the semiconductor chip CHP1 is mounted.

In the main surface of the semiconductor chip CHP1, a cell formation region CFR is provided in the central portion thereof, and a peripheral region PER is provided around the cell formation region CFR. Connection regions CR1 and CR2, a drain connection region R2, and a source connection region R3 are provided in the peripheral region PER. A gate electrode EG and a gate wiring WLG connected to the gate electrode EG are provided in the peripheral region PER.

The gate wiring WLG extends annularly along the outer periphery of the semiconductor chip CHP1 and surrounds the cell formation region CFR, the coupling regions CR1 and CR2, the drain connection region R2, and the source connection region R3.

The gate electrode EG is covered with the protective film PRO, and the region exposed from the pad opening OPG provided in the protective film PRO is the gate pad GP. Gate pad GP is connected to gate terminal GT via wire BWg.

A power MOSFET 1 and a snubber capacitor Csnu are formed in the cell formation region CFR, and the power MOSFET 1 has a source S, a drain D, and a gate G, as shown in FIG. Capacitance electrodes CE1 and CE2 forming snubber capacitance Csnu are arranged in cell formation region CFR. A source electrode ES connected to the source S is provided in the cell formation region CFR so as to cover the power MOSFET 1 and the capacitance electrodes CE1 and CE2. The capacitance electrode CE2 is connected to the source electrode ES. The source electrode ES is covered with the protective film PRO, and the region exposed from the pad opening OPS provided in the protective film PRO is the source pad SP. The source pad SP is connected to the source terminal ST via multiple wires BWs.

Also, the gate G of the power MOSFET 1 is connected to the gate wiring WLG, and is connected to the gate terminal GT via the gate pad GP and the wire BWg. The drain D of the power MOSFET 1 corresponds to the back surface of the semiconductor chip CHP1 and is connected to the drain terminal DT via the die pad DIP.

The drain connection region R2 is a region for connecting the capacitance electrode CE1 to the drain D of the power MOSFET1. The drain connection region R1 includes a pad electrode SNP1 connected to the capacitance electrode CE1, a conductor layer CP3 connected to the drain D of the power MOSFET 1, and a snubber wiring ESN1 connecting the pad electrode SNP1 and the conductor layer CP3. In the first embodiment, the snubber wiring ESN1 is used to connect the capacitance electrode CE1 of the snubber capacitance Csnu to the drain of the power MOSFET1. In other words, the snubber capacitance Csnu is connected between the drain and source of the power MOSFET1.

The source connection region R3 includes a pad electrode SNP2 connected to the capacitance electrode CE2 and a snubber wire ESN2 connected to the pad electrode SNP2.

The areas of the drain connection region R2 and the source connection region R3 are reduced compared to the area of the drain connection region R1 of the comparative example. This is because there is no need to connect bonding wires to the pad electrode SNP1 and conductor layer CP3 arranged in the drain connection region R2 and the pad electrode SNP2 arranged in the source connection region R3. In the screening process, the test terminals TND are brought into contact with the pad electrodes SNP1 and SNP2. Therefore, the size of the pad electrodes SNP1 and SNP2 should be sufficient to contact the test terminal TND. Since the conductor layer CP3 is not in contact with the test terminal TND, it can be much smaller than the pad electrodes SNP1 and SNP2. For example, the size of the drain connection region R2 can be about 60 μm×70 μm, and the size of the source connection region R3 can be about 60 μm×60 μm. The areas of the drain connection region R2 and the source connection region R3 are 1/30 or less of the drain connection region R1 of the comparative example.

Therefore, in the semiconductor chip CHP1, compared with the semiconductor chip CHP0 of the comparative example, the occupation ratio of the cell formation region CFR (in other words, the source electrode ES) can be improved, and the on-resistance of the power MOSFET1 can be reduced.

FIG. 4 is a fragmentary cross-sectional view of the semiconductor chip CHP1 of the first embodiment. FIG. 4 shows patterns of conductor layers (conductor layers CP1, CP2 and CP3, source electrode ES, snubber wiring ESN1, and gate wiring WLG) formed on the semiconductor substrate. 5 is a cross-sectional view along line X0-X0 in FIG. 4, FIG. 6 is a cross-sectional view along line X1-X1 in FIG. 4, and FIG. 7 is a cross-sectional view along line Y1-Y1 in FIG. Note that FIGS. 6 and 7 show the protective film PRO, which is not shown in FIG.

As shown in FIG. 4, a plurality of trench gate electrodes GE, a plurality of capacitance electrodes CE1 and CE2, a plurality of conductor layers CP1 and CP3, and a source electrode ES are formed in the cell formation region CFR. The plurality of trench gate electrodes GE and the plurality of capacitor electrodes CE1 extend in the Y direction and are arranged at regular intervals in the X direction. The capacitance electrode CE1 is arranged on and overlapping the trench gate electrode GE. For example, the width of the capacitance electrode CE1 is narrower than the width of the trench gate electrode GE in the X direction. The Y direction is a direction crossing the X direction, for example, a direction orthogonal to the X direction.

Between adjacent trench gate electrodes GE, a laminated structure including a conductor layer CP1, a capacitor electrode CE2 (in other words, a conductor layer CP2) and a conductor layer CP3 is arranged. The stacked structures extend in the Y direction and are arranged at regular intervals in the X direction. The capacitive electrode CE2 (in other words, the conductor layer CP2) is arranged on top of the conductor layer CP1 so as to overlap the conductor layer CP1. greater than Further, the conductor layer CP3 is arranged on the capacitance electrode CE2 so as to overlap with the capacitance electrode CE2, and the size of the conductor layer CP3 is larger than the size of the capacitance electrode CE2 in the X direction and the Y direction. A source electrode ES is formed in the cell formation region CFR so as to cover the plurality of capacitance electrodes CE1 and CE2. The source electrode ES is connected to the capacitor electrode CE2 via the conductor layer CP3.

A coupling wiring WLC1 extending in the X direction is arranged in the coupling region CR1, which is a part of the peripheral region PER, and the plurality of capacitor electrodes CE1 are connected to each other by the coupling wiring WLC1.

A pad electrode (snubber pad electrode) SNP1, a conductor layer CP3 connected to the drain D of the power MOSFET 1, and a snubber wire ESN1 are arranged in the drain connection region R2, which is a part of the peripheral region PER. A coupling wiring WLC1 arranged in the coupling region CR1 extends to the drain connection region R2 and is connected to the pad electrode SNP1. The pad electrode SNP1 and the conductor layer CP3 connected to the drain D of the power MOSFET 1 are connected by a snubber wiring ESN1 formed thereon.

Further, as described above, the gate wiring WLG is provided in the peripheral region PER. In the cell formation region CFR, the trench gate electrode GE extending in the Y direction is connected to the gate wiring WLG via the conductor layers CP1, CP2 and CP3 in the peripheral region PER.

Power MOSFET 1 will be described with reference to FIGS. 4 and 5. FIG. As shown in FIG. 5, the semiconductor substrate SUB has a substrate region (n-type semiconductor region) SUBR and a drift region (n-type semiconductor region) DR on the substrate region SUBR. The concentration of n-type impurities in substrate region SUBR is higher than the concentration of n-type impurities in drift region DR.

In cell formation region CFR, body region (p-type semiconductor region, channel layer, base region) BR is formed over drift region DR, and source region (n-type semiconductor region) SR is formed over body region BR. Drift region DR reaches main surface SUBa of semiconductor substrate SUB, and body region BR and source region SR are formed in drift region DR. The concentration of n-type impurities in source region SR is higher than the concentration of n-type impurities in drift region DR. A body contact region (p-type semiconductor region) BCR is formed in the body region BR, and the p-type impurity concentration of the body contact region BCR is higher than the p-type impurity concentration of the body region BR.

A plurality of trenches TR are formed in the cell formation region CFR at equal intervals in the X direction, and each of the plurality of trenches TR extends in the Y direction (see FIG. 4). A trench gate electrode GE is formed inside each of the plurality of trenches TR with a gate insulating film GI interposed therebetween. The trench TR is filled with a trench gate electrode GE formed through the gate insulating film GI. The gate insulating film GI is composed of, for example, a silicon oxide film or a silicon oxynitride film, and the trench gate electrode GE is composed of, for example, a polycrystalline silicon film containing n-type impurities or p-type impurities. . In the direction from main surface SUBa to back surface SUBb, trench TR penetrates source region SR and body region BR and reaches drift region DR. In other words, the body region BR and the source region SR are arranged between two adjacent trenches TR, and the body region BR and the source region SR are in contact with the gate insulating film GI formed in the two adjacent trenches TR. there is

Substrate region SUBR and drift region DR correspond to drain D, source region SR to source S, and trench gate electrode GE to gate G of power MOSFET 1 shown in FIG. 1, respectively. When a predetermined voltage is applied to trench gate electrode GE, a channel is formed at the interface with gate insulating film GI in body region BR, and current flows between drift region DR and substrate region SUBR and source region SR.

The main surface SUBa of the semiconductor substrate SUB is covered with an insulating film (interlayer insulating film) ILD1. The trench gate electrode GE exposed on the main surface SUBa is also covered with the insulating film ILD1. A contact trench (contact hole, opening, wiring trench) CH1 is formed in the insulating film ILD1 and the semiconductor substrate SUB, and a conductor layer CP1 (wiring, contact plug) is embedded in the contact trench CH1. Contact trench CH1 penetrates source region SR and reaches body contact region (p-type semiconductor region) BCR formed in body region BR. Conductive layer CP1 is electrically connected to source region SR and body contact region BCR (in other words, body region BR). Although not shown, the conductor layer CP1 has a laminated structure of a barrier film and a main conductor film on the barrier film, the barrier film is made of a titanium nitride film or a titanium tungsten film, and the main conductor film is made of a tungsten film. .

A plurality of capacitance electrodes CE1 and a plurality of capacitance electrodes CE2 are arranged on the insulating film ILD1. The capacitive electrode CE2 is located above the source region SR and connected to the source region SR via the conductor layer CP1. The capacitance electrode CE1 is arranged above the trench gate electrode GE via the insulating film ILD1. That is, the capacitance electrode CE1 is insulated from the trench gate electrode GE. Each of the plurality of capacitance electrodes CE1 and CE2 extends in the Y direction and is alternately arranged in the X direction. An insulating film (interlayer insulating film) ILD2 is provided between the adjacent capacitance electrodes CE1 and CE2. That is, in the X direction, the insulating film ILD2 has a plurality of contact grooves (contact holes, openings, wiring grooves) CH2 arranged at regular intervals, and the capacitance electrodes CE1 or CE2 are embedded in the plurality of contact grooves CH2. ing. The capacitive electrodes CE1 and CE2 are surrounded by an insulating film ILD2 in plan view. The capacitive electrodes CE1 and CE2 have a laminated structure of a barrier film and a main conductor film on the barrier film, the barrier film being made of a titanium nitride film or a titanium tungsten film, and the main conductor film being made of a tungsten film. The capacitive electrodes CE1 and CE2 are composed of a conductor layer (wiring, contact plug) CP2.

An insulating film (interlayer insulating film) ILD3 is formed over the capacitive electrodes CE1 and CE2 and the insulating film ILD2 so as to cover the capacitive electrodes CE1 and CE2 and the insulating film ILD2. The insulating film ILD3 has a plurality of contact trenches (contact holes, openings, wiring trenches) CH3, and conductor layers (wirings, contact plugs) CP3 are embedded in the plurality of contact trenches CH3. The conductor layer CP3 is surrounded by an insulating film ILD3 in plan view. The conductor layer CP3 is arranged on the capacitive electrode CE2 and connected to the capacitive electrode CE2. As shown in FIG. 4, the conductor layer CP3 formed in the contact groove CH3 extends in the Y direction.

Here, the insulating films ILD1, ILD2, and ILD3 are composed of, for example, a silicon oxide film, a silicon nitride film, or a laminated film of a silicon nitride film and a silicon oxide film thereon.

A source electrode ES is formed over the conductor layer CP3 and the insulating film ILD3 so as to cover the conductor layer CP3 and the insulating film ILD3. The source electrode ES is connected to the plurality of conductor layers CP3 and covers the entire cell formation region CFR. The source electrode ES is made of an aluminum film or an aluminum alloy film, but may be a laminated film of a barrier film and a main conductor film on the barrier film. In the case of laminated films, the barrier film is made of a titanium nitride film or a titanium tungsten film, and the main conductor film is made of an aluminum film or an aluminum alloy film. Here, the aluminum alloy film contains aluminum and additives such as silicon, copper, or silicon and copper.

As shown in FIG. 5, the source electrode ES is electrically connected to the source region SR, the body contact region BCR and the body region BR via the conductor layer CP3, the capacitor electrode CE2 (the conductor layer CP2) and the conductor layer CP1. ing. That is, the capacitance electrode CE2, which is one electrode of the snubber capacitance Csnu, is connected to the source region SR and the source electrode ES. In other words, the capacitance electrode CE2, which is one electrode of the snubber capacitance Csnu, is connected to the source S of the power MOSFET1.

A drain electrode ED is formed on the back surface SUBb of the semiconductor substrate SUB, and the drain electrode ED is electrically connected to the substrate region SUBR and the drift region DR.

Note that the snubber capacitance Csnu shown in FIG. 1 includes a first capacitance formed of the capacitance electrodes CE1 and CE2, an insulating film ILD2 disposed between the capacitance electrodes CE1 and CE2, the capacitance electrode CE1 and the source electrode ES. , and an insulating film ILD3 arranged between the capacitor electrode CE1 and the source electrode ES. The first capacitor and the second capacitor are connected in parallel. Also, the parasitic resistance Rsnu corresponds to, for example, the resistance components of the capacitance electrodes CE1 and CE2 extending in the Y direction.

Next, a structure for connecting the capacitive electrode CE1 and the drain D of the power MOSFET 1 will be described with reference to FIGS. 4 and 6. FIG. As shown in FIG. 6, in the coupling region CR1, a coupling wiring WLC1 is formed over the main surface SUBa of the semiconductor substrate SUB with an insulating film ILD1 interposed therebetween. The capacitive electrode CE1 and the coupling wiring WLC1 are formed in a contact groove (contact hole, opening, wiring groove) CH2 provided in the insulating film ILD2 formed over the insulating film ILD1. The capacitance electrode CE1 and the coupling wiring WLC1 are formed of the conductor layer CP2, and the portion of the coupling wiring WLC1 located over the trench gate electrode GE serves as the capacitance electrode CE1.

The coupling wiring WLC1 extends from the coupling region CR1 to the drain connection region R2 and is connected to the pad electrode SNP1 at the drain connection region R2. The pad electrode SNP1 is formed in a contact groove CH3 provided in the insulating film ILD3 covering the coupling wiring WLC1 and the capacitor electrode CE1.

In the drain connection region R2, an n-type semiconductor region NR is provided in the drift region DR formed in the semiconductor substrate SUB. The n-type semiconductor region NR is connected to the drift region DR and substrate region SUBR. That is, the n-type semiconductor region NR is connected to the drain D of the power MOSFET 1 shown in FIG. A conductor layer CP3 is connected to the n-type semiconductor region NR via the conductor layers CP1 and CP2. A conductor layer CP3 connected to the n-type semiconductor region NR is formed in a contact groove (contact hole, opening, wiring groove) CH3 provided in the insulating film ILD3. A snubber wiring ESN1 is provided over the conductor layer CP3, the pad electrode SNP1, and the insulating film ILD3 connected to the n-type semiconductor region NR. and the pad electrode SNP1. In other words, the snubber wiring ESN1 connects the pad electrode SNP1 to the conductor layer CP3 connected to the n-type semiconductor region NR. That is, the snubber wiring ESN1 connects the capacitance electrode CE1 of the snubber capacitance Csnu to the drain D of the power MOSFET 1 (see FIG. 1). The snubber wire ESN1 has its entire main surface covered with a protective film PRO formed over the insulating film ILD3.

Next, the relationship between the capacitance electrode CE1 and the trench gate electrode GE and source electrode ES of the power MOSFET 1 will be described with reference to FIGS. 4 and 7. FIG. As shown in FIG. 7, in the cell formation region CFR, the capacitor electrode CE1 is arranged over the main surface SUBa of the semiconductor substrate SUB with the insulating film ILD1 interposed therebetween. The capacitive electrode CE1 extends from the cell formation region CFR to the peripheral region PER and is connected to the coupling wiring WLC1 in the coupling region CR1 which is part of the peripheral region PER. The capacitance electrode CE1 is arranged over the trench gate electrode GE formed in the semiconductor substrate SUB via the insulating film ILD1. The capacitance electrode CE1 is electrically isolated from the trench gate electrode GE by the insulating film ILD1. Also, in the cell formation region CFR, the source electrode ES is arranged over the capacitor electrode CE1 via the insulating film ILD3. The capacitance electrode CE1 is electrically separated from the source electrode ES by an insulating film ILD3. The source electrode ES is covered with the protective film PRO, but part of the source electrode ES is exposed from the pad opening OPS provided in the protective film PRO, and the exposed region serves as the source pad SP.

Also, in the peripheral region PER, the trench gate electrode GE formed in the semiconductor substrate SUB is connected to the gate wiring WLG via the conductor layers CP1, CP2 and CP3.

FIG. 8 is a fragmentary cross-sectional view of the semiconductor chip of the first embodiment. FIG. 8 shows patterns of conductor layers (conductor layers CP1, CP2 and CP3, source electrode ES, snubber wiring ESN2, and gate wiring WLG) formed on the semiconductor substrate. 9 is a cross-sectional view along line X2-X2 of FIG. 8, and FIG. 10 is a cross-sectional view along line Y2-Y2 of FIG. 9 and 10 show the protective film PRO, which is not shown in FIG.

First, the structure for connecting the capacitive electrode CE2 and the source S of the power MOSFET 1 will be described with reference to FIGS. 8 and 9. FIG. As shown in FIG. 8, in a connecting region CR2, which is a part of the peripheral region PER, a connecting wiring WLC2 extending in the X direction is arranged, and a plurality of capacitive electrodes CE2 connected to the source S of the power MOSFET 1 are connected to each other. , are connected to each other by a connecting wiring WLC2.

The coupling wiring WLC2 extends from the coupling region CR2 to the source connection region R3, and is connected to the pad electrode (snubber pad electrode) SNP2 in the source connection region R3. The pad electrode SNP2 is formed in a contact groove CH3 provided in the insulating film ILD3 covering the coupling wiring WLC2 and the capacitor electrode CE2. A snubber wiring ESN2 connected to the pad electrode SNP2 is formed in the source connection region R3. The snubber wiring ESN2 is formed integrally with the source electrode ES and is connected to the source electrode ES. That is, the pad electrode (snubber pad electrode) SNP2 is connected to the source electrode ES.

As shown in FIG. 9, in the coupling region CR2, a coupling wiring WLC2 is formed over the main surface SUBa of the semiconductor substrate SUB with an insulating film ILD1 interposed therebetween. The capacitive electrode CE2 and the coupling wiring WLC2 are formed in a contact groove (contact hole, opening, wiring groove) CH2 provided in the insulating film ILD2 formed over the insulating film ILD1. The capacitance electrode CE2 and the coupling wiring WLC2 are formed of the conductor layer CP2, and the portion of the coupling wiring WLC2 located between the trench gate electrodes GE serves as the capacitance electrode CE2.

The coupling wiring WLC2 extends from the coupling region CR2 to the source connection region R3, and is connected to the pad electrode SNP2 in the source connection region R3. The pad electrode SNP2 is formed in a contact groove CH3 provided in the insulating film ILD3 covering the coupling wiring WLC2 and the capacitor electrode CE2. On the insulating film ILD3, the source electrode ES is formed in the coupling region CR2, and the snubber wiring ESN2 is formed in the source connection region R3. As described above, since the snubber wiring ESN2 is connected to the source electrode ES, the pad electrode (snubber pad electrode) SNP2 is connected to the source electrode ES via the snubber wiring ESN2.

Next, the relationship between the capacitance electrode CE2 and the source S and the source electrode ES of the power MOSFET 1 in the cell formation region CFR will be described with reference to FIGS. 8 and 10. FIG. As shown in FIG. 10, in the cell formation region CFR, the source electrode ES is connected to the source region SR via the laminated structure including the conductor layer CP1, the capacitor electrode CE2 (in other words, the conductor layer CP2), and the conductor layer CP3. It is connected. That is, since the capacitance electrode CE2 and the source electrode ES are connected in the cell formation region CFR, in the source connection region R3 shown in FIGS. No need to connect to ES. In other words, in the source connection region R3, the pad electrode SNP2 connected to the capacitor electrode CE2 via the coupling wiring WLC2 is arranged, and the snubber wiring ESN2 is not necessarily formed.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing the semiconductor device of the first embodiment will be described with reference to FIGS. 11 to 17. FIGS. 11 is a flow chart showing the manufacturing process of the semiconductor device of the first embodiment, and FIGS. 12 to 17 are cross-sectional views showing the manufacturing process of the semiconductor device of the first embodiment. 12 to 17 show cross-sectional views of the cell formation region CFR, the drain connection region R2 and the source connection region R3.

First, as shown in FIG. 11, the method of manufacturing the semiconductor device according to the first embodiment includes a power MOSFET 1 forming step (step S1), a conductor layer CP1 forming step (step S2), and a capacitive electrodes CE1 and CE2 forming step (step S3 ), connecting wirings WLC1, WLC2 forming step (step S4), pad electrodes SNP1, SNP2 forming step (step S5), screening step (step S6), snubber wiring ESN1, source electrode ES forming step (step S7), protective film PRO It includes a forming step (step S8), a wire bonding step (step S9) and a sealing body MR forming step (step S10). In the following description, the cell formation region CFR, drain connection region R2 and source connection region R3 are simply referred to as region CFR, region R2 and region R3. Moreover, in particular, when the description is given without specifying the regions, it means that the same steps are performed for the regions CFR, the regions R2 and the regions R3.

FIG. 12 shows the step of forming the power MOSFET 1 (step S1) and the step of forming the conductor layer CP1 (step S2) in FIG. First, in the power MOSFET 1 forming step (step S1), the power MOSFET 1 is formed on the semiconductor substrate SUB in the region CFR. As shown in FIG. 1, the power MOSFET 1 has a source S, a drain D and a gate G. Further, as shown in FIG. 17, the source S corresponds to the source electrode ES and source region SR, the gate G corresponds to the trench gate electrode GE, and the drain D corresponds to the drift region DR and substrate region SUBR. ing. In addition, in the power MOSFET 1 forming step (step S1), the n-type semiconductor region NR is formed in the semiconductor substrate SUB in the region R2. The n-type semiconductor region NR is connected to the drift region DR and substrate region SUBR.

Next, in the conductor layer CP1 forming step (step S2), an insulating film ILD1 is formed over the main surface SUBa of the semiconductor substrate SUB. Next, in the regions CFR and R2, after forming the contact groove CH1 in the insulating film ILD1, the conductor layer CP1 is formed in the contact groove CH1. In region CFR, conductor layer CP1 is connected to source region SR and body contact region BCR. Furthermore, in the region R2, the conductor layer CP1 is connected to the n-type semiconductor region NR. After depositing the first conductor film on the insulating film ILD1 and in the contact trench CH1, the first conductor film is subjected to a polishing process called a CMP (Chemical Mechanical Polishing) method. Thus, the conductor layer CP1 is selectively formed in the contact trenches CH1.

FIG. 13 shows the step of forming capacitor electrodes CE1 and CE2 (step S3) and the step of forming coupling lines WLC1 and WLC2 (step S4) in FIG. An insulating film ILD2 is formed over the main surface SUBa of the semiconductor substrate SUB so as to cover the insulating film ILD1 and the conductor layer CP1. Next, after forming a plurality of contact trenches CH2 in the insulating film ILD2, a conductor layer CP2 is formed in the contact trenches CH2. After depositing the second conductor film on the insulating film ILD2 and in the contact trenches CH2, the second conductor film is subjected to CMP polishing. Thus, the conductor layer CP2 is selectively formed in the contact trenches CH2.

In region CFR, capacitance electrodes CE1 and CE2 formed of a conductor layer CP2 are formed. The capacitance electrode CE1 is formed above the trench gate electrode GE via the insulating film ILD1, and the capacitance electrode CE2 is formed in the region between the adjacent trench gate electrodes GE and connected to the source region SR via the conductor layer CP1. is doing.

In the region R2, a conductor layer CP2 connected to the n-type semiconductor region NR through the conductor layer CP1 and a coupling wiring WLC1 formed of the conductor layer CP2 are formed.

In the region R3, a coupling wiring WLC2 made of the conductor layer CP2 is formed.

In this example, the capacitance electrodes CE1 and CE2 and the coupling wirings WLC1 and WLC2 are formed in the same conductor layer CP2. can also be formed with

FIG. 14 shows the step of forming pad electrodes SNP1 and SNP2 (step S5) in FIG. An insulating film ILD3 is formed over the main surface SUBa of the semiconductor substrate SUB so as to cover the insulating film ILD2 and the conductor layer CP2. Next, after forming a plurality of contact trenches CH3 in the insulating film ILD3, a conductor layer CP3 is formed in the contact trenches CH3. After depositing the third conductor film on the insulating film ILD3 and in the contact trench CH3, the third conductor film is subjected to CMP polishing. Thus, the conductor layer CP3 is selectively formed in the contact trenches CH3.

In the region CFR, a conductor layer CP3 connected to the capacitance electrode CE2 is formed over the capacitance electrode CE2.

In the region R2, a conductor layer CP3 connected to the n-type semiconductor region NR through the conductor layers CP1 and CP2 and a pad electrode SNP1 connected to the coupling wiring WLC1 are formed.

In region R3, pad electrode SNP2 connected to coupling line WLC2 is formed.

FIG. 15 shows the screening step (step S6) in FIG. A test terminal TND is brought into contact with a pad electrode SNP1 connected to a plurality of capacitor electrodes CE1 through a connecting line WLC1 and a pad electrode SNP2 connected to a plurality of capacitor electrodes CE2 through a connecting line WLC2. A screening voltage is applied across the test terminals TND. Thus, the screening step (step S6) of snubber capacitance Csnu having capacitance electrodes CE1 and CE2 is performed. The screening voltage is, for example, 150 to 200 V, which is higher than the breakdown voltage between the source and drain of the power MOSFET1.

FIG. 16 shows the snubber wiring ESN1 and source electrode ES forming step (step S7) in FIG. After the screening step (step S6) is performed and before the wire bonding step (step S9), which will be described later, the snubber wiring ESN1 and source electrode ES formation step (step S7) is performed. As shown in FIG. 16, in the region CFR, the source electrode ES is formed over the insulating film ILD3 and the conductor layer CP3. The source electrode ES is connected to the capacitor electrode CE2 via the conductor layer CP3, and further connected to the source region SR via the conductor layer CP1.

In the region R2, the snubber wiring ESN1 that connects the pad electrode SNP1 to the conductor layer CP3 is formed over the insulating film ILD3. By forming the snubber wiring ESN1, the drain D of the power MOSFET1 is connected to the capacitance electrode CE1 of the snubber capacitance Csnu.

In region R3, snubber wiring ESN2 connected to pad electrode SNP2 is formed on insulating film ILD3.

By performing the snubber wiring ESN1 and the source electrode ES forming step (step S7) in this manner, the snubber capacitance Csnu is connected between the source and the drain of the power MOSFET1.

FIG. 17 shows the protective film PRO forming step (step S8) in FIG. A protective film PRO is formed over the main surface SUBa of the semiconductor substrate SUB so as to cover the insulating film ILD3, the source electrode ES, and the snubber interconnections ESN1 and ESN2. The protective film PRO is, for example, an organic insulating film such as polyimide, but may be an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a laminated film of a silicon oxide film and a silicon nitride film thereon. Furthermore, a laminated structure of an inorganic insulating film and an organic insulating film may be employed. As shown in FIG. 3, the protective film PRO has pad openings OPS and OPG exposing part of the source electrode ES and part of the gate electrode EG.

The protective film PRO is not shown in the region CFR shown in FIG. This is because FIG. 17 shows a region located within the pad opening OPS.

In regions R2 and R3, snubber lines ESN1 and ESN2 are entirely covered with a protective film PRO.

For example, the steps up to the step of forming the protective film PRO (step S8) are the manufacturing steps of the semiconductor chip CHP1, and the subsequent steps are the mounting steps of the semiconductor chip CHP1.

Next, a wire bonding step (step S9) and a sealing body MR forming step (step S10) shown in FIG. 11 are performed. Description will be made with reference to FIG. A semiconductor chip CHP1 is fixed on the die pad DIP. Next, in a wire bonding step (step S9), the gate pad GP and the gate terminal GT are connected by bonding wires BWg, and the source electrode ES and the source terminal ST are connected by a plurality of bonding wires BWs. In order to reduce the on-resistance of the power MOSFET 1, the bonding wires BWs having a wire diameter larger than that of the bonding wires BWg are used, and a plurality of bonding wires BWs are used to connect the source electrode ES and the source terminal ST. is doing.

Next, as shown in FIG. 3, the semiconductor chip CHP1 mounted on the die pad DIP, bonding wires BWg and BWs, and part of the gate terminal GT and source terminal ST are sealed with a sealing body MR. The sealing body MR is, for example, insulating resin such as epoxy resin.

Although the above process is a part of the manufacturing process of the semiconductor device SD1, the semiconductor device SD1 is completed by performing the above process.

According to the semiconductor device and the manufacturing method thereof according to the first embodiment, the following features can be obtained.

In order to connect the pad electrode SNP1 connected to the capacitor electrode CE1 and the conductor layer CP3 connected to the drain D of the power MOSFET 1 with the snubber wiring ESN1 without using a bonding wire, the pad electrode SNP1 and the conductor layer CP3 are formed. The size can be reduced, and as a result, the drain connection region R2 can be reduced. Therefore, in the semiconductor chip CHP1, the occupation ratio of the source electrode ES of the power MOSFET1 can be improved, the ON resistance of the power MOSFET1 can be reduced, and the performance of the semiconductor device SD1 can be improved.

In the manufacturing process of the semiconductor chip CHP1, after the screening process of the snubber capacitance Csnu, the snubber capacitance Csnu is connected between the drain and source of the power MOSFET1, and then the mounting process of the semiconductor chip CHP1 including the wire bonding process is performed. Since the connection between the capacitance electrode CE1 of the snubber capacitance Csnu and the drain D of the power MOSFET 1 is performed by the snubber wiring ESN1 and no bonding wire is used, it is possible to prevent the yield of the semiconductor device from decreasing due to poor connection of the bonding wire. That is, the yield of the semiconductor device SD1 can be improved.

Since the screening step (step S6) is performed before the snubber capacitance Csnu is connected between the source and drain of the power MOSFET 1, a screening voltage higher than the withstand voltage between the source and drain of the power MOSFET 1 can be applied. Screening can be performed. That is, the reliability of the semiconductor device SD1 incorporating the snubber capacitance Csnu can be improved.

(Embodiment 2)
The second embodiment is a modification of the first embodiment. A dummy electrode DMP1 is arranged below the pad electrode SNP1 in the drain connection region R2. A dummy electrode DMP2 is arranged below the pad electrode SNP2 in the source connection region R3. 18 and 19 are plan views of essential parts of the semiconductor chip CHP2 of the second embodiment, and FIG. 20 is a cross-sectional view showing a manufacturing process of the semiconductor device of the second embodiment.

As shown in FIG. 18, a dummy electrode DMP1 is arranged under the pad electrode SNP1 so as to overlap the entire area of the pad electrode SNP1. For example, the pad electrode SNP1 and the dummy electrode DMP1 are rectangular and have two long sides extending in the X direction and two short sides extending in the Y direction. The short sides of the dummy electrode DMP1 are longer than the short sides of the pad electrode SNP1, and the long sides of the dummy electrode DMP1 are longer than the long sides of the pad electrode SNP1. That is, in plan view, the pad electrode SNP1 is included in the dummy electrode DMP1. Note that the pad electrode SNP1 and the dummy electrode DMP1 may be square.

As shown in FIG. 19, the relationship between the pad electrode SNP2 and the dummy electrode DMP2 is the same as the relationship between the pad electrode SNP1 and the dummy electrode DMP1 shown in FIG.

FIG. 20 corresponds to the screening step (step S6) of the first embodiment. In the regions R2 and R3, the pad electrodes SNP1 and SNP2 are brought into contact with the test terminals TND. It is possible to prevent cracks in the insulating film ILD2 or ILD1 caused by this. If dummy electrodes DMP1 and DMP2 are not arranged, cracks may occur in insulating films ILD2, ILD1, or ILD2 and ILD1 due to pressing of test terminal TND.

Further, in the first embodiment described above, in the step of forming the pad electrodes SNP1 and SNP2 (step S5) described with reference to FIG. There is a risk that the pad electrodes SNP1 and SNP2 will be etched and short-circuited with the semiconductor substrate SUB. In the second embodiment, as shown in FIG. 20, in the etching step of forming the plurality of contact grooves CH3 in the insulating film ILD3, the dummy electrodes DMP1 and DMP2 function as etching stoppers to overetch the insulating films ILD2 and ILD1. can be prevented.

Note that the second embodiment can be applied to the first embodiment.

(Embodiment 3)
Embodiment 3 is a modification of Embodiment 2. FIG. The pad electrode SNP1a and the dummy electrode DMP1a have a lattice pattern. FIG. 21 is a fragmentary plan view of the semiconductor chip CHP3 of the third embodiment, and FIG. 22 is a fragmentary cross-sectional view of the semiconductor chip CHP3 of the third embodiment.

As shown in FIG. 21, the pad electrode SNP1a includes a plurality of grid wiring lines GR1X extending in the X direction, a plurality of grid wiring lines GR1Y extending in the Y direction, and a grid opening GOP1. The grid opening GOP1 is surrounded by two adjacent grid lines GR1X and two adjacent grid lines GR1Y.

The dummy electrode DMP1a also includes a plurality of grid wiring lines GR2X extending in the X direction, a plurality of grid wiring lines GR2Y extending in the Y direction, and grid openings GOP2. The grid opening GOP2 is surrounded by two adjacent grid lines GR2X and two adjacent grid lines GR2Y.

As shown in FIG. 22, the grid opening GOP1 of the pad electrode SNP1a is filled with the insulating film ILD3, and the grid opening GOP2 of the dummy electrode DMP1a is filled with the insulating film ILD2. Also, the grid opening GOP1 of the pad electrode SNP1a and the grid opening GOP2 of the dummy electrode DMP1a overlap each other.

Also, in the screening step (step S6), the test terminal TND is in contact with the multiple grid lines GR1X and the multiple grid lines GR1Y. The interval between adjacent grid lines GR1X and the interval between adjacent grid lines GR1Y in FIG. 21 are, for example, about 1 μm.

By forming the pad electrode SNP1a into a lattice pattern, dishing on the upper surface of the pad electrode SNP1 can be prevented even when the CMP method is used in the pad electrode SNP1 forming step (step S5). Similarly, dishing of the dummy electrode DMPa can be prevented.

In addition, in the second embodiment, the pad electrode SNP2 and the dummy electrode DMP2 can be formed in a lattice pattern. Furthermore, in Embodiment 1, the pad electrodes SNP1 and SNP2 can be formed in a lattice pattern.

(Embodiment 4)
A fourth embodiment is a modification of the third embodiment. A barrier layer BM is interposed between the pad electrode SNP1a and the snubber wire ESN1. FIG. 23 is a fragmentary plan view of the semiconductor chip CHP4 of the fourth embodiment, and FIGS. 24 and 25 are cross-sectional views showing manufacturing steps of the semiconductor device of the fourth embodiment.

As shown in FIG. 23, in plan view, the barrier layer BM includes the pad electrode SNP1a, but exposes the conductor layer CP3 provided in the drain connection region R2. That is, the barrier layer BM covers the pad electrode SNP1a but does not cover the conductor layer CP3. The snubber wire ESN1 covers both the pad electrode SNP1a and the conductor layer CP3. As shown in FIG. 25, the barrier layer BM is connected to the pad electrode SNP1a. The snubber wiring ESN1 is connected to the pad electrode SNP1 through the barrier film BM, and is connected to the conductor layer CP3 without the barrier film BM.

In the flowchart showing the manufacturing process of the semiconductor device shown in FIG. 11, the barrier layer BM forming process is performed between the pad electrodes SNP1 and SNP2 forming process (step S5) and the screening process (step S6).

As shown in FIG. 24, in the screening step (step S6), the test terminal TND is brought into contact with the barrier layer BM and electrically connected to the pad electrode SNP1a via the barrier layer BM. Since the contact resistance of the test terminal TND can be reduced, a more accurate screening process can be performed. Note that the barrier layer BM is made of, for example, a titanium nitride film or a titanium tungsten film.

The fourth embodiment can also be applied to the first or second embodiment.

(Embodiment 5)
The fifth embodiment is a modification of the first embodiment. Pad electrode SNP1b is larger than pad electrodes SNP1 and SNP2 in the first embodiment. FIG. 26 is a fragmentary plan view of the semiconductor chip CHP5 of the fifth embodiment.

As shown in FIG. 26, in the screening step (step S6), the pad electrode SNP1b is in contact with the test terminal TND, and the A region where the probe mark PM is formed and the area A where the test terminal TND is not contacted and the probe mark is formed. B area where PM is not formed. The snubber wiring ESN1b covers the entire area of the pad electrode SNP1b including the regions A and B and the conductor layer CP3, and connects the pad electrode SNP1b to the conductor layer CP3.

By providing the region B in which the probe mark PM is not formed on the pad electrode SNP1b, the connection reliability between the pad electrode SNP1b and the snubber wire ESN1b can be improved.

Although the probe marks are formed on the pad electrode SNP2 in the source connection region R3 shown in FIG. 8 as well, the capacitance electrode CE2 is connected to the source electrode ES in the cell formation region CFR. Don't worry about resistance. Therefore, the area of the pad electrode SNP2 arranged in the source connection region R3 is smaller than the area of the pad electrode SNP1b arranged in the drain connection region R2.

The fifth embodiment can also be applied to the second to fourth embodiments.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and can be variously modified without departing from the gist of the invention. Needless to say.

BCR body contact region (p-type semiconductor region)
BM barrier layer BR body region (p-type semiconductor region, channel layer, base region)
BWd, BWg, BWs bonding wires CE1, CE2 capacitive electrodes CFR cell forming regions CH1, CH2, CH3 contact grooves (contact holes, openings, wiring grooves)
CHP0, CHP1 Semiconductor chips CP1, CP2, CP3 Conductor layers (wiring, contact plugs)
CR1, CR2 Connection region Csnu Snubber capacitance D Drain DIP Die pads DMP1, DMP2 Dummy electrodes (wiring)
DP drain pad DR drift region (n-type semiconductor region)
DT drain terminal ED drain electrode EDP drain pad electrode EG gate electrode ES source electrodes ESN1 and ESN2 snubber wiring (snubber electrode)
G Gate GE Trench gate electrode GI Gate insulating films GOP1, GOP2 Grid opening GP Gate pad GR1X, GR1Y, GR2X, GR2Y Grid wiring GT Gate terminals ILD1, ILD2, ILD3 Insulating film (interlayer insulating film)
MM Main conductor layer MR Sealing body NR N-type semiconductor regions OPD, OPG, OPS, OPSN Pad opening PER Peripheral region PM Probe mark PRO Protective films R1, R2 Drain connection region R3 Source connection region Rsnu Parasitic resistance S Source SD, SD0 Semiconductor Device SNP1, SNP2 Pad electrode (snubber pad electrode)
SP source pad SR source region (n-type semiconductor region)
ST Source terminal SUB Semiconductor substrate SUBa Main surface (first surface)
SUBb back side (second side)
SUBR Substrate region (n-type semiconductor region)
TND Test terminal TR Grooves WLC1, WLC2 Connection wiring WLD Drain connection wiring (wiring)
WLG Gate wiring (wiring)
1 power MOSFET

Claims (20)

a semiconductor substrate formed with a power MOSFET including a source, drain and gate;
a first capacitance electrode extending in a first direction on the main surface of the semiconductor substrate;
a second capacitive electrode extending in the first direction on the main surface of the semiconductor substrate and connected to the source;
a first wiring extending in a second direction crossing the first direction on the main surface of the semiconductor substrate and connected to the first capacitance electrode;
a second wiring extending in the second direction on the main surface of the semiconductor substrate and connected to the second capacitance electrode;
a first pad electrode connected to the first wiring on the main surface of the semiconductor substrate;
a second pad electrode connected to the second wiring on the main surface of the semiconductor substrate;
a third wiring disposed on the first pad electrode and connecting the first pad electrode and the drain;
a source electrode disposed on the first capacitor electrode and the second capacitor electrode and connected to the second capacitor electrode;
A semiconductor device, including The semiconductor device according to claim 1,
moreover,
a first insulating film interposed between the first capacitor electrode and the second capacitor electrode;
A semiconductor device, including The semiconductor device according to claim 1,
moreover,
a second insulating film interposed between the first capacitor electrode and the source electrode;
A semiconductor device, including The semiconductor device according to claim 1,
moreover,
a third insulating film interposed between the first capacitor electrode and the semiconductor substrate;
A semiconductor device, including The semiconductor device according to claim 1,
moreover,
a protective film covering the third wiring and the source electrode and including an opening exposing a portion of the source electrode;
a wire connected to the source electrode in the opening;
A semiconductor device, including The semiconductor device according to claim 1,
moreover,
a dummy electrode arranged under the first pad electrode;
including
The semiconductor device, wherein the dummy electrode includes the first pad electrode in plan view. The semiconductor device according to claim 1,
The semiconductor device, wherein the first pad electrode has a lattice pattern including a plurality of first grid lines extending in the first direction and a plurality of second grid lines extending in the second direction. The semiconductor device according to claim 1,
moreover,
a fourth wiring disposed on the main surface of the semiconductor substrate and connected to the drain;
including
the third wiring has a laminated structure of a barrier layer and a main conductor layer on the barrier layer;
the barrier layer covers the first pad electrode and exposes the fourth wiring;
The semiconductor device, wherein the main conductor layer is connected to the barrier layer covering the first pad electrode and the fourth wiring. The semiconductor device according to claim 1,
The semiconductor device, wherein the first pad electrode is larger than the second pad electrode in plan view. (a) forming a power MOSFET including a source, drain and gate in a semiconductor substrate;
(b) forming a first insulating film on the main surface of the semiconductor substrate;
(c) in plan view, a first groove and a second groove extending in a first direction; a third groove connected to the first groove and extending in a second direction intersecting with the first direction; forming a fourth groove connected to the second groove and extending in the second direction in the first insulating film;
(d) a first capacitor electrode in the first groove, a second capacitor electrode connected to the source in the second groove, and a first capacitor electrode connected to the first capacitor electrode in the third groove; forming a second wiring connected to the second capacitor electrode in the fourth groove;
(e) forming a second insulating film on the first capacitor electrode, the second capacitor electrode, the first wiring, and the second wiring;
(f) forming a fifth groove exposing a portion of the first wiring and a sixth groove exposing a portion of the second wiring in the second insulating film;
(g) forming a first pad electrode connected to the first wiring in the fifth groove and a second pad electrode connected to the second wiring in the sixth groove;
(h) applying a desired voltage between the first capacitor electrode and the second capacitor electrode via the first pad electrode and the second pad electrode;
(i) forming, after the step (h), a third wiring connecting the first pad electrode to the drain on the second insulating film;
A method of manufacturing a semiconductor device, comprising: In the method of manufacturing a semiconductor device according to claim 10,
The method of manufacturing a semiconductor device, wherein the step (i) includes forming a source electrode connected to the second capacitor electrode on the second insulating film. The method for manufacturing a semiconductor device according to claim 11,
moreover,
(j) forming a protective film covering the third wiring and the source electrode;
including
The method of manufacturing a semiconductor device, wherein the protective film includes an opening that partially exposes the source. In the method of manufacturing a semiconductor device according to claim 12,
moreover,
(k) connecting a wire to the source electrode in the opening;
A method of manufacturing a semiconductor device, comprising: In the method of manufacturing a semiconductor device according to claim 10,
The step (c) includes forming a seventh groove in the first insulating film,
The step (d) includes forming a dummy electrode in the seventh groove,
the dummy electrode is arranged under the first pad electrode;
The method of manufacturing a semiconductor device, wherein the dummy electrode includes the first pad electrode in plan view. In the method of manufacturing a semiconductor device according to claim 10,
wherein the first pad electrode has a lattice pattern including a plurality of first grid wirings extending in the first direction and a plurality of second grid wirings extending in the second direction; Production method. In the method of manufacturing a semiconductor device according to claim 10,
The step (f) includes forming an eighth groove in the second insulating film,
The step (g) includes forming a fourth wiring connected to the drain in the eighth groove,
the third wiring has a laminated structure of a barrier layer and a main conductor layer on the barrier layer;
the barrier layer covers the first pad electrode and exposes the fourth wiring;
The method of manufacturing a semiconductor device, wherein the main conductor layer is connected to the barrier layer connected to the first pad electrode and to the fourth wiring. In the method of manufacturing a semiconductor device according to claim 10,
The method of manufacturing a semiconductor device, wherein the first pad electrode is larger than the second pad electrode in plan view. (a) forming a power MOSFET including a source, drain and gate in a semiconductor substrate;
(b) forming, on the main surface of the semiconductor substrate, a first capacitor electrode extending in a first direction and a second capacitor electrode connected to the source and extending in the first direction;
(c) on the main surface of the semiconductor substrate, a first wiring connected to the first capacitance electrode and extending in a second direction intersecting the first direction; and a first wiring connected to the second capacitance electrode, forming a second wiring extending in the second direction;
(d) forming a first pad electrode connected to the first wiring and a second pad electrode connected to the second wiring on the main surface of the semiconductor substrate;
(e) applying a desired voltage between the first capacitor electrode and the second capacitor electrode via the first pad electrode and the second pad electrode;
(f) forming a third wiring connecting the first pad electrode to the drain after the step (e);
A method of manufacturing a semiconductor device, comprising: 19. The method of manufacturing a semiconductor device according to claim 18,
The method of manufacturing a semiconductor device, wherein the step (f) includes forming a source electrode connected to the second capacitor electrode. In the method of manufacturing a semiconductor device according to claim 19,
moreover,
(g) forming a protective film covering the third wiring and the source electrode and including an opening exposing a portion of the source electrode;
(h) connecting a wire to the source electrode in the opening;
A method of manufacturing a semiconductor device, comprising:

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