JP2007300133A - Semiconductor light receiving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light receiving device for suppressing leak currents even when it is mounted on a module. <P>SOLUTION: A PIN type photo-diode 10 is provided with: a semiconductor substrate 31; first conductive type first semiconductor layers 34 and 35 formed on the semiconductor substrate 31; a light absorbing layer 36 formed on the first semiconductor layer for generating a carrier according to incident rays of light; second conductive type second semiconductor layers 37, 38, 39 and 40 formed on the light absorbing layer 36; a first electrode part 41 for applying a first potential to the first semiconductor layer; a second electrode part 42 for applying a second potential to the second semiconductor layer; and at least one second conductive type third semiconductor layer 33 interposed between the first main surface of the substrate and the first semiconductor layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor light receiving device, and more particularly to a PIN photodiode that can operate at high speed and can be used in a communication system of a large capacity optical fiber.

  In recent years, with the increase in capacity of optical communication systems, transmission systems with speeds of several tens of Gbps (for example, 40 Gbps) or higher have been developed. Since the semiconductor light receiving element used in such a large capacity transmission system is required to operate at a high speed of 40 GHz or more, it must have higher performance and higher reliability than the conventional one. .

  FIG. 5 is a perspective view showing a configuration example of a PIN photodiode in which a tapered optical waveguide structure disclosed in Patent Document 1 is integrated, and an A part in the figure is an enlarged sectional view of a light receiving part of the photodiode. . As shown in the figure, the photodiode 100 has a tapered optical waveguide structure 102 coupled to a side portion of the light receiving element 103 on a semi-insulating InP substrate 101. The tapered optical waveguide structure 102 converts light from the optical fiber into a spot size and makes it incident from the side surface of the light absorption layer 104 of the light receiving element 103.

  The p-side electrode pad 105 is formed in a predetermined shape on the substrate 101 via an insulating film, while the n-side electrode pad 106 is also formed on the same plane as the p-side electrode pad 105. Therefore, the photodiode 100 can be directly connected to a substrate having a coplanar stripline structure. A P electrode 107 is formed on the top of the light receiving element 103, and the P electrode 107 is connected to the p-side electrode pad 105 by an air bridge 107a.

  The n-electrode 108 is formed on the surface of the n-type semiconductor layer 109 exposed by etching the light-receiving element 103 into a mesa structure. N electrode 108 is connected to n side electrode pad 106 extending on semiconductor layer 109. The n-side electrode pad 106 has a relatively large area. This is to secure a connection region with a bypass capacitor, which will be described later, and to ensure that the n-electrode 108 is at the ground potential during high-frequency operation.

  In realizing a high-speed operation of several tens GHz (for example, around 40 GHz) or more, a photodiode having an extremely small PIN junction area (for example, several tens of fF or less) than a conventional chip can be applied between electrodes even when a slight noise pulse is applied. There is a possibility that a large voltage is applied and the element is deteriorated. Therefore, in a normal optical receiver module, as shown in FIG. 6, when the photodiode chip 110 and the amplifier circuit (preamplifier) 111 for amplifying the received signal are mounted, the vicinity of the n-side electrode pad 106 of the photodiode 100. It was necessary to provide a large bypass capacitor 112.

In the optical receiving module, the chip 110 of the photodiode 100 is brazed with AuSn (silver paste) on the subcarrier, whereby the metal layer on the back surface of the chip 110 is connected to the ground potential. The n-side electrode pad 106 of the photodiode is electrically connected to the upper electrode 112a of the bypass capacitor 112 via the wiring 113, and the upper electrode 112a is further connected to the positive potential side of the DC bias power supply 115 via the wiring 114. The lower electrode of the bypass capacitor 112 is connected to the ground potential. The p-side electrode pad 105 of the photodiode is connected to the ground potential via the input terminal 111 a of the preamplifier 111.
JP 2001-127333 A

  However, the conventional semiconductor light receiving device has the following problems. Since the photodiode chip 110 and the bypass capacitor 112 are arranged in a plane in the optical receiving module, a large area is required. The bypass capacitor 112 has a planar size at least several times that of the photodiode chip 110, and a plurality of such bypass capacitors may be connected as necessary. For this reason, it is difficult to miniaturize the optical receiver module and it is difficult to simplify the manufacturing process.

  Furthermore, in order to connect to the upper electrode 112a having such a large area and the n-side electrode pad 106 of the photodiode 100, a large number of wirings 113 are required. For this reason, the inductance component (L component) by many wiring 113 became very large, and this became the hindrance of high-speed operation.

  Furthermore, since the p-side electrode pad 105 of the photodiode and the chip back surface (metal layer) are connected to the ground potential having the same potential, a leak path is formed between the n-side electrode 106 and the chip back surface (metal layer). As a result, there is a problem that the leakage current flowing through the module after mounting is rapidly increased even though the leakage current of the chip alone is sufficiently low.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described conventional technique and provide a semiconductor light-receiving device that can be miniaturized and is excellent in high-speed operation.

  Another object of the present invention is to provide a semiconductor light receiving device in which leakage current is suppressed even when mounted on a module.

  The semiconductor light-receiving device according to claim 1 is formed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and on the first main surface side of the semiconductor substrate. A first semiconductor layer including two first conductivity type semiconductor layers, a light absorption layer formed on the first semiconductor layer and generating carriers in response to incident light, and formed on the light absorption layer. A second semiconductor layer including at least one second-conductivity-type semiconductor layer; a first electrode portion that is electrically connected to the first semiconductor layer and applies a first potential; and the second semiconductor layer A second electrode portion that is electrically connected to the layer and applies a second potential; and at least one second conductivity type interposed between the first main surface of the semiconductor substrate and the first semiconductor layer. And a third semiconductor layer.

  The semiconductor light-receiving device according to claim 1, wherein at least one third semiconductor layer of the second conductivity type is provided between the first main surface of the substrate and the first semiconductor layer, whereby the third semiconductor Since the layer has a conductivity type different from that of the first semiconductor layer, formation of a current path between the first electrode portion and the substrate is prevented, and carriers generated in the light absorption layer move from the first semiconductor layer to the substrate. Suppress. As a result, current flowing between the first semiconductor layer and the second semiconductor layer at the time of light reception can be effectively suppressed from leaking to the substrate side, or dark current can flow. It is possible to accurately detect the current corresponding to the amount of light received from the electrode part and the second electrode part.

  According to a second aspect of the present invention, the second main surface is connected to a ground potential, and the first potential is a positive potential. According to a third aspect of the present invention, a reverse bias is applied to the junction formed by the first semiconductor layer and the third semiconductor layer. Furthermore, as described in claim 4, the semiconductor substrate is a semi-insulating semiconductor substrate.

  Preferably, the semiconductor light-receiving device further includes a fourth semiconductor layer of a first conductivity type, and the third semiconductor layer includes the first semiconductor layer and the fourth semiconductor layer. You may make it interpose between semiconductor layers. In such a configuration, an npn or pnp type multilayer buffer structure (for example, a bypass diode) is formed. As a result, the current leakage path between the first electrode portion connected to the first semiconductor layer and the substrate can be eliminated, and the leakage current during module mounting can be reduced as in the conventional case. Further, such a multilayer buffer structure can also function as a bypass capacitor due to the capacitance formed by the pn junction.

  According to a sixth aspect of the present invention, the first semiconductor layer may include a high impurity concentration contact layer connected to the first electrode portion. According to a seventh aspect of the present invention, the second semiconductor layer may include a high impurity concentration contact layer connected to the second electrode portion. The contact layer preferably has an impurity concentration of an ohmic connection with the first and second metal parts.

  According to an eighth aspect of the present invention, the first semiconductor layer may include a low concentration buffer layer. According to a ninth aspect of the present invention, the second semiconductor layer may include a graded layer in which a plurality of semiconductor layers whose band gaps are gradually inclined are stacked.

  The light absorption layer and the second semiconductor layer may have a mesa structure, and light may be incident from a side surface of the light absorption layer exposed by the mesa structure. Good. That is, it is desirable that the semiconductor light-receiving device is of an end-face incident type, but the present invention is not necessarily limited to the end-face-incidence type, and can also be applied to a semiconductor light-receiving device of a type in which light enters from the upper surface or the lower surface of the substrate.

  According to an eleventh aspect of the present invention, an optical waveguide for allowing light to enter the light absorption layer may be disposed on a side portion of the mesa structure. The optical waveguide may include a semiconductor layer, and these may be formed on the same substrate.

  13. The surface of the first semiconductor layer is exposed at the bottom of the mesa structure, the first electrode is formed on the exposed surface, and the second semiconductor layer of the mesa structure is formed. A second electrode may be formed thereon.

  According to a thirteenth aspect of the present invention, the semiconductor light receiving device may include an avalanche diode. Furthermore, the semiconductor light receiving device may include a phototransistor.

Preferably, the first semiconductor layer includes an n-type InP layer, the second semiconductor layer includes a p-type InP layer, and the third semiconductor layer includes a p-type InP layer. Type InP layer (preferably with an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less), and the light absorbing layer is preferably an InGaAs layer. However, it goes without saying that other III-V semiconductor compounds may be used.

  According to the present invention, since the semiconductor layer is integrated so that a capacitor with a pn junction is formed on the substrate of the semiconductor light receiving device, a conventional bypass capacitor externally attached to the semiconductor light receiving device can be reduced in size or Reduction (including reduction of number, complete removal). This makes it possible to reduce the size of the semiconductor light receiving device. At the same time, the number of wires connected to such an external bypass capacitor can be reduced by reducing or reducing the size of the external bypass capacitor, and it is also possible to improve the high-speed response by reducing the L component due to the wiring. . Furthermore, by integrating such a bypass capacitor on the substrate, current leakage on the back surface (second main surface side) of the substrate can be efficiently prevented.

Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a cross section of a PIN photodiode according to the first embodiment of the present invention. The PIN photodiode 10 according to the present embodiment is obtained by integrating an npn bypass diode 20 on a semiconductor substrate 31. In this figure, on a semiconductor substrate 31 made of InP, an n ⁺ type InP layer 32, a p ⁻ type InP layer 33 (preferably an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less), an n ⁺ type InP. Contact layer 34 composed of layers, low-concentration buffer layer 35 composed of n ⁻ -type InP, non-doped InGaAs light absorption layer 36, graded layers 37 and 38 composed of p ⁻ -type InGaAsP layers, and p ⁺ -type InP layer 39 , And a contact layer 40 made of a p ⁺ -type InGaAsP layer. The npn-type bypass diode 20 includes an n-type InP layer 32, a p-type InP layer 33, and an n-type InP contact layer 34.

  An n-side electrode 41 made of Au / Ge two-layer metal is ohmically connected to the contact layer 34, and a p-side electrode 42 made of Au / Zn two-layer metal is ohmically connected to the contact layer 40. A contact metal layer 43 made of a Ti / Pt / Au layer or a TiW / Au layer is formed on the back surface of the substrate 1.

The n-side electrode 41 is set to a positive potential, and the p-side electrode 42 is set to a negative potential. The contact metal 43 is set to the ground potential. As a result, a reverse bias voltage is applied to the p-side semiconductor layers 37, 38, 39 and 40 and the n-side semiconductor layers 34 and 35 sandwiching the light absorption layer 36 which is a light receiving portion. A reverse bias is also applied to the npn-type bypass diode 20, and a depletion layer or a depletion region is formed at the pn junction surface between the contact layer 34 and the semiconductor layer 33. This depletion region functions as a capacitor. The capacitance of the npn junction is equal to the capacitance of a parallel plate electrode in which an insulator having a relative dielectric constant ε and a thickness d of a depletion layer is inserted. The thickness of the depleted p ⁻ InP layer 33 is 0.5 μm, the chip area is 500 × 600 μm ² , and the capacitance of the bypass diode 20 is 10 pF. If such a capacitance is integrated, the capacitor can sufficiently function as a bypass capacitor of the photodiode, and an external bypass capacitor is not necessarily used. However, this does not prevent the combined use of the bypass diode 20 and an external bypass capacitor.

  A light receiving portion of the mesa structure 46 is formed on the semiconductor substrate 31. The mesa structure 46 is obtained by etching a semiconductor layer from the contact 40 to the buffer layer 35. At the same time, a part of the surface of the contact layer 34 is exposed by this etching, and the n-side electrode 41 is formed on the contact layer 34. Is formed. Since the npn-type bypass diode 20 is not formed in the mesa structure 46 but is formed between the mesa structure 46 and the substrate 1, the area of the pn junction surface of the bypass diode 20 is relatively small as described above. The capacitance of the capacitor can be increased.

  By forming the mesa structure 46, the side surface 36 a of the light absorption layer 36 is exposed, and although not shown here, the optical waveguide is disposed on the side of the mesa structure 46 on the semiconductor substrate 31. The optical waveguide is connected to the side surface 36a of the light absorption layer 36, and light guided by the optical waveguide enters the light absorption layer 36 from the side surface 36a.

  FIG. 4 is a diagram showing an equivalent circuit in a module including the PIN type photodiode shown in FIG. As described above, in the PIN photodiode 10, the bypass diode 20 is integrated on the semiconductor substrate 31, and this constitutes one chip or element 10a. The cathodes of the photodiode 10 and the npn-type bypass diode 20 are connected to the ground potential 45 through the load ZL. Preferably, the module or the case body on which the chip 10a is mounted is grounded, and the cathode is connected to this. The anodes of the photodiode 10 and the bypass diode 20 are connected to the positive potential of the DC power supply 44 via the load Rb, and the bypass diode 20 is connected in parallel with the photodiode 10.

  Next, the operation of the PIN photodiode will be described. In operation, a reverse bias is applied between the n-side electrode 41 and the p-side electrode 42 of the photodiode 10. When light from the optical waveguide enters from the side surface 36 a of the light absorption layer 36, electron and hole carriers are generated in the light absorption layer 36, and these carriers move in the thickness direction of the light absorption layer 36. . Electrons reach the n-side electrode 41 through the buffer layer 35 and the contact layer 34, and holes reach the p-side electrode 42 through the p-side semiconductor layers 37, 38, 39, and 40, depending on incident light. The detected current is detected from the n-side electrode 41 and the p-side electrode 42.

  At this time, a reverse bias is applied to the contact layer 34 and the p-type InP layer 33 constituting the npn-type bypass diode 20, and a depletion region functioning as a capacitor is formed on this junction surface. Since the npn bypass diode 20 is connected in parallel with the photodiode 10, this capacitor functions as a bypass capacitor. Furthermore, since there is a reverse-biased pn junction between the n-side electrode 41 and the contact metal layer 43, a leak path between the n-side electrode 41 and the contact metal layer 43 is prevented, and the current generated by the light absorption layer 36 Can effectively suppress so-called dark current flowing through the semiconductor substrate 31 to the contact metal layer 43.

  Thus, by laminating the bypass diode 20 on the monolithic substrate, the size or number of bypass capacitors externally attached to the PIN photodiode 10 can be reduced. As a result, the module body or case body on which the photodiode is mounted can be reduced in size. Of course, all functions may be substituted by the bypass diode 20 without using an external bypass capacitor. Furthermore, if the size or number of external bypass capacitors is reduced, the number of wires required for this can be reduced, and the frequency response characteristics can be improved by reducing the inductance component due to the wires. Preferably, it is possible to operate at a high speed of 35 to 40 GHz or higher.

  Next, a PIN photodiode 11 according to a second embodiment of the present invention is shown in FIG. FIG. 2 is a view showing a cross section of the photodiode as in FIG. In the photodiode 11 of the second embodiment, the n-type InP layer 32 in the first embodiment is removed, and a p-type InP layer 33 is formed on the substrate 31. Other configurations Is the same as that of the first embodiment.

  A p-type InP layer 33 and an n-type contact layer 34 are formed on the semiconductor substrate 31. By supplying a positive potential to the n-side electrode 41 and setting the contact metal layer 43 to the ground potential, a reverse bias voltage is applied to the pn junction between the InP layer 33 and the contact layer 34, and due to the depletion region of the pn junction surface. The capacitor 21 is obtained. The basic operation of the capacitor 21 is the same as that of the bypass diode 20 of the first embodiment.

  Next, a third embodiment of the present invention will be described. FIG. 3 is a cross-sectional view showing the configuration of the avalanche photodiode according to the third embodiment. The avalanche photodiode avalanche-multiplies electron / hole carriers generated by the incidence of light to increase the responsiveness to the incidence of light. As shown in FIG. 3, an n + type InP 51 and an i type or n type InP multiplication layer 52 for avalanche multiplication are formed on the graded layer 38. The npn-type bypass diode 20 has the same configuration as in the first embodiment.

  Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications are possible within the scope of the gist of the present invention described in the claims.・ Change is possible.

  For example, although the non-doped InGaAs layer is used as the light absorption layer 36 in the above embodiment, it is not limited to this and may be p-type or n-type. Further, the semiconductor light receiving device is exemplified as an end face type in which light is incident from the side or end surface of the mesa structure. However, the present invention is not limited to this, and the light receiving device that allows light to be incident from the top of the mesa structure or the back surface side of the substrate. It is possible to apply. Furthermore, the number of p-type and n-type semiconductor layers stacked on the upper and lower sides of the light absorption layer 36 and the composition thereof are not limited to the above-described embodiments, and can be appropriately changed without departing from the gist of the present invention. is there.

1 is a cross-sectional view of a PIN photodiode according to a first embodiment of the present invention. It is sectional drawing of the PIN type photodiode which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the avalanche type photodiode which concerns on the 3rd Embodiment of this invention. 2 is an equivalent circuit in a module including the PIN photodiode shown in FIG. It is a perspective view which shows one structural example of the conventional semiconductor light-receiving device. It is a typical top view which shows the mounting state of the semiconductor light-receiving device in the conventional optical receiver module.

Explanation of symbols

10, 11, 12, 13: PIN type photodiode 14: Avalanche photodiode 20: npn type bypass diode 21: Capacitor 31: Semiconductor substrate 32: n ⁺ InP layer 33: p ⁻ InP layer 34: n ⁺ contact layer 35: Low concentration buffer layer 36: light absorption layer 39: p ⁺ InP layer 40: p ⁺ contact layer 41: n-side electrode 42: p-side electrode

Claims (16)

A semiconductor substrate comprising a first main surface and a second main surface opposite to the first main surface;
A first semiconductor layer formed on the first main surface side of the semiconductor substrate and including at least one semiconductor layer of a first conductivity type;
A light absorption layer formed on the first semiconductor layer and generating carriers in response to incident light;
A second semiconductor layer formed on the light absorption layer and including at least one second conductivity type semiconductor layer;
A first electrode portion electrically connected to the first semiconductor layer and applying a first potential;
A second electrode portion that is electrically connected to the second semiconductor layer and applies a second potential;
A semiconductor light receiving device having a second conductivity type third semiconductor layer interposed between a first main surface of the semiconductor substrate and the first semiconductor layer.   The semiconductor light receiving device according to claim 1, wherein the second main surface is connected to a ground potential, and the first potential is a positive potential.   The semiconductor light receiving device according to claim 2, wherein a reverse bias is applied to a junction formed by the first semiconductor layer and the third semiconductor layer.   The semiconductor light receiving device according to claim 1, wherein the semiconductor substrate is a semi-insulating semiconductor substrate.   The semiconductor light receiving device further includes a fourth semiconductor layer of a first conductivity type, and the third semiconductor layer is interposed between the first semiconductor layer and the fourth semiconductor layer. Semiconductor light receiving device. The semiconductor light receiving device according to claim 1, wherein the first semiconductor layer includes a contact layer having a high impurity concentration connected to the first electrode portion. The semiconductor light-receiving device according to claim 1, wherein the second semiconductor layer includes a contact layer having a high impurity concentration connected to the second electrode portion. The semiconductor light receiving device according to claim 1, wherein the first semiconductor layer includes a buffer layer having a low impurity concentration. 2. The semiconductor light receiving device according to claim 1, wherein the second semiconductor layer includes a graded layer in which a plurality of semiconductor layers are stacked such that a forbidden band width is gradually inclined. 2. The semiconductor light receiving device according to claim 1, wherein at least the light absorption layer and the second semiconductor layer have a mesa structure, and light enters from a side surface of the light absorption layer exposed by the mesa structure. The semiconductor light-receiving device according to claim 10, further comprising an optical waveguide disposed on a side portion of the mesa structure for allowing light to enter the light absorption layer. The surface of the first semiconductor layer is exposed at the bottom of the mesa structure, the first electrode is formed on the exposed surface, and the second electrode is formed on the second semiconductor layer of the mesa structure. The semiconductor light-receiving device according to claim 10. The semiconductor light receiving device according to claim 1, wherein the semiconductor light receiving device includes an avalanche diode. The semiconductor light receiving device according to claim 1, wherein the first semiconductor layer includes an n-type InP layer, and the second semiconductor layer includes a p-type InP layer. The semiconductor light receiving device according to claim 1, wherein the light absorption layer is an InGaAs layer. 2. The semiconductor light receiving device according to claim 1, wherein the third semiconductor layer is a p-type InP layer and has an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less.

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