JP2007299904A5 - - Google Patents

Description

Semiconductor device and inspection method thereof

  The present invention relates to various types of Si LSIs such as dynamic random access memory (DRAM), flash memory, logic LSI, and the like, and more particularly, to electrical due to defective line width and contact diameter generated in these Si LSIs. The present invention relates to a semiconductor device capable of detecting a conduction failure and a short-circuit failure with high sensitivity and a short inspection time, and an inspection method thereof.

  2. Description of the Related Art Conventionally, various proposals have been made for detecting an electrical failure that occurs in the wiring of a semiconductor device. One example is the potential contrast method described in Patent Document 1, which will be described with reference to FIG. In FIG. 11, the semiconductor device has a structure in which a plurality of wirings 1a to 1k and 2a to 2k extending in the X direction are arranged in parallel to each other in the Y direction on a substrate. As shown in the figure, among these alternately arranged wires, the first set of wires 1a to 1k and the second set of wires 2a to 2k are arranged at different positions in the X direction, that is, the second set The pair of wirings 2a to 2k protrude downward in the figure, and the protruding end portions are connected to a single power supply wiring 3 to which a predetermined potential is applied. On the other hand, each of the first set of wirings 1a to 1k is at a floating potential.

  When the semiconductor device is scanned by moving the semiconductor device and the electron beam relatively in the Y direction while irradiating the semiconductor device having such a structure with the electron beam, the second set The potentials of the wirings 2a to 2k are fixed to a predetermined potential given in advance and do not change. On the other hand, the potentials of the first set of wirings 1a to 1k in the floating state fluctuate by an amount corresponding to “amount of electrons obtained by irradiation” − “amount of secondary electrons emitted”. The amount of secondary electrons emitted from the wirings 1a to 1k is different from the amount of electrons emitted from the second set of wirings 2a to 2k. Accordingly, by detecting such a change (that is, a difference) in the amount of emitted secondary electrons, it is possible to separate and extract the wiring at the floating potential from the wiring at the fixed potential. This is called a potential contrast method (VC method).

Therefore, when one wiring of the first set of wirings at the floating potential, for example, the wiring 1d, is short-circuited to the wiring 2c at the adjacent fixed potential, the potential of the wiring 1d at the floating potential becomes a fixed potential. . Therefore, when scanning with an electron beam as described above, the amount of secondary electrons emitted from the wiring 1d is the same as the amount of secondary electrons emitted from the fixed potential wirings 2c and 2d sandwiching the wiring 1d. As a result, the wiring 1d can be separated and extracted from wirings at other floating potentials, and it is possible to detect which wiring is short-circuited with the adjacent wiring.
Japanese Patent Laid-Open No. 11-27066

  However, the conventional electrical failure detection method described with reference to FIG. 11 is effective in detecting a short-circuit failure, but the structural dimensions such as how much the short-circuit is likely to occur from the line space. You cannot know the margin.

  The present invention has been proposed in view of the above problems, and the object of the present invention is not only to detect the presence or absence of short-circuit defects, but also to provide a short-circuit-proof dimension margin, a disconnection-proof dimension margin, a conduction-defective margin, etc. An object of the present invention is to provide a semiconductor device having a structure capable of performing various inspections and an inspection method thereof.

  In order to achieve the above object, for example, in order to know the structural dimensional margin from the viewpoint of short-circuit resistance, FIG. 11 is developed and a plurality of test element groups (hereinafter referred to as “line width” and “wiring space”) are changed. And TEG), and a short circuit yield is measured for each TEG by VC inspection using an electron beam. Similarly, when knowing the breakage margin of wiring and the contact and via conduction failure margin, a plurality of TEGs with different dimensions may be arranged and detected by VC inspection.

Therefore, a semiconductor device according to the invention of claim 1 is:
Provided with a plurality of wirings arranged symmetrically and parallel to the axis so that one end faces each other, the other wirings of the plurality of wirings are grounded at the other end, and the remaining wirings are at a floating potential. A wiring pattern including at least one TEG is provided.

A semiconductor device according to the invention of claim 2 is provided.
A wiring pattern including a plurality of wirings arranged symmetrically and in parallel with respect to an axis so that one end faces each other, and including a wiring pattern including at least one TEG connected to the ground electrode at the other end of the plurality of wirings. Features.

  In a semiconductor device according to a third aspect of the invention, the plurality of wirings are provided in a first wiring layer, and the ground electrode is provided in a second wiring layer different from the first wiring layer, A plurality of wirings and the ground electrode are connected by vias.

According to a fourth aspect of the present invention, there is provided a semiconductor device further comprising a wiring having a ground potential or a floating potential provided in a region having a predetermined width centered on the axis.
A semiconductor device according to a fifth aspect of the present invention includes a wiring pattern in which a plurality of the TEGs are arranged in a predetermined direction.

A semiconductor device according to a sixth aspect of the invention is characterized in that a multiple of 2 or a power of 2 TEGs are arranged in the predetermined direction.
A semiconductor device according to the invention of claim 7
The design parameters such as the line width and distance between the plurality of TEGs are different from each other,
A plurality of the TEGs are arranged in the order of low occurrence frequency of disconnection defects in the electron beam scanning direction at the time of inspection by potential contrast.

  In the semiconductor device according to the invention of claim 8, the plurality of TEGs are arranged over a plurality of wiring layers, and the TEGs arranged in the same wiring layer are continuously arranged in the electron beam scanning direction at the time of inspection by potential contrast. It is characterized by being.

  An inspection method according to a ninth aspect of the invention irradiates an electron beam to a region having a predetermined width including the axis and the opposing ends of the plurality of wirings, and corresponds to the amount of secondary electrons emitted from the region. A defective portion is detected based on a potential contrast signal to be detected.

  In the inspection method according to the invention of claim 10, the electron beam is scanned in a direction parallel to the axis and sequentially shifted in position, and the amount of secondary electrons emitted in response to the irradiation of the electron beam is set. It is characterized in that defective portions are continuously detected based on corresponding potential contrast signals.

  The inspection method according to an eleventh aspect of the invention is characterized in that a plurality of regions located at predetermined intervals in a direction perpendicular to the axis line are simultaneously irradiated with an electron beam to continuously detect defective portions.

  The present invention can not only efficiently detect short-circuit defects and disconnection defects occurring in wiring on a semiconductor device, but also quickly detect deterioration of a margin in a manufacturing process in which such defects are generated. There is a special effect that you can. Therefore, it is possible to contribute to improving the efficiency of countermeasures against defects in the manufacturing process and improving the yield of semiconductor devices.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, several embodiments of a semiconductor device and an inspection method thereof according to the present invention will be described in detail with reference to FIGS. In all the drawings, the same reference numerals or reference numerals indicate the same or similar components.

  (A-1) to (A-3) of FIG. 1 schematically show three basic structure patterns of a wiring short-circuit detection TEG for measuring a short-circuit-proof dimension margin according to the present invention, A cross section of one of the TEGs is shown in FIG. In addition, (A-1) to (A-3) in FIG. 1 are diagrams for explaining the positional relationship between components in three types of TEGs having different pattern shapes. Regardless of whether they are formed in layers, they are shown on the same plane.

  In FIG. 1, TEGs having any one of the basic structure patterns (A-1) to (A-3) are formed on the same semiconductor device, for example, on the same die (or chip). First wirings 11, 12, and 13 having a floating potential, and a pair of second wirings 141, 142; 151, 152; 161, 162 disposed on both sides of the first wiring in parallel. In order to set these second wirings to the ground potential, the third wirings 143, 153, and 163 are connected between the wirings forming the respective pairs. As shown in the figure, the line width of the TEG shown in (A-1) is the largest, and the line width of the TEG shown in (A-3) is the smallest, but has the same basic structure in other points. .

As shown in FIG. 1B, the first wiring 11 and the second wirings 141 and 142 are formed on the upper surface of the SiO ₂ layer 17 to form the first layer 18, and the third wiring 143 is made of SiO _2. A plurality of contacts 19 penetrating the layer 17 are connected to the second layer active region 21 formed on the Si substrate 20. Reference numeral 22 denotes an STI (shallow trench isolation) layer. Such a structure is the same in the TEGs shown in FIGS. 1A-2 and A-3.

  Therefore, in the TEG shown in FIG. 1, when a short circuit failure occurs between the first wiring and the second wiring, the first wiring originally in the floating potential becomes the ground potential, and an image obtained in the VC inspection is obtained. Since this is different from the normal image, it is possible to know where the short-circuit defect has occurred. As described above, the present invention has been proposed based on the knowledge that the occurrence of a short circuit failure can be detected by alternately arranging two types of wirings having different potentials in a predetermined direction. Hereinafter, an embodiment of a semiconductor device having a TEG structure according to the present invention and an inspection method thereof will be described in detail with reference to FIGS.

  FIG. 2 is a diagram schematically showing a first embodiment of a semiconductor device according to the present invention. In order to realize the above knowledge, this semiconductor device is configured by alternately arranging two types of wirings having different potentials. A number of TEGs are provided that are arranged symmetrically. As shown in the figure, the TEG 31 is surrounded by a TEG frame 32 that is a grounded wiring, and the wiring 33 that is connected to the TEG frame 32 and is at the ground potential and the wiring 34 that is at the floating potential are alternately and parallel to each other. Have two TEG regions 35 and 36 arranged in the same manner. Further, between the two TEG regions 35, 36, a ground potential wiring 37 disposed in a direction perpendicular to the wirings 33, 34 is provided. The two TEG regions 35 and 36 are arranged symmetrically with respect to the wiring 37. By adopting such a structure, there is an effect that, when the TEG 31 is irradiated with an electron beam, the electron beam hits outside the region of the TEG 31, and the portion is prevented from being charged up.

  As shown in the drawing, the wiring 34 at the floating potential has a shape having a pad structure 38 in which an end portion close to the center of the TEG 31 swells. In this pad structure 38, when any part of the wiring 34 at the floating potential is short-circuited to the wiring 33 having the adjacent ground potential (for example, when a short-circuit occurs at a part indicated by numeral 39 in FIG. 2), the VC inspection is performed. Is provided to emphasize changes in light and darkness in the image obtained by the above. As described above, since there are a large number of floating potential pad structures 38 in the central portion of the TEG 31 and the entire central portion is likely to become a floating potential, the ground potential is applied to the central portion for the purpose of stabilizing the central potential. A structure in which the wiring 37 is arranged is employed.

  FIG. 3 is a diagram schematically showing a second embodiment of the semiconductor device according to the present invention, and shows a TEG 41 in which the left and right symmetrical TEGs 31 shown in FIG. 2 are two-dimensionally arranged. 3, the TEG 41 shown in FIG. 3A has a structure in which a TEG 42 having the same structure as the TEG 31 shown in FIG. 2 is used as a basic structure, and a large number of TEGs 42 are arranged vertically and horizontally. The periphery of the TEG 41 is surrounded by a TEG frame 43. It is. That is, the TEG 41 shown in FIG. 3 has a larger TEG frame 43 than the TEG 31 shown in FIG. 2, and the TEGs 42 having the basic structure shown in FIG.

  Therefore, when the TEG 41 shown in FIG. 3 is inspected, it is possible to scan with a narrow width from the beginning using an electron beam having a sufficiently small pixel size so that the details of the defective portion can be detected. . However, if this is the case, the inspection time may become enormous. Therefore, in order to shorten the inspection time, the first inspection is performed by irradiating an electron beam with a large pixel, and thus with a wide scan width. It is preferable to grasp in advance a minimum TEG width unit in advance and to inspect only the TEG region where the short-circuit defect has occurred in the second inspection with a small pixel size and a narrow scan width. In this case, if the scan width in the second inspection is set to an integer multiple of the scan width in the first inspection, a multiple of 2 or a power of 2, the scan width in the second inspection becomes the first scan width. It can fit in the scan width in the inspection without excess and deficiency, and the inspection efficiency can be improved. Further, when designing the TEG, it is preferable to set the scan width so that an unscanned area does not appear.

  FIG. 4 is a diagram schematically showing a third embodiment of the semiconductor device according to the present invention, and this semiconductor has three basic structures shown in (A-1) to (A-3) of FIG. The TEG 51 has a structure in which two pairs of TEGs are arranged so as to face each other. That is, the TEG 51 includes a TEG group 52 having the largest line width, a TEG group 53 having an intermediate line width, and a TEG group 54 having the smallest line width. The TEG 51 is designed for the purpose of examining the correlation between the line width and the occurrence of a short circuit failure. In general, it is considered that as the line width increases, a short circuit failure is more likely to occur.

  By the way, in a VC inspection using an electron beam, if there are many regions at a floating potential, the potential on the surface of the semiconductor device greatly fluctuates in the vicinity of such a region, so that the electron beam for scanning is bent and the inspection result is adversely affected. May appear. That is, if a region with many wirings at a floating potential is arranged on the upstream side of the electron beam irradiation, there is a possibility that the adverse effect may reach the downstream side. In order to avoid this problem as much as possible, in FIG. 4, the TEG region 52 having the largest line width, which is assumed to have relatively few regions at the floating potential, is arranged upstream of the electron beam irradiation. ing.

  In such a TEG for detecting a short-circuit failure, in the vicinity of the mirror symmetry axis of the TEG (for example, in FIG. 2 and FIG. 3, the axis passing through the center line of the wiring 37), there are many A relatively large pad structure 38 is formed so as to emit secondary electrons and thus obtain a large VC test signal. Therefore, in order to detect whether or not the TEG has a short circuit failure, it is only necessary to inspect only the vicinity of the pad structure 38. For example, in FIG. 3, the electron beam may be irradiated to the area including the wiring 37 and the pad structures on both sides thereof. Further, in FIG. 4, only the area including the pad structure located on both sides of the symmetry axis of each of the TEG regions 52 to 54 needs to be inspected by scanning with an electron beam.

  FIG. 5 is a diagram schematically showing a fourth embodiment of the semiconductor device according to the present invention, which is an extension of the TEG 51 shown in FIG. In FIG. 4, the TEG 51 is for a specific wiring layer. On the other hand, in the fourth embodiment, the TEG 51 shown in FIG. 4 is shifted in position so as not to overlap with different wiring layers (first wiring layer to third wiring layer in FIG. 5). It is intended to be provided. The reason why the TEGs are continuously arranged so as not to overlap each other is to irradiate only the regions where the TEGs are formed and not to irradiate unnecessary regions with the electron beams.

  FIG. 6 schematically shows a fifth embodiment of the semiconductor device according to the invention. In this embodiment, the TEG 51 shown in FIG. 4 is arranged in one wiring layer, and the same wiring layer is arranged on the upstream side, downstream side of the TEG 51 as viewed from the scanning direction of the electron beam in the VC inspection, or Stable dummy TEGs 61 having no risk of disconnection failure are arranged on the upstream side and the downstream side. As shown in the figure, the dummy TEG 61 includes a pair of wirings 62 and 63 that are at a floating potential and are arranged in parallel, and a wiring 64 of a ground potential that is arranged so as to surround the periphery of these wirings.

  Since the dummy TEG 61 is thus provided, when the electron beam is irradiated for the VC inspection, the electron beam is also irradiated to the upstream and downstream regions of the TEG 51 due to insufficient positioning accuracy. Therefore, it is possible to avoid the problem that the area other than the TEG 51 is charged up.

  FIG. 7 is a diagram schematically showing a sixth embodiment of a semiconductor device according to the present invention, in which a TEG for detecting a short circuit failure and a TEG for detecting a disconnection failure are arranged in one wiring layer. It is a thing. As shown in the figure, a TEG 51 shown in FIG. 4 is used as a TEG for detecting a short circuit failure, and a TEG 71 having a pattern with a low risk of occurrence of a disconnection failure is used as the TEG for detecting a disconnection failure. The TEG 71 includes three TEG regions 72, 73, and 74, and each TEG region has four pairs of wirings that are at the ground potential. As shown in the figure, the line width is the largest in the TEG region 72 and the smallest in the TEG region 74.

  In the sixth embodiment, the TEG 51 for detecting the short circuit failure is arranged upstream of the TEG 71 for detecting the disconnection failure when viewed from the electron beam scanning direction. The TEG 51 causes the disconnection failure more than the TEG 71. This is because the danger is low, and therefore there is little risk of fluctuation of the semiconductor surface potential due to the floating potential region.

  As described above, when a TEG for detecting a disconnection failure is disposed, it is preferable to dispose a TEG having a low risk of occurrence of a disconnection failure on the upstream side in the electron beam scanning direction in the VC inspection. Moreover, when there are TEG regions having different line widths such as the TEG 51, a TEG region having a larger line width is less likely to cause a disconnection failure. Therefore, it is preferable to arrange a TEG region having a larger line width upstream.

  Further, in such a TEG for detecting disconnection failure, relative to the vicinity of the mirror symmetry axis of the TEG so that many secondary electrons are emitted in response to the electron beam irradiation, and thus a large VC inspection signal can be obtained. A large area pad structure 75 is formed. Therefore, only the vicinity of the pad structure 75 needs to be inspected in order to detect whether or not the TEG has a short circuit defect.

  Although various TEGs according to the present invention have been described above, when there is a narrow scribe area around the product die, the inspection time can be shortened by optimally arranging the TEG in the scribe area. For example, in FIG. 8, there are four dies 81 to 84 in one exposure field, and a plurality of TEGs (for example, TEG 31 in FIG. 2) are arranged in the same direction in the scribe regions 85 to 87 around each die. Shows the case. However, FIG. 8 shows a case where each die has a small scribe area and a sufficient TEG cannot be arranged. Therefore, TEGs are arranged in the same direction in all the scribe areas 85 to 87 in the exposure field in units of exposure fields in which dies are arranged.

  Here, the relationship between the region of the electron beam irradiated for scanning the TEG and the TEG will be described. In general, an insulating film and a wiring having a floating potential exist around a region where the TEG is disposed. Therefore, these insulating films and wirings are disadvantageously charged when irradiated with an electron beam. Therefore, as shown in FIG. 9, when scanning the TEG 91 with an electron beam, the size of the area 92 irradiated with the electron beam at a certain moment is appropriately selected, and the electron beam passes through the TEG 91 from one end to the other end. It is preferable to prevent the electron beam from irradiating the region outside the TEG 91 when scanning with the direction alternately changed in the column direction.

  However, there is a restriction on the size and arrangement of the TEG, and the electron beam may not be narrowed down. Therefore, the electron beam may irradiate the outside of the TEG. In such a case, it is preferable to surround the periphery of the TEG 91 with a ground wire 93 as shown in FIG.

  Although various TEG groups according to the present invention have been described above, this is merely an example in nature, and the present invention is not limited to these examples. A person skilled in the art can conceive various variations and modifications, which are included in the scope of the claims.

(A-1) to (A-3) schematically show the structures of three types of wiring short-circuit detection TEGs for measuring the short-circuit-proof dimension margin according to the present invention. It is sectional drawing of one TEG. 1 is a diagram schematically illustrating a first embodiment of a semiconductor device according to the present invention, and includes TEGs in which two types of wirings having different potentials are alternately and symmetrically arranged. FIG. 6 is a diagram schematically showing a second embodiment of a semiconductor device according to the present invention, and includes a TEG in which the TEG shown in FIG. 2 is arranged on a large scale. FIG. 3 is a diagram schematically showing a third embodiment of a semiconductor device according to the present invention, and includes three TEG regions having two pairs of wirings facing each other. FIG. 10 is a diagram schematically showing a fourth embodiment of a semiconductor device according to the present invention, which is an extension of the TEG shown in FIG. 4. FIG. 6 is a diagram schematically showing a fifth embodiment of a semiconductor device according to the present invention, which includes a dummy TEG. FIG. 10 is a diagram schematically showing a fifth embodiment of a semiconductor device according to the invention; FIG. 10 is a diagram schematically showing a fifth embodiment of a semiconductor device according to the invention; FIG. 10 is a diagram schematically showing a fifth embodiment of a semiconductor device according to the invention; FIG. 10 is a diagram schematically showing a fifth embodiment of a semiconductor device according to the invention; It is a figure for demonstrating one conventional test | inspection method for detecting the electrical failure which arises in the wiring of a semiconductor device.

Explanation of symbols

11, 12, 13: first wiring 141, 142, 151, 152, 161, 162: second wiring 143, 153, 163: third wiring 18: first wiring layer 19: contact 20: substrate 21: Active region 31, 41, 51, 71: TEG
32, 93: TEG frame 61: Dummy TEG
85, 86, 87: Scribe area

Claims (11)

  A plurality of wirings arranged symmetrically and parallel to the axis so that one end faces each other are provided, the other wirings of the plurality of wirings are grounded at the other end, and the remaining wirings are at a floating potential. A semiconductor device comprising a wiring pattern including at least one TEG.   A wiring pattern including a plurality of wirings arranged symmetrically and in parallel with respect to an axis so that one end faces each other, and including a wiring pattern including at least one TEG connected to the ground electrode at the other end of the plurality of wirings. A featured semiconductor device.   The plurality of wirings are provided in a first wiring layer, and the ground electrode is provided in a second wiring layer different from the first wiring layer, and the space between the plurality of wirings and the ground electrode is provided. The semiconductor device according to claim 2, wherein the semiconductor devices are connected by vias.   The semiconductor device according to claim 1, further comprising a wiring at a ground potential or a floating potential provided in a region having a predetermined width centered on the axis.   The semiconductor device according to claim 1, further comprising a wiring pattern in which a plurality of the TEGs are arranged in a predetermined direction.   6. The semiconductor device according to claim 5, wherein TEGs of multiples of 2 or powers of 2 are arranged in the predetermined direction. A semiconductor device according to claim 5 or 6,
The design parameters such as the line width and distance between the plurality of TEGs are different from each other,
A semiconductor device, wherein a plurality of the TEGs are arranged in ascending order of occurrence of disconnection failure in the electron beam scanning direction during inspection by potential contrast.   8. The semiconductor device according to claim 7, wherein the plurality of TEGs are arranged over a plurality of wiring layers, and the TEGs arranged in the same wiring layer are continuously arranged in an electron beam scanning direction at the time of inspection by potential contrast. A semiconductor device which is arranged.   9. The semiconductor device according to claim 1, wherein a region having a predetermined width including the axis and the opposing ends of the plurality of wirings is irradiated with an electron beam and emitted from the region. An inspection method, wherein a defective portion is detected based on a potential contrast signal corresponding to the amount of secondary electrons.   10. The semiconductor device according to claim 9, wherein the electron beam is scanned in a direction parallel to the axis and sequentially shifted in position, corresponding to the amount of secondary electrons emitted in response to the electron beam irradiation. An inspection method, wherein defective portions are continuously detected based on a potential contrast signal to be detected.   The inspection method according to claim 9 or 10, wherein a plurality of regions located at predetermined intervals in a direction perpendicular to the axis line are simultaneously irradiated with an electron beam to continuously detect defective portions. Inspection method.