JP2007295198A - Voltage-controlled oscillation circuit and its adjustment method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage-controlled oscillation circuit capable of accurately adjusting the amount of change of a frequency with respect to a control voltage concerning the voltage-controlled oscillation circuit and its adjustment method. <P>SOLUTION: The voltage-controlled oscillation circuit includes: a variable capacitor where a capacitance component is controlled in response to the control voltage; a serial capacitor serially connected to the variable capacitor; a parallel capacitor connected to a serial circuit in parallel, which is composed of the variable capacitor and the serial capacitor; and an inductor which is connected to the serial circuit in parallel composed of the variable capacitor and the serial capacitor, so as to constitute an inductive component. The serial capacitor and the parallel capacitor are respectively exchangeable in capacitance components. When the capacitance component of the serial capacitor and that of the parallel capacitor are exchanged, the amount of change of the oscillation frequency with respect to the control voltage is adjusted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a voltage-controlled oscillation circuit and a method for adjusting the same, and more particularly, a variable capacitance element whose capacitance component is controlled according to a control voltage, and a series capacitance that is connected in series to the variable capacitance element and cuts the control voltage. An inductive component connected in parallel to a series capacitor composed of an element, a parallel capacitor connected in parallel to a series circuit composed of a variable capacitor and a series capacitor, and a variable capacitor and a series capacitor. The present invention relates to a voltage controlled oscillation circuit including

  In an integrated voltage controlled oscillator circuit, the oscillation frequency varies due to variations in the manufacturing process. For this reason, oscillation frequency trimming or adjustment is required.

  FIG. 10 shows a circuit configuration diagram of a voltage controlled oscillation circuit using LC.

  The voltage-controlled oscillation circuit 10 using LC includes an inductor L, variable capacitance diodes Cv11 and Cv12, capacitors Cs11, Cs12, Cp11 and Cp12, and transistors Q11 to Q14.

  The voltage-controlled oscillation circuit 10 using LC is configured by an inductor L, variable capacitance diodes Cv11, Cv12, and fixed capacitors Cs11, Cs12, Cp11, Cp12, with the capacitances of the variable capacitance diodes Cv11, Cv12 being changed by the control voltage Vcnt. The oscillation frequency changes as the resonance frequency of the resonance circuit changes.

  The transistors Q11 and Q13 and the transistors Q12 and Q14 each constitute a CMOS inverter, and are connected between both ends of the resonance circuit so that their inputs and outputs are opposite to each other.

  The fixed capacitors Cs11 and Cs12 are capacitors for cutting the DC bias applied to the variable capacitance diodes Cv11 and Cv12.

  In the voltage control circuit 10 using such LC, the capacitances of the fixed capacitors Cp11 and Cp12 are varied in order to correct the frequency variation with respect to the control voltage.

  FIG. 11 is a characteristic diagram of the frequency with respect to the control voltage of the voltage controlled oscillation circuit 10.

  The voltage controlled oscillation circuit 10 can compress the high frequency band component with respect to the control voltage as shown by the solid line and the alternate long and short dash line in FIG. 11 by changing the capacitance of the fixed capacitors Cp11 and Cp12.

  Therefore, conventionally, the amount of change in the frequency with respect to the control voltage is adjusted by controlling the change in the high frequency band component with respect to the control voltage by changing the setting of the capacitances of the fixed capacitors Cp11 and Cp12.

  As a voltage-controlled oscillator of this type, a switchable capacitor is provided between both ends of the varactor connected in parallel to the inductor and the ground, and the bias is controlled according to the adjustment capacitor to stabilize the operating point. There has been proposed a voltage controlled oscillator (see Patent Document 1).

Further, as a different technical field, a variable capacitance modulator is proposed in which a switched trim capacitor is provided between a connection point between a varactor and a coupling capacitor and ground (see Patent Document 2).
JP 2004-266571 A JP 2005-253066 A

  However, in the conventional voltage controlled oscillation circuit, when adjusting the relationship of the frequency to the control voltage, the high frequency band side is compressed as shown in FIG. 11 by changing the capacitance of the fixed capacitors Cp11 and Cp12. As a result, the amount of change in the oscillation frequency with respect to the control voltage could not be adjusted to a desired characteristic.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a voltage controlled oscillation circuit that can freely adjust the amount of change in frequency with respect to a control voltage, and an adjustment method thereof.

  The present invention includes variable capacitance elements (Cv1, Cv2) whose capacitance components are controlled according to a control voltage (Vcnt), and series capacitance elements (Cs1, Cs2) connected in series to the variable capacitance elements (Cv1, Cv2). A parallel capacitance element (Cp1, Cp2) connected in parallel to a series circuit composed of a variable capacitance element (Cv1, Cv2) and a series capacitance element (Cs1, Cs2), and a variable capacitance element (Cv1, Cv2) In a voltage controlled oscillation circuit having an inductive component (L) connected in parallel to a series circuit composed of a series capacitance element (Cs1, Cs2), a series capacitance element (Cs1, Cs2) and a parallel capacitance element (Cp1) , Cp2) are configured such that their capacitance components can be switched, and the control voltage (Vcnt) can be switched by switching the capacitance components of the series capacitance elements (Cs1, Cs2) and the parallel capacitance elements (Cp1, Cp2). ) Is the amount of change in oscillation frequency Characterized in that it is an integer.

  The series capacitance elements (Cs1, Cs2) and the parallel capacitance elements (Cp1, Cp2) switch the connection between the plurality of capacitors (C0, C1 to C4) and the plurality of capacitors (C0, C1 to C4), respectively. It is characterized by comprising switch means (SW1 to SW4).

  Further, by changing the capacitance components of the series capacitive elements (Cs1, Cs2) and the parallel capacitive elements (Cp1, Cp2), the amount of change in the oscillation frequency with respect to the control voltage (Vcnt) can be changed to the low frequency band side and the high frequency band side. It is characterized by being adjusted so as to be even.

  The present invention also provides variable capacitance elements (Cv1, Cv2) whose capacitance components are controlled according to the control voltage (Vcnt) and series capacitance elements (Cs1, Cv2, Cv1, Cv2) connected in series to the variable capacitance elements (Cv1, Cv2). Cs2), parallel capacitive elements (Cp1, Cp2) connected in parallel to a series circuit composed of variable capacitive elements (Cv1, Cv2) and series capacitive elements (Cs1, Cs2), and variable capacitive elements (Cv1, In a method for adjusting a voltage controlled oscillation circuit having an inductive component connected in parallel to a series circuit composed of Cv2) and series capacitance elements (Cs1, Cs2), the series capacitance elements (Cs1, Cs2) and the parallel capacitance elements (Cp1, Cp2) are configured so that their capacitance components can be switched, and the control voltage (Cp1, Cp2) can be switched by switching the capacitance components of the series capacitance elements (Cs1, Cs2) and the parallel capacitance elements (Cp1, Cp2). Of the oscillation frequency for Vcnt) And adjusting the reduction amount.

  In addition, by switching the capacitance components of the series capacitance elements (Cs1, Cs2) and the capacitance components of the parallel capacitance elements (Cp1, Cp2), the amount of change in the oscillation frequency with respect to the control voltage (Vcnt) can be reduced. It adjusts so that it may become equal on the side.

  In addition, the said reference code is a reference to the last, and description of a claim is not limited by this.

  According to the present invention, the series capacitive element and the parallel capacitive element can each switch their capacitance components, and the change amount of the oscillation frequency with respect to the control voltage is switched by switching the capacitive component of the series capacitive element and the capacitive component of the parallel capacitive element. By adjusting this, it is possible to set the amount of change in frequency with respect to the control voltage relatively freely.

  FIG. 1 is a circuit diagram showing an embodiment of the present invention.

  The voltage controlled oscillation circuit 100 of the present embodiment includes an inductor L, variable capacitance elements Cv1, Cv2, series capacitance elements Cs1, Cs2, parallel capacitance elements Cp1, Cp2, transistors Q1-Q4, and a bias circuit 111.

  The variable capacitance elements Cv1, Cv2 are composed of variable capacitance diodes. The variable capacitor Cv1 has a cathode connected to the variable capacitor Cv2, and an anode connected to one end of the series capacitor Cs1. The variable capacitor Cv2 has a cathode connected to the cathode of the variable capacitor Cv1, and an anode connected to one end of the series capacitor Cs2.

  A control voltage Vcnt is supplied to a connection point between the cathode of the variable capacitor Cv1 and the cathode of the variable capacitor Cv2. The anodes of the variable capacitance elements Cv1 and Cv2 are connected to the bias circuit 111, and bias voltages Vb1 and Vb2 are applied from the bias circuit 111.

  As a result, the capacitances of the variable capacitance elements Cv1 and Cv2 change according to the difference voltage between the control voltage Vcnt and the bias voltages Vb1 and Vb2. As the capacitances of the variable capacitance elements Cv1 and Cv2 change, the capacitance component changes, and the amount of change in the oscillation frequency with respect to the control voltage Vcnt changes.

  The bias circuit 111 is composed of resistors R11, R21, R22, and a diode D1. The resistor R11 has one end applied with the power supply voltage Vcc and the other end connected to the anode of the diode D1. The diode D1 has an anode connected to the other end of the resistor R11 and a cathode grounded. The power supply voltage Vcc is applied to the diode D1 via the resistor R11, and a forward voltage is generated at a connection point with the resistor R11. The forward voltage generated at the connection point between the diode D1 and the resistor R11 is applied to the connection point between the anode of the variable capacitive element Cv1 and one end of the series capacitive element Cs1 via the resistor R21, and via the resistor R22. The voltage is applied to a connection point between the anode of the variable capacitor Cv2 and one end of the series capacitor Cs1. As a result, the anodes of the variable capacitance elements Cv1 and Cv2 are biased.

  At this time, the forward voltage of the diode D1 has a negative temperature characteristic. Therefore, a positive temperature coefficient is given to the bias voltage applied to the variable capacitance element, and a negative temperature coefficient is given to the capacitance. In general, the capacitance of the variable capacitance element has a positive temperature coefficient and can be canceled out.

  FIG. 2 is a block diagram of the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2.

  The series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 are composed of capacitors C0 and C1 to C4 and switches SW1 to SW4. Capacitors C1 to C4 are connected in parallel to the capacitor C0 via switches SW1 to SW4.

  By turning on the switch SW1, the capacitor C1 is connected in parallel with the capacitor C0. By turning on the switch SW2, the capacitor C2 is connected in parallel with the capacitor C0. By turning on the switch SW3, the capacitor C3 is in parallel with the capacitor C0. The capacitor C4 is connected in parallel to the capacitor C0 by turning on the switch SW4. The series capacitance elements Cs1 and Cs2 and the parallel capacitance elements Cp1 and Cp2 can be switched in capacity so that the capacitance increases by turning on the switches SW1 to SW4.

  By adjusting the capacitances of the series capacitive elements Cs1 and Cs2 and the capacitances of the parallel capacitive elements Cp1 and Cp2, the frequency change on the low frequency band side and the frequency change on the high frequency band side with respect to the control voltage can be equalized. As a result, the frequency can be changed linearly with respect to the control voltage.

[Application example]
FIG. 3 is a block diagram showing an application example of one embodiment of the present invention.

  The PLL circuit 200 of this application example is mounted on, for example, a one-chip semiconductor device. From the voltage-controlled oscillation circuit 100, the frequency divider 211, the phase comparator 212, the loop filter 213, and the control circuit 215 of this example. It is configured.

  The oscillation output fout of the voltage controlled oscillation circuit 100 is output from the output terminal Tout and supplied to the frequency divider 211. The frequency divider 211 divides the oscillation output of the voltage controlled oscillation circuit 100. The signal divided by the frequency divider 211 is supplied to the phase comparator 212.

  The phase comparator 212 is supplied with the reference oscillation signal fref from the reference oscillator 213, compares the signal supplied from the frequency divider 211 with the reference oscillation signal fref from the reference oscillator 213, and according to the phase difference. Output a phase difference signal. The phase difference signal of the phase comparator 212 is supplied to the loop filter 214.

  It is composed of a loop filter 2134, a low-pass filter, and an integration circuit, and outputs a signal obtained by removing high-frequency components from the phase difference signal. The output of the loop filter 214 is supplied to the voltage controlled oscillation circuit 100 as the control voltage Vcnt. The voltage controlled oscillation circuit 100 controls the oscillation frequency according to the control voltage Vcnt supplied from the loop filter 214.

  Thus, the PLL circuit 200 can output the oscillation output fout that is phase-synchronized with the reference oscillation signal fref.

  The control circuit 215 performs band switching and processing for adjusting the capacitances of the series capacitance elements Cs1 and Cs2 and the capacitances of the parallel capacitance elements Cp1 and Cp2 in accordance with an instruction from the outside.

[Adjustment operation]
Next, the adjustment process of the output frequency with respect to the control voltage of the voltage controlled oscillation circuit 100 by the control circuit 215 will be described.

  FIG. 4 shows a process flowchart of the adjustment process by the control circuit 215.

  First, in step S1-1, the control circuit 215 performs rough adjustment of the output frequency with respect to the control voltage in a predetermined band. Next, the control circuit 215 executes a cover range measurement process for measuring the cover range in step S1-2. The cover range measurement process is a process for measuring the cover range of the selected band.

  The cover range measurement process will be described later with reference to the drawings.

  Next, the control circuit 215 executes a modulation sensitivity adjustment process for adjusting the modulation sensitivity in Step 1-3. The modulation sensitivity adjustment process is a process for adjusting the modulation sensitivity to be within a specified range by switching the series capacitive elements Cs1 and Cs2.

  Next, in step S1-4, the control circuit 215 executes a cover range adjustment process for adjusting the cover range by switching the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2. The cover range adjustment process is a process of switching the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 so that the minimum frequency fmin and the maximum frequency fmax measured by the cover range measurement process are within specified values.

  When the adjustment in steps S1-1 to S1-4 is completed for all bands in step S1-5, the control circuit 215 determines the adjustment values of the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 in step S1-6. To do.

  Next, the control circuit 215 confirms the cover range in step S1-7. If the cover range satisfies the standard in step S1-8, the control circuit 215 terminates the processing. If the standard does not satisfy the standard, step S1- In step 9, an error notification is issued to the outside.

  Next, the rough adjustment process in step S1-1 will be described.

  FIG. 5 shows a process flowchart of the coarse adjustment process.

  In the coarse adjustment process, the reference oscillation signal fref of the reference oscillator 213 and the frequency division ratio of the frequency divider 211 are set to predetermined values in step S2-1, and a PLL is applied.

  Next, the control circuit 215 controls the switches SW1 to SW4 of the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 in steps S2-2 and S2-3, and the parallel capacitances of the series capacitive elements Cs1 and Cs2. While switching the capacities of the elements Cp1 and Cp2, the control voltage Vcnt is monitored, and the capacities of the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 are adjusted so that the control voltage Vcnt approximates the reference voltage Vref.

  Thus, the rough adjustment is completed.

  Next, the cover range measurement process in step S1-2 will be described.

  FIG. 6 shows a process flowchart of the cover range measurement process.

  First, the control circuit 215 controls the frequency divider 211 in step S3-1 to vary the PLL set frequency, and in step S3-2, the minimum frequency fmin and the maximum voltage when the control voltage Vcnt is the minimum voltage Vmin. The frequency fmax at Vmax is detected.

  The control circuit 215 determines whether or not the minimum frequency fmin and the maximum frequency fmax detected in step S3-3 are within the set frequency range. The control circuit 215 ends the process when the minimum frequency fmin and the maximum frequency fmax are within the set frequency range in step S3-3, and when the minimum frequency fmin and the maximum frequency fmax are outside the set frequency range, the control circuit 215 performs the process in step S3-4. Issue an error notification to the outside.

  The cover range measurement is thus completed.

  Next, the modulation sensitivity adjustment process in step S1-3 will be described.

  FIG. 7 shows a process flowchart of the modulation sensitivity adjustment process.

  In step S4-1, the control circuit 215 calculates the modulation sensitivity from the minimum frequency fmin and the maximum frequency fmax, and the minimum value Vmax and the maximum value Vmin of the control voltage.

The modulation sensitivity k is obtained by dividing the difference between the minimum frequency fmin and the maximum frequency fmax by the difference between the minimum value Vmax and the maximum value Vmin of the control voltage.
k = (fmax−fmin) / (Vmax−Vmin)
Is required.

  In step S4-2, the control circuit 215 determines whether the modulation sensitivity is within a specified range. If the modulation sensitivity is within the specified range in step S4-2, the control circuit 215 ends the process. If the modulation sensitivity is not within the specified range in step S4-2, the control circuit 215 determines whether or not the modulation sensitivity calculation count is a predetermined count in step S4-3.

  If the number of modulation sensitivity adjustments is within the predetermined number in step S4-3, the control circuit 215 performs the coarse adjustment process in step S1-1 and the cover range measurement process in step S1-2 in steps S4-4 and S4-5. The process returns to step S4-1 to detect the modulation sensitivity k again. When the number of modulation sensitivity adjustments reaches a predetermined number in step S4-3, the control circuit 215 issues an error notification to the outside in step S4-6 and ends the process.

  The modulation sensitivity adjustment process is thus completed.

  Next, the cover range adjustment process in step S1-4 will be described.

  FIG. 8 shows a process flowchart of the cover range adjustment process.

  The control circuit 215 switches the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 in step S5-1, and in step S5-2, the guard band which is the difference between the minimum frequency fmin and the band fBL adjacent to the low frequency side. gb1 = (fmin−fBL) and a guard band gb2 = (fmax−fBH) which is a difference between the maximum frequency fmax and the band fBH adjacent to the high frequency side is detected.

  The control circuit 215 obtains the capacities of the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 when the guard band deviation (gb1 + gb2) is minimized in step S5-3. The set values of the series capacitive elements Cs1, Cs2 and the parallel capacitive elements Cp1, Cp2 are set to adjustment values.

  Thus, the cover range adjustment process ends.

  FIG. 9 is a characteristic diagram of the oscillation frequency with respect to the control voltage.

  According to the present embodiment, by switching the capacitances of the series capacitive elements Cs1 and Cs2 as shown in FIG. 9, the low frequency band centered on the center voltage Vcnt0 of the control voltage Vcnt as shown by the solid line and the broken line in FIG. The characteristic can be switched symmetrically on the side and the high frequency band side.

  As described above, according to the present embodiment, the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 are configured so that their capacitive components can be switched, and the capacitive elements of the series capacitive elements Cs1 and Cs2 and the parallel capacitive elements Cp1 and Cp2 By switching the capacitance component and adjusting the amount of change in the oscillation frequency with respect to the control voltage Vcnt, it becomes possible to set the amount of change in the frequency with respect to the control voltage Vcnt relatively freely.

  According to the present embodiment, since the amount of change in the oscillation frequency with respect to the control voltage Vcnt can be made linear, the loop characteristics of the PLL circuit can be greatly improved. As a result, the required oscillation frequency range can be surely kept within the control voltage range, so that the center of the oscillation frequency and the center of the control voltage can be reliably matched. The range can be expanded.

  The present invention is not limited to the above-described embodiments, and various modifications can be considered without departing from the scope of the claims of the present invention.

It is a circuit block diagram of one Example of this invention. It is a block block diagram of series capacitive elements Cs1 and Cs2 and parallel capacitive elements Cp1 and Cp2. It is a block block diagram of the example of application of one Example of this invention. 10 is a process flowchart of an adjustment process by a control circuit 215. It is a processing flowchart of rough adjustment processing. It is a process flowchart of a cover range measurement process. It is a process flowchart of a modulation sensitivity adjustment process. It is a process flowchart of a cover range adjustment process. It is a figure for demonstrating adjustment operation | movement. It is a circuit block diagram of the voltage controlled oscillation circuit using LC. It is a characteristic figure of the oscillation frequency with respect to the conventional control voltage.

Explanation of symbols

100 voltage controlled oscillation circuit 111 bias circuit L inductor Cv1, Cv2 variable capacitance element, Cs1, Cs2 series capacitance element, Cp1, Cp2 parallel capacitance element Q1-Q4 transistor

Claims (5)

A variable capacitance element whose capacitance component is controlled according to a control voltage, a series capacitance element connected in series to the variable capacitance element, and a series circuit composed of the variable capacitance element and the series capacitance element are connected in parallel. In a voltage-controlled oscillation circuit having an inductive component connected in parallel to a series circuit composed of a connected parallel capacitive element, the variable capacitive element and the series capacitive element,
Each of the series capacitive element and the parallel capacitive element is configured to be capable of switching its capacitive component,
A voltage-controlled oscillation circuit, wherein a change amount of an oscillation frequency with respect to the control voltage is adjusted by switching a capacitance component of the series capacitance element and a capacitance component of the parallel capacitance element. Each of the series capacitor element and the parallel capacitor element includes a plurality of capacitors,
2. The voltage controlled oscillation circuit according to claim 1, comprising switch means for switching connection of the plurality of capacitors. By switching the capacitive component of the series capacitive element and the capacitive component of the parallel capacitive element, the amount of change in the oscillation frequency with respect to the control voltage is adjusted to be equal between the low frequency band side and the high frequency band side. The voltage controlled oscillation circuit according to claim 1, wherein A variable capacitance element whose capacitance component is controlled according to a control voltage, a series capacitance element connected in series to the variable capacitance element, and a series circuit composed of the variable capacitance element and the series capacitance element are connected in parallel. In a method for adjusting a voltage-controlled oscillation circuit having an inductive component connected in parallel to a series circuit composed of a connected parallel capacitive element, the variable capacitive element and the series capacitive element,
The series capacitive element and the parallel capacitive element are each configured to be capable of switching its capacitive component,
A method for adjusting a voltage-controlled oscillation circuit, characterized by adjusting a change amount of an oscillation frequency with respect to the control voltage by switching a capacitance component of the series capacitance element and a capacitance component of the parallel capacitance element. By switching between the capacitive component of the series capacitive element and the capacitive component of the parallel capacitive element, the amount of change in the oscillation frequency with respect to the control voltage is adjusted to be equal between the low frequency band side and the high frequency band side. The method for adjusting a voltage controlled oscillation circuit according to claim 4.

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