JP2007294815A - Visual inspection method and apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a visual inspection method and a visual inspection apparatus that allows for an easy focus correction while dealing with a warpage of a wafer and significant reduction of inspection time when imaging inspection images of each portion of the wafer. <P>SOLUTION: The mark focus point of an alignment pattern used when aligning a wafer (P1) is measured (P2). A warpage shape of the wafer is obtained based on the mark focus point. Each focus position in each portion of each surface of the wafer to be inspected is calculated from the warpage shape (P3). Therefore, it becomes unnecessary to perform focus adjustment (focusing) for each portion of the surface of the wafer to be inspected. In other words, the focus position in each portion of the wafer can be obtained without taking time to focus each portion of the wafer. This allows an easy focus correction while dealing with the warpage of the wafer, which has holes or the back of which was supposed to be difficult to be contacted, and significantly reduces the time required to visually inspect the wafer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to focus correction in the case where an in-focus position shift occurs between each part of a wafer due to the warp of the wafer when an inspection image of each part of the wafer used for appearance inspection of a semiconductor wafer or the like is taken.

  Conventionally, in the appearance inspection of a semiconductor wafer in which a semiconductor integrated circuit is mounted and separated into a large number of IC (Integrated Circuit) chips, each part of the wafer is imaged with a CCD (charge-coupled device) camera or the like. Image processing is performed for each inspection image. When each inspection image is captured, it is necessary to deal with a focus shift due to wafer warpage. As one countermeasure, for example, as shown in FIGS. 8A and 8B, the warped wafer W is vacuum-chucked by the jig J, and the entire wafer W as shown in FIG. There is a method of correcting to a flat state. If the warpage of the wafer W is corrected in this way, it is only necessary to focus at one location such as the center of the wafer W, so that the processing is simple. In FIGS. 8 and 9, the degree of warping of the wafer is emphasized.

On the other hand, since the imaging of the wafer is performed for each part when the surface to be inspected is divided into a plurality of imaging ranges, the wafer warp is dealt with by focusing on each part of the surface to be inspected. There is also a method. As a known focusing method, for example, a light beam is irradiated from a laser light source through a focusing lens, and the light beam reflected by the inspected surface of the wafer is collected by the lens. Based on the detection signal of the photoelectric sensor, the focus lens is driven by a motor (Patent Document 1).
Alternatively, an inspection alignment mark is formed in the center of the wafer, and the inspection alignment mark is monitored by an image processing apparatus at each position (height) when the wafer is moved up and down. Focus adjustment is performed by setting a position (height) at which the contrast of the image signal of the alignment mark is maximized as a focus position (Patent Document 2).

JP-A-5-5827 Japanese Patent Laid-Open No. 5-21318

  Incidentally, some semiconductor wafers have holes H as shown in FIGS. 9A and 9B, and vacuum chucking is impossible in such a holed wafer. In addition, even in a semiconductor wafer having no holes, if the jig cannot be allowed to contact the back side, the warp cannot be corrected by a vacuum chuck or the like. As described above, when the wafer warp cannot be mechanically corrected, in order to cope with the wafer warp, a method of adjusting the focus for each part of the wafer may be employed. However, as in Patent Documents 1 and 2, it takes a lot of time and effort to perform focusing processing with vertical movement of the focus lens and the wafer for each part of the wafer.

  In view of such problems, the object of the present invention is to easily perform focus correction while coping with the wafer warp even when the wafer warp cannot be mechanically corrected when capturing inspection images of each part of the wafer. An object of the present invention is to provide a wafer appearance inspection method and an appearance inspection apparatus capable of greatly reducing time.

  The wafer appearance inspection method of the present invention is a wafer appearance inspection method for performing image processing based on each inspection image when each part of the inspection surface of the wafer is imaged by an imaging means, An alignment step of positioning the wafer at a reference position using an alignment mark formed on a surface; a mark focus position measurement step of measuring a mark focus position of the imaging means for the alignment mark; and the mark focus Each part in-focus position calculating step for obtaining a warp shape of the wafer based on the position, and calculating each part in-focus position of the image pickup means for each part of the surface to be inspected based on the warp shape; and An inspection image capturing step for capturing each inspection image at the respective in-focus positions for each of the respective sections.

  In addition, the wafer appearance inspection apparatus of the present invention includes an imaging means for obtaining each inspection image by imaging each part of the surface to be inspected of the wafer, and an image inspection apparatus for processing each inspection image. An alignment unit for positioning the wafer at a reference position using an alignment mark formed on a surface to be inspected of the wafer, and an alignment mark for measuring a mark focusing position of the imaging unit with respect to the alignment mark In-focus position measuring means, each part for obtaining the warp shape of the wafer based on the mark in-focus position, and for calculating the in-focus position of each part of the imaging means for each part of the surface to be inspected based on the warp shape Focusing position calculation means, and the imaging means picks up each inspection image at the focus position of each part for each part.

According to these inventions, the mark focus position of the alignment mark used when aligning the wafer to the reference position is measured, the warp shape of the wafer is obtained based on the mark focus position, and the wafer is obtained from the warp shape. Therefore, it is not necessary to perform focus adjustment (focusing) for each part of the surface to be inspected of the wafer.
That is, the wafer part including the alignment mark is monitored at the time of alignment, but it is only necessary to measure the mark in-focus position for the alignment mark at substantially the same timing as the alignment or immediately after the alignment. Thus, the configuration of the image processing is simplified, and the processing efficiency is improved. That is, the alignment process and the mark focus position measurement process, or the alignment means and the mark focus position measurement means can be processed at substantially the same timing. In the present invention, each part of the wafer is focused. In this way, the in-focus position in each part of the wafer can be obtained, so that focus correction corresponding to the warp of the wafer can be performed quickly.
As described above, even for wafers that have holes or that cannot be contacted on the back side, it is possible to easily perform focus correction while dealing with wafer warpage when capturing inspection images of each part of the wafer, which is necessary for visual inspection of the wafer. Time can be greatly reduced.

  In the wafer appearance inspection method of the present invention, a plurality of the alignment marks are provided, and in each in-focus position calculation step, an approximate expression is obtained for the mark in-focus position of each alignment mark, and the warped shape is determined by the approximate expression. Is preferably represented.

  According to the present invention, it is possible to perform the focus correction more appropriately by deriving an approximate expression for each mark in-focus position of each of the plurality of alignment marks.

  In the wafer visual inspection apparatus of the present invention, it is preferable that three or more alignment marks are provided at different positions in the X direction and the Y direction within the surface to be inspected.

  According to the present invention, since it is possible to grasp both the X-direction warp and the Y-direction warp on the surface to be inspected by using three or more alignment marks, the focus correction can be performed more appropriately.

  In the wafer appearance inspection apparatus according to the present invention, it is preferable that the alignment mark is formed as a semiconductor pattern formed on any of a plurality of chips into which the wafer is separated.

  According to the present invention, the semiconductor pattern formed on the chip can also be used as an alignment mark.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic external view of the configuration of an appearance inspection apparatus 1 according to this embodiment. FIG. 2 is a schematic plan view of the wafer 2 to be inspected by the appearance inspection apparatus 1.
The appearance inspection apparatus 1 includes a table 3 on which a semiconductor wafer 2 is installed, a drive device 31 that drives the table 3 in the X direction and the Y direction, and an imaging unit that is provided above the table 3 and images the wafer 2. A color CCD camera 4 and an image processing device 5 having a monitor 5A are provided. Note that the wafers 2 are sequentially transferred onto the table 3 by the transfer device 6.

  The image processing device 5 is connected to the camera 4, the driving device 31 of the table 3, and the transport device 6, and an image captured by the camera 4 is taken into a processing unit inside the image processing device 5. The image processing device 5 synchronizes the camera 4 and the driving device 31. When the wafer 2 is imaged, the driving device 31 drives the table 3 in the X direction and the Y direction to move the camera 4. The wafer 2 is moved.

The wafer 2 has a substantially circular planar shape, and substantially the entire surface to be inspected 2A processed by etching or printing is inspected by the appearance inspection apparatus 1 and separated into a large number of chips 20 by dicing, slicing, or the like. . Each chip 20 is formed with a plurality of fine semiconductor patterns (not shown) constituting an integrated circuit. Further, holes (not shown) penetrating in the thickness direction are formed in the wafer 2 in a scattered manner.
Here, when the surface 2A to be inspected 2A (FIG. 2) of the wafer 2 is inspected, substantially the entire surface 2A to be inspected or a region where the chip 20 is cut out (in the case of FIG. Are divided into a plurality of imaging ranges (each part of the wafer). Note that the present invention is not limited to this embodiment, and each part of the wafer 2 may be imaged by moving the camera 4 relative to the table 3. In the present embodiment, the number of units that are imaging units on the wafer 2 is 1500 to 1600.

  On the outer periphery of the wafer 2, a linear orientation flat 2B formed for positioning on the table 3 is formed. In addition, alignment marks 2C and 2D for alignment to the reference position of the wafer 2 are formed on both ends in the radial direction of the wafer 2 on the outer peripheral portion of the wafer 2 to be inspected 2A that is not separated into individual chips 20. ing.

  Further, among the many chips 20, the chip 200 disposed near the plane center of the wafer 2 and the chips disposed on both ends of the X axis when the X coordinate and the Y coordinate are assumed in the plane direction of the surface 2 A to be inspected. Alignment patterns 21 as alignment marks are formed on a total of five chips 20Y1 and 20X2 and chips 20Y1 and 20Y2 arranged on both ends of the Y axis, respectively, as shown in an enlarged view in FIG. The alignment pattern 21 is a semiconductor pattern formed on the surface of the wafer 2 by etching or printing, and is circular in FIG. 3, but may be other shapes such as a rectangular shape, and further constitutes an integrated circuit. In other words, the pattern may be formed so as to serve both as a circuit and an alignment. In addition to the alignment pattern 21, a large number of semiconductor patterns constituting an integrated circuit are formed on the chip of FIG.

  Here, the alignment of the wafer 2 is performed in two stages of coarse alignment and fine alignment, and the orientation flat 2B and the alignment marks 2C and 2D on the outer periphery of the wafer 2 are used for the coarse alignment. For fine alignment, the alignment patterns 21 of the chips 200, 20X1, 20X2, 20Y1, and 20Y2 are used.

FIG. 4 is a block diagram showing the internal configuration of the image processing apparatus 5. The image processing apparatus 5 performs the focus alignment of the camera 4 for each of the alignment pattern 21 of each chip 200, 20X1, 20X2, 20Y1, and 20Y2, and the coarse alignment means 51 that performs coarse alignment, the fine alignment means 52 that performs fine alignment, and the alignment pattern 21 of each chip 200, 20X1, 20X2, 20Y1, and 20Y2. Mark focus position measuring means 53 for measuring the position and the warp shape of the wafer 2 based on each mark focus position, and each part focus position for each part of the inspection surface 2A of the wafer 2 based on this warp shape Each unit in-focus position calculating means 54 is provided. These means 51 to 54 are respectively read and executed by the control means 50 such as a CPU mounted on the image processing apparatus 5.
Each of the in-focus position calculation means 54 includes approximate expression creating means 541 that obtains an approximate expression for the mark focus position.

  Hereinafter, with reference to the flowchart of FIG. 5, processes up to capturing of the inspection image of the wafer 2 in the appearance inspection apparatus 1 will be described. The process generally includes an alignment process P1 for positioning the wafer 2 at a reference position, a mark focus position measurement process P2 for measuring the focus position of the alignment pattern 21, and a warp shape of the wafer 2. A focus correction step P3 for calculating the respective in-focus positions in the respective portions of the inspected surface 2A based on the shape; and an inspection image imaging step P4 for capturing an inspection image of the wafer 2 at each in-focus position calculated in the step P3; It is constituted by. Among these steps, the focus correction step P3 corrects the in-focus position for each part of the wafer 2 in response to the warpage of the wafer 2. This is because the wafer 2 of this embodiment has a hole (not shown) as described above, and thus a method of correcting the warp with a vacuum chuck or the like cannot be adopted.

The alignment process P1 includes a rough alignment process P11 and a fine alignment process P12. In the coarse alignment process P11, the alignment to the reference position of the wafer 2 is performed by the coarse alignment means 51 (FIG. 4) using the orientation flat 2B and the alignment marks 2C and 2D. In this embodiment, each of the in-plane X direction, the in-plane Y direction, and the in-plane rotation direction of the surface 2A to be inspected is driven by driving the table 3 through the image processing apparatus 5 or by manually observing the monitor 5A. Then, the wafer 2 is aligned.
Note that the alignment method is arbitrary, and for example, alignment can be performed by image processing using alignment reference pattern data prepared in advance for the master wafer. In addition, alignment may be performed by using a mask and aligning the holes formed in the mask with the alignment marks 2C and 2D.

  In the next fine alignment step P12, the fine alignment means 52 aligns the wafer 2 using the alignment patterns 21 of the chips 200, 20X1, 20X2, 20Y1, and 20Y2. In this fine alignment, the dimension of the alignment pattern 21 is smaller than the dimensions of the alignment marks 2C, 2D, etc. on the outer periphery of the wafer 2, and the number of alignment patterns 21 to be used is large (five). Accurately aligned. About the direction and method to align, you may be the same as that of the rough alignment process P11.

The subsequent mark focus position measurement step P2 includes the first mark focus position measurement step P21 to the fifth mark focus position measurement step P25.
In the first to fifth mark focus position measurement steps P21 to P25, the chip 200 is moved by the mark focus position measurement unit 53 with the movement step PM for moving the wafer 2 by driving the table 3 by the driving device 31. , 20X1, 20X2, 20Y1, and 20Y2 are performed for each alignment pattern 21.
The focusing method by the mark focusing position measuring means 53 at this time is arbitrary. For example, the distance between the camera 4 and the surface to be inspected 2A is adjusted by a moving mechanism provided in the camera 4, and each distance is adjusted. The focus position of the mark can be measured based on the brightness contrast of the captured monitor image.

FIG. 6 and FIG. 7 show approximate curves by the mark in-focus positions measured in the first to fifth mark in-focus position measuring steps P21 to P25 and their proportional distribution. The X direction in FIG. 6 and the Y direction in FIG. 7 correspond to the X direction and the Y direction in FIG. 2, respectively.
FIG. 6 shows mark focusing positions 20X1F, 200F, and 20X2F for the alignment patterns 21 of the chips 20X1, 200, and 20X2, respectively. Accordingly, it can be seen that the center of the wafer 2 is warped upward in the X direction when compared with the reference position B due to the influence of its own weight and the like.
Further, FIG. 7 shows mark focusing positions 20Y1F, 200F, and 20Y2F for the alignment patterns 21 of the chips 20Y1, 200, and 20Y2, respectively. Thus, it can be seen that the wafer 2 is warped upward in the center in the Y direction when compared with the reference position B due to the influence of its own weight and the like.

  Returning to FIG. 5, the focus correction step P3 includes a warp shape calculation step P31 for obtaining an approximate expression by the approximate expression creating means 541, and the camera 4 for each part of the wafer 2 based on the warp shape of the wafer 2 represented by the approximate expression. Each part in-focus position calculation step P32 for calculating the in-focus position. In the warp shape calculation step P31, as shown in FIGS. 6 and 7, approximate expressions for the mark in-focus positions 200F, 20X1F, 20X2F, 20Y1F, and 20Y2F are obtained by the approximate expression creating means 541, and the wafer is obtained from this approximate expression. Two warp shapes are represented. Then, in each subsequent in-focus position calculation step P32, based on this approximate expression, in-focus for each section when each in-focus position calculation means 54 divides the inspection surface 2A of the wafer 2 into a plurality of imaging ranges. A position is required.

  Through these processes P31 and P32, the inspection image capturing process P4 is reached. In this inspection image imaging process P4, the inspection surface 2A of the wafer 2 is imaged for each part by the camera 4 at the in-focus position in each part of the wafer 2 obtained in the process so far. The image processing apparatus 5 takes in the data. Subsequently, the image processing apparatus 5 performs defect detection, defect classification, and the like by a pattern matching method based on comparison with non-defective patterns and adjacent patterns based on each inspection image, and then the appearance inspection of the wafer 2 is finished.

The present embodiment described above has the following effects.
(1) According to the appearance inspection apparatus 1, the mark focus position of the alignment pattern 21 used when aligning the wafer 2 is measured, and the warp shape of the wafer 2 is obtained based on the mark focus position. Since the respective in-focus positions at the respective portions of the surface 2A to be inspected 2 of the wafer 2 are calculated from this warped shape, it is not necessary to perform focus adjustment (focusing) for each portion of the inspected surface 2A of the wafer 2. That is, since it is possible to obtain the in-focus position in each part of the wafer 2 without taking the trouble of focusing on each part of the wafer 2, it is possible to quickly perform focus correction corresponding to the warp of the wafer 2.
Therefore, when the inspection image of each part of the wafer 2 with a hole (not shown) is taken, focus correction can be easily performed while coping with the warpage of the wafer 2, so that the time required for the appearance inspection of the wafer 2 can be reduced. Can be greatly shortened.

(2) Further, by using a total of five alignment patterns 21 in each of the chips 200, 20X1, 20X2, 20Y1, and 20Y2 formed from the wafer 2, approximation of the mark in-focus positions measured for these alignment patterns 21 By deriving the formula, the focus correction can be performed more appropriately.

(3) Furthermore, the alignment patterns 21 in each of the chips 200, 20X1, 20X2, 20Y1, and 20Y2 are arranged at different positions in the in-plane X direction and the Y direction of the surface 2A to be inspected of the wafer 2, respectively. Since both the X-direction warpage and the Y-direction warpage on the inspection surface 2A are grasped, the focus correction can be performed more appropriately.

(4) Since the semiconductor pattern formed on the chip 20 cut out from the wafer 2 is also used as the alignment pattern 21, the alignment mark or pattern cannot be formed on the outer peripheral portion of the inspection surface 2A of the wafer 2. However, focus correction via alignment can be realized.

Although the present invention has been specifically described in the above embodiments, the present invention can be variously modified and improved without departing from the gist of the present invention.
For example, in the above-described embodiment, the alignment is performed in two stages of the coarse alignment and the fine alignment. However, the alignment is not limited to this, and it may be considered to perform the alignment using only the chip alignment pattern 21 used for the fine alignment. .
In the above-described embodiment, the five alignment patterns 21 are used. However, the present invention is not limited to this. For example, the wafer 2 can also be formed by providing three alignment marks in a scattered manner along the outer periphery of the surface 2A to be inspected. The warp shape in the X direction and Y direction in the surface 2A to be inspected can be calculated.

  Furthermore, in the said embodiment, after aligning by the five alignment patterns 21 in the alignment process P1, the focus position measurement about each alignment pattern 21 was performed in the mark focus position measurement process P2, but these alignment processes It is also possible to combine P1 and the mark focus position measurement process P2 into one process. That is, since each alignment pattern 21 is monitored by the camera 4 at the time of alignment, it is conceivable to measure the in-focus position of the camera 4 with respect to the alignment pattern 21 at the same timing.

The best configuration, method and the like for carrying out the present invention have been disclosed in the above description, but the present invention is not limited to this. That is, the invention has been illustrated and described primarily with respect to particular embodiments, but may be configured for the above-described embodiments without departing from the scope and spirit of the invention. Various modifications can be made by those skilled in the art in terms of materials, quantity, and other detailed configurations.
Therefore, the description limited to the shape, material, etc. disclosed above is an example for easy understanding of the present invention, and does not limit the present invention. The description by the name of the member which remove | excluded the limitation of one part or all of such restrictions is included in this invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. The plane schematic diagram of the semiconductor wafer in the said embodiment. The enlarged plan view of the chip | tip in which the alignment pattern was formed among each chip | tip formed from the semiconductor wafer in the said embodiment. The block diagram which shows the internal structure of the image processing apparatus in the said embodiment. The flowchart which shows the external appearance test process in the said embodiment. The figure which shows the focusing position about each alignment pattern arrange | positioned along the X direction of the wafer in the said embodiment with an approximated curve. The figure which shows the focusing position about each alignment pattern arrange | positioned along the Y direction of the wafer in the said embodiment with an approximated curve. Reference drawing of the present invention (showing a holeless wafer). Reference drawing of the present invention (showing a perforated wafer).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Appearance inspection apparatus, 2 ... Wafer, 2A ... Test surface, 4 ... Camera (imaging means), 5 ... Image processing apparatus, 20 ... Chip, 21 ... Alignment pattern (alignment mark) 52... Fine alignment means (alignment means) 53. Mark focus position measurement means 54... Each part focus position calculation means 200, 20X1, 20X2, 20Y1, 20Y2 ... chip, 200F, 20X1F, 20X2F, 20Y1F, 20Y2F ... mark in-focus position, B ... reference position, P12 ... fine alignment process (alignment process), P21 to P25 ... first mark In-focus position measurement step to fifth mark in-focus position measurement step, P31... Warp shape calculation step, P32... Each part in-focus position calculation step, P4. Degree.

Claims (5)

A wafer appearance inspection method for performing image processing based on each inspection image when each part of the inspection surface of the wafer is imaged by an imaging means,
An alignment step of positioning the wafer at a reference position using an alignment mark formed on the inspection surface of the wafer;
A mark in-focus position measuring step for measuring a mark in-focus position of the imaging means for the alignment mark;
Each part in-focus position calculating step for obtaining the warp shape of the wafer based on the mark in-focus position, and calculating each in-focus position of the imaging means for each part of the surface to be inspected based on the warp shape;
A wafer appearance inspection method, comprising: an inspection image capturing step for capturing each inspection image at each unit in-focus position for each unit by the imaging unit. The wafer visual inspection method according to claim 1,
A plurality of the alignment marks are provided,
In the respective in-focus position calculation step, an approximate expression is obtained for the mark in-focus position of each alignment mark, and the warp shape is represented by the approximate expression. A wafer appearance inspection apparatus comprising: imaging means for capturing each inspection image by imaging each part of the surface to be inspected of the wafer; and an image processing apparatus for processing each inspection image,
Alignment means for positioning the wafer at a reference position using an alignment mark formed on the surface to be inspected of the wafer;
An alignment mark in-focus position measuring means for measuring a mark in-focus position of the imaging means for the alignment mark;
Each part in-focus position calculating means for obtaining a warp shape of the wafer based on the mark in-focus position, and calculating each in-focus position of the imaging means for each part of the surface to be inspected based on the warp shape; Prepared,
The wafer imaging inspection apparatus characterized in that the imaging means images each inspection image at each unit in-focus position for each unit. In the wafer visual inspection apparatus according to claim 3,
Three or more alignment marks are provided at different positions in the X direction and the Y direction within the surface to be inspected. The wafer visual inspection apparatus according to claim 3 or 4,
The alignment mark is formed as a semiconductor pattern formed on any one of a plurality of chips from which the wafer is singulated.

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