JP2007294082A5 - - Google Patents
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- JP2007294082A5 JP2007294082A5 JP2007090867A JP2007090867A JP2007294082A5 JP 2007294082 A5 JP2007294082 A5 JP 2007294082A5 JP 2007090867 A JP2007090867 A JP 2007090867A JP 2007090867 A JP2007090867 A JP 2007090867A JP 2007294082 A5 JP2007294082 A5 JP 2007294082A5
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- nonvolatile memory
- nand
- nand type
- cell
- potential
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- 230000015654 memory Effects 0.000 claims 42
- 238000000034 method Methods 0.000 claims 12
- 239000004065 semiconductor Substances 0.000 claims 4
- 229910052732 germanium Inorganic materials 0.000 claims 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
Claims (8)
複数の不揮発性メモリが直列に接続されたＮＡＮＤ型セルと、
選択トランジスタと、を有し、
前記不揮発性メモリは、第１の絶縁膜を介した半導体膜上の電荷蓄積層と、第２の絶縁膜を介した前記電荷蓄積層上の制御ゲートと、を有し、
前記ＮＡＮＤ型セルの一方の端子は、前記選択トランジスタを介して、前記ビット線に接続され、
前記ＮＡＮＤ型セルの他方の端子は、前記ソース線に接続されたＮＡＮＤ型不揮発性メモリのデータ消去方法であって、
前記ＮＡＮＤ型セルにおけるいずれか一の前記不揮発性メモリにおける前記電荷蓄積層に格納された電荷の放出は、前記ビット線、前記ソース線に第１の電位を印加し、当該不揮発性メモリの制御ゲートに第２の電位を印加し、前記ＮＡＮＤ型セルの他の前記不揮発性メモリの前記制御ゲートには第３の電位を印加することにより行われることを特徴とするＮＡＮＤ型不揮発性メモリのデータ消去方法。 A bit line, a source line ,
A NAND type cell nonvolatile memory several are connected in series,
A selection transistor, and
Wherein the nonvolatile memory has a charge storage layer over the semiconductor film through the first insulating film, a control gate on the charge storage layer through the second insulating film, and
One terminal of the NAND cell is connected to the bit line through the selection transistor,
The other terminal of the NAND cell is a data erasing method of a NAND nonvolatile memory connected to the source line,
The discharge of the charge stored in the charge storage layer in any one of the nonvolatile memories in the NAND cell is performed by applying a first potential to the bit line and the source line, and controlling the control gate of the nonvolatile memory. the second potential is applied, the data erasing of the NAND type nonvolatile memory in addition to the control gate of the nonvolatile memory of the NAND type cell is characterized by being performed by applying a third potential to Method.
複数の不揮発性メモリが直列に接続されたＮＡＮＤ型セルと、
選択トランジスタと、を有し、
前記不揮発性メモリは、第１の絶縁膜を介した半導体膜上の電荷蓄積層と、第２の絶縁膜を介した前記電荷蓄積層上の制御ゲートと、を有し、
前記ＮＡＮＤ型セルの一方の端子は、前記選択トランジスタを介して、前記ビット線に接続され、
前記ＮＡＮＤ型セルの他方の端子は、前記ソース線に接続されたＮＡＮＤ型不揮発性メモリのデータ消去方法であって、
前記ＮＡＮＤ型セルにおけるいずれか一の前記不揮発性メモリにおける前記電荷蓄積層に格納された電荷の放出は、当該不揮発性メモリにおけるソース端子、ドレイン端子に第１の電位を印加し、前記制御ゲートに第２の電位を印加し、前記ＮＡＮＤ型セルの他の前記不揮発性メモリの前記制御ゲートには第３の電位を印加することにより行われることを特徴とするＮＡＮＤ型不揮発性メモリのデータ消去方法。 A bit line, a source line,
A NAND type cell nonvolatile memory several are connected in series,
A selection transistor, and
Wherein the nonvolatile memory has a charge storage layer over the semiconductor film through the first insulating film, a control gate on the charge storage layer through the second insulating film, and
One terminal of the NAND cell is connected to the bit line through the selection transistor,
The other terminal of the NAND cell is a data erasing method of a NAND nonvolatile memory connected to the source line,
Release of charges stored in the charge storage layer in any one of the nonvolatile memory in the NAND type cell, the source terminal of the non-volatile memory, the first potential is applied to the drain terminal, to said control gate A method of erasing data in a NAND type nonvolatile memory , wherein a second potential is applied and a third potential is applied to the control gate of the other nonvolatile memory in the NAND cell. .
複数の不揮発性メモリが直列に接続された第１のＮＡＮＤ型セル及び第２のＮＡＮＤ型セルと、
第１の選択トランジスタと、第２の選択トランジスタと、を有し、
前記不揮発性メモリは、第１の絶縁膜を介した半導体膜上の電荷蓄積層と、第２の絶縁膜を介した前記電荷蓄積層上の制御ゲートと、を有し、
前記第１のＮＡＮＤ型セルの一方の端子は、前記第１の選択トランジスタを介して、前記ビット線に接続され、
前記第１のＮＡＮＤ型セルの他方の端子は、前記ソース線に接続され、
前記第２のＮＡＮＤ型セルの一方の端子は、前記第２の選択トランジスタを介して、前記ビット線に接続され、
前記第２のＮＡＮＤ型セルの他方の端子は、前記ソース線に接続されたＮＡＮＤ型不揮発性メモリのデータ消去方法であって、
前記第１のＮＡＮＤ型セルにおけるいずれか一の前記不揮発性メモリ及び前記第２のＮＡＮＤ型セルにおけるいずれか一の前記不揮発性メモリにおける前記電荷蓄積層に格納された電荷の放出は、前記ビット線、前記ソース線に第１の電位を印加し、且つ前記第１のＮＡＮＤ型セルの前記一の前記不揮発性メモリの前記制御ゲートと、前記第２のＮＡＮＤ型セルの前記一の前記不揮発性メモリの前記制御ゲートに第２の電位を印加し、前記第１のＮＡＮＤ型セルの他の前記不揮発性メモリ及び前記第２のＮＡＮＤ型セルの他の前記不揮発性メモリの前記制御ゲートには第３の電位を印加することにより行われることを特徴とするＮＡＮＤ型不揮発性メモリのデータ消去方法。 A bit line, a source line,
A first NAND type cell and a second NAND type cell nonvolatile memory several are connected in series,
A first selection transistor and a second selection transistor;
Wherein the nonvolatile memory has a charge storage layer over the semiconductor film through the first insulating film, a control gate on the charge storage layer through the second insulating film, and
One terminal of the first NAND type cell is connected to the bit line via the first selection transistor,
The other terminal of the first NAND type cell is connected to the source line,
One terminal of the second NAND cell is connected to the bit line via the second selection transistor,
The other terminal of the second NAND type cell is a data erasing method of a NAND type nonvolatile memory connected to the source line ,
Release of the charge stored in the charge storage layer in any one of the non-volatile memories in the first NAND type cell and any one of the non-volatile memories in the second NAND type cell is performed by the bit line. The first potential is applied to the source line , and the control gate of the one nonvolatile memory of the first NAND cell and the one nonvolatile memory of the second NAND cell are applied. A second potential is applied to the control gate of the second NAND type cell, and a third potential is applied to the control gate of the other nonvolatile memory of the first NAND type cell and the other nonvolatile memory of the second NAND type cell. A method for erasing data in a NAND nonvolatile memory, which is performed by applying a potential of
複数の不揮発性メモリが直列に接続された第１のＮＡＮＤ型セル及び第２のＮＡＮＤ型セルと、
第１の選択トランジスタと、第２の選択トランジスタと、を有し、
前記不揮発性メモリは、第１の絶縁膜を介した半導体膜上の電荷蓄積層と、第２の絶縁膜を介した前記電荷蓄積層上の制御ゲートと、を有し、
前記第１のＮＡＮＤ型セルの一方の端子は、前記第１の選択トランジスタを介して、前記ビット線に接続され、
前記第１のＮＡＮＤ型セルの他方の端子は、前記ソース線に接続され、
前記第２のＮＡＮＤ型セルの一方の端子は、前記第２の選択トランジスタを介して、前記ビット線に接続され、
前記第２のＮＡＮＤ型セルの他方の端子は、前記ソース線に接続されたＮＡＮＤ型不揮発性メモリのデータ消去方法であって、
前記第１のＮＡＮＤ型セルにおけるいずれか一の前記不揮発性メモリ及び前記第２のＮＡＮＤ型セルにおけるいずれか一の前記不揮発性メモリにおける前記電荷蓄積層に格納された電荷の放出は、前記第１のＮＡＮＤ型セルにおける前記一の前記不揮発性メモリ及び前記第２のＮＡＮＤ型セルにおける前記一の前記不揮発性メモリにおけるソース端子、ドレイン端子に第１の電位を印加し、且つ前記第１のＮＡＮＤ型セルの前記一の前記不揮発性メモリの前記制御ゲートと、前記第２のＮＡＮＤ型セルの前記一の前記不揮発性メモリの前記制御ゲートに第２の電位を印加し、前記第１のＮＡＮＤ型セルの他の前記不揮発性メモリ及び前記第２のＮＡＮＤ型セルの他の前記不揮発性メモリの前記制御ゲートには第３電位を印加することにより行われることを特徴とするＮＡＮＤ型不揮発性メモリのデータ消去方法。 A bit line, a source line,
A first NAND type cell and a second NAND type cell nonvolatile memory several are connected in series,
A first selection transistor and a second selection transistor;
Wherein the nonvolatile memory has a charge storage layer over the semiconductor film through the first insulating film, a control gate on the charge storage layer through the second insulating film, and
One terminal of the first NAND type cell is connected to the bit line via the first selection transistor,
The other terminal of the first NAND type cell is connected to the source line,
One terminal of the second NAND cell is connected to the bit line via the second selection transistor,
The other terminal of the second NAND type cell is a data erasing method of a NAND type nonvolatile memory connected to the source line ,
The first of any one of the stored in the charge storage layer in any one of the nonvolatile memory in the nonvolatile memory and said second NAND type cell charge in the NAND cell release, the first It said nonvolatile memory and a source terminal of said nonvolatile memory of said one of said second NAND type cell, the first potential is applied to the drain terminal, and said first NAND type of the one in the NAND type cell Applying a second potential to the control gate of the one non-volatile memory of the cell and the control gate of the one non-volatile memory of the second NAND cell, the first NAND cell said nonvolatile memory and said the other of said control gates of said non-volatile memory of the second NAND type cell lines by applying a third potential of the other Data erase method of a NAND type nonvolatile memory, characterized in that it is.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007090867A JP2007294082A (en) | 2006-03-31 | 2007-03-30 | Method for deleting data from nand type nonvolatile memory |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006101219 | 2006-03-31 | ||
| JP2007090867A JP2007294082A (en) | 2006-03-31 | 2007-03-30 | Method for deleting data from nand type nonvolatile memory |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012119909A Division JP2012212892A (en) | 2006-03-31 | 2012-05-25 | Method for erasing data of nand type nonvolatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007294082A JP2007294082A (en) | 2007-11-08 |
| JP2007294082A5 true JP2007294082A5 (en) | 2010-05-06 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007090867A Withdrawn JP2007294082A (en) | 2006-03-31 | 2007-03-30 | Method for deleting data from nand type nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2007294082A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009152498A (en) | 2007-12-21 | 2009-07-09 | Toshiba Corp | Nonvolatile semiconductor memory |
| JP5295606B2 (en) * | 2008-03-28 | 2013-09-18 | 株式会社東芝 | NAND type nonvolatile semiconductor memory device |
| JP5378255B2 (en) * | 2010-02-02 | 2013-12-25 | 株式会社東芝 | Nonvolatile semiconductor memory device and driving method of nonvolatile semiconductor memory device |
| JP5571156B2 (en) * | 2012-11-21 | 2014-08-13 | 株式会社東芝 | Manufacturing method of semiconductor device |
| JP5583238B2 (en) * | 2013-04-26 | 2014-09-03 | 株式会社東芝 | NAND-type nonvolatile semiconductor memory device and manufacturing method thereof |
| US10269822B2 (en) | 2015-12-29 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to fabricate uniform tunneling dielectric of embedded flash memory cell |
| CN107039452B (en) * | 2015-12-29 | 2020-02-21 | 台湾积体电路制造股份有限公司 | Method of fabricating uniform tunnel dielectric for embedded flash memory cells |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR910007434B1 (en) * | 1988-12-15 | 1991-09-26 | 삼성전자 주식회사 | Eeprom and the programming method |
| JP2523019B2 (en) * | 1989-06-30 | 1996-08-07 | 株式会社半導体エネルギー研究所 | Field effect type semiconductor device |
| JP3272007B2 (en) * | 1991-10-31 | 2002-04-08 | ローム株式会社 | Method for manufacturing charge trapping film |
| JP3230323B2 (en) * | 1993-03-22 | 2001-11-19 | 日本電気株式会社 | Control method of nonvolatile storage device |
| JP2838993B2 (en) * | 1995-11-29 | 1998-12-16 | 日本電気株式会社 | Nonvolatile semiconductor memory device |
| JPH11219950A (en) * | 1998-02-03 | 1999-08-10 | Hitachi Ltd | Manufacture of semiconductor integrated circuit and manufacturing device thereof |
| KR100297712B1 (en) * | 1998-07-23 | 2001-08-07 | 윤종용 | Nonvolatile memory for high integration & fabricating method the same |
| JP3942902B2 (en) * | 2001-01-26 | 2007-07-11 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4969001B2 (en) * | 2001-09-20 | 2012-07-04 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| JP2003152102A (en) * | 2001-11-15 | 2003-05-23 | Hitachi Ltd | Method of manufacturing semiconductor integrated circuit device |
| JP4329293B2 (en) * | 2002-01-10 | 2009-09-09 | ソニー株式会社 | Nonvolatile semiconductor memory device and charge injection method |
| JP4040534B2 (en) * | 2003-06-04 | 2008-01-30 | 株式会社東芝 | Semiconductor memory device |
| JP4481632B2 (en) * | 2003-12-19 | 2010-06-16 | 株式会社半導体エネルギー研究所 | Thin film integrated circuit |
| KR101157409B1 (en) * | 2004-02-10 | 2012-06-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Nonvolatile memory and IC card, ID card and ID tag incorporated with the same |
| JP2006041107A (en) * | 2004-07-26 | 2006-02-09 | Seiko Epson Corp | Semiconductor device and its fabrication process |
| JP4942959B2 (en) * | 2004-07-30 | 2012-05-30 | 株式会社半導体エネルギー研究所 | Laser irradiation apparatus and laser irradiation method |
-
2007
- 2007-03-30 JP JP2007090867A patent/JP2007294082A/en not_active Withdrawn
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