JP2007294013A5 - - Google Patents

Claims (9)

A plurality of entries, each having a plurality of content reference memory cells;
A plurality of match lines that are arranged corresponding to each of the entries, and in which content reference memory cells of the entry corresponding to each are coupled in parallel;
A search data bus coupled in parallel to each of the entries and transferring search data in common to each of the entries;
Coupled to each of said match lines, each of which compares a precharge circuit for precharging to a predetermined precharge voltage to the match line of the associated, a voltage of said corresponding match line the base reference voltage, indicating the comparison result A plurality of match amplifiers including an amplification circuit that generates a signal, and a capacitive element that supplies a charge to a corresponding match line when comparing the search data of the search data bus with the stored data of each entry Reference memory. The content reference memory according to claim 1, wherein the precharge voltage of the match line is a voltage equal to or lower than an intermediate value between a power supply voltage and a ground voltage. The precharge voltage and the reference voltage are supplied from the same power source,
Each of the match amplifiers further includes a reference capacitor element that is charged with the precharge voltage during a precharge operation of the precharge circuit, and the charge voltage of the reference capacitor element is transmitted to the amplifier circuit as the reference voltage. The content reference memory according to claim 1 or 2 . The match amplifier further includes:
Coupled between the capacitive element and a corresponding match line, and conducts when the search data is transferred to supply a charge of the capacitive element to the corresponding match line; and when the amplifier circuit is activated, A first transistor element to be
3. The content reference memory according to claim 1, further comprising: a second transistor element that charges the capacitor element to a power supply voltage level when the amplifier circuit is activated and the first transistor element is in a cut-off state. 4. A plurality of entries, each having a plurality of content reference memory cells;
A plurality of match lines that are arranged corresponding to each of the entries, and in which content reference memory cells of the entry corresponding to each are coupled in parallel;
A search data bus coupled in parallel to each entry and transferring search data in parallel to each entry, and coupled to each match line, each precharges a corresponding match line to a ground voltage level. In a comparison operation between the charge circuit and the search data of the search data bus and the stored data of each entry, the current having a limited current value is supplied to the corresponding match line and the upper limit value of the voltage level of the corresponding match line A content reference memory comprising a plurality of match amplifiers including a pull-up current supply / determination circuit that clamps at a predetermined value or less and generates a signal corresponding to the voltage level of the corresponding match line at an internal node. The limited current value is smaller than the current value that flows when the one-bit content reference memory cell of one entry is turned on, and when all of the one-entry content reference memory cells are turned off. 6. The content reference memory according to claim 5 , wherein the current reference memory has a current value larger than a current flowing from the corresponding match line through the one entry. The content reference memory according to claim 5 , wherein each of the match amplifiers further includes a capacitive element that supplies a charge to a corresponding match line during the comparison operation. The pull-up current supply / determination circuit includes:
A current source transistor element which supplies a current in a complementary manner with the first transistor element constituting the precharge circuit;
6. The content reference memory according to claim 5 , further comprising: a clamp transistor element that receives a bias voltage at a gate and supplies a current from the current source transistor element to a corresponding match line. The pull-up current supply / determination circuit further includes:
A second transistor element connected between the current source transistor element and the clamp transistor element;
And a gate circuit for selectively turned the second transistor element according to the voltage and the pull-up instruction of the connection node between said second transistor element and the clamp transistor device, according to claim 8 Content reference memory.