JP5104297B2 - Associative memory - Google Patents

Description

  The present invention retrieves an associative memory (CAM: Content Addressable Memory), that is, an address for storing the same data as search data given from the outside, and externally sends an address signal indicating the address for storing the same data as the search data. The present invention relates to a memory having an output function (so-called search function).

  FIG. 17 is a diagram for explaining the function of the associative memory in comparison with a RAM (Random Access Memory). In FIG. 17, 1 is a RAM and 2 is an associative memory. The RAM 1 is capable of writing and reading. As shown in (A), when a write command, an address signal, and data are given, data is written to the address indicated by the address signal, and (B ), When a read command and an address signal are given, data is read from the address indicated by the address signal and output.

  The associative memory 2 is capable of writing, reading, and searching. As shown in (C), when a write command, an address signal, and data are given, data writing to an address indicated by the address signal is performed. When a read command and an address signal are given as shown in (D), data is read out from the address indicated by the address signal and output, and as shown in (E), when a search command and data are given The address storing the same data as the given data is searched, and an address signal indicating the searched address is output.

  FIG. 18 is a circuit diagram showing an example of a memory cell provided in the associative memory. In FIG. 18, WL is a word line for selecting a memory cell at the time of writing / reading, BL and XBL are transmitted to the memory cell of complementary write data output from the write amplifier at the time of writing, and memory at the time of reading. Bit lines SB and XSB for transmitting the complementary read data read from the cell to the sense amplifier, the data obtained by complementing the search data given from the outside is transmitted from the search driver to the memory cell. A search bus ML is a match line for detecting a match or mismatch between the search data and the stored data of the memory cell, and 3 is a memory cell composed of SRAM (Static Random Access Memory) cells.

  In the memory cell 3, reference numeral 4 denotes a flip-flop forming a storage medium, reference numerals 5 and 6 denote inverters, and reference numerals S0 and S1 denote storage nodes. 7 and 8 are NMOS transistors whose ON / OFF is controlled by the potential of the word line WL, 9 is an NMOS transistor whose ON / OFF is controlled by the potential of the storage node S0, and 10 is ON / OFF by the potential of the storage node S1. An NMOS transistor to be controlled, 11 is an NMOS transistor whose ON / OFF is controlled by the potential of the search bus XSB, and 12 is an NMOS transistor whose ON / OFF is controlled by the potential of the search bus SB.

  In this example, data writing to the memory cell 3 and data reading from the memory cell 3 are performed using the word line WL, the bit lines BL and XBL, and the NMOS transistors 7 and 8. Table 1 shows the relationship between the data stored in the memory cell 3, the logical values of the storage nodes S0 and S1, and the logical values of the bit lines BL and XBL when data is written to and read from the memory cell 3. Yes.

  Here, when data “0” is written to the memory cell 3, the logical value of the word line WL = “1”, the state of the NMOS transistors 7 and 8 = ON, the logical value of the bit line BL = “0”, the bit By setting the logical value of the line XBL = “1”, the logical value of the storage node S0 = “0”, the logical value of the storage node S1 = “1”, and then the logical value of the word line WL = “0”, The state of the NMOS transistors 7 and 8 is set to OFF.

  On the other hand, when data “1” is written in the memory cell 3, the logical value of the word line WL = “1”, the state of the NMOS transistors 7 and 8 = ON, and the logical value of the bit line BL = “1”. By setting the logical value of the bit line XBL = “0”, the logical value of the storage node S0 = “1”, the logical value of the storage node S1 = “0”, and then the logical value of the word line WL = “0” "The state of the NMOS transistors 7 and 8 is set to OFF."

  When the storage data of the memory cell 3 is “0”, that is, when the logical value of the storage node S0 = “0” and the logical value of the storage node S1 = “1”, the logical value of the word line WL When the value = “1”, the state of the NMOS transistors 7 and 8 = ON, and data is read from the memory cell 3, the logical value of the bit line BL = “0” and the logical value of the bit line XBL = “1”.

  On the other hand, when the storage data of the memory cell 3 is “1”, that is, when the logical value of the storage node S0 = “1” and the logical value of the storage node S1 = “0”, the word line When the logical value of WL is “1”, the state of the NMOS transistors 7 and 8 is ON, and data is read from the memory cell 3, the logical value of the bit line BL is “1” and the logical value of the bit line XBL is “0”. It becomes.

  The search for the memory cell 3 is performed using the search buses SB and XSB, the NMOS transistors 9 to 12 and the match line ML. Table 2 shows the relationship between the storage data of the memory cell 3, the logical values of the storage nodes S0 and S1, the search data, the logical values of the search buses SB and XSB, and the logical value of the match line ML at the time of retrieval. FIG. 22 is a circuit diagram for explaining a search operation for the memory cell 3.

  In this example, at the time of non-search, the logical values of the search buses SB and XSB = “0”, and the states of the NMOS transistors 11 and 12 are OFF. On the other hand, at the time of search, the match line ML is precharged to the power supply voltage VDD, and its logical value is set to “1”. When the search data = "0", the logical value of the search bus SB = "0" and the logical value of the search bus XSB = "1". When the search data = "1", the search bus The logical value of SB = “1” and the logical value of search bus XSB = “0”.

  Here, as shown in FIG. 19, when the storage data of the memory cell 3 is “0” (that is, the logical value of the storage node S0 = “0” and the logical value of the storage node S1 = “1”). In this case, when “0” is input as the search data (that is, when the logical value of the search bus SB = “0” and the logical value of the search bus XSB = “1”), the NMOS transistor 9 Is OFF, the NMOS transistor 10 is ON, the NMOS transistor 11 is ON, and the NMOS transistor 12 is OFF, so that the logic value = “1” of the match line ML is maintained.

  On the other hand, as shown in FIG. 20, when the storage data of the memory cell 3 = “0” (that is, the logical value of the storage node S0 = “0” and the logical value of the storage node S1 = “1”). When “1” is input as search data (ie, when the logical value of the search bus SB = “1” and the logical value of the search bus XSB = “0”), the NMOS Since the transistor 9 is OFF, the NMOS transistor 10 is ON, the NMOS transistor 11 is OFF, and the NMOS transistor 12 is ON, the match line ML is grounded via the NMOS transistors 10 and 12, and the logical value of the match line ML is “ Transition to 0 ".

  Further, as shown in FIG. 21, when the storage data of the memory cell 3 is “1” (that is, the logical value of the storage node S0 is “1” and the logical value of the storage node S1 is “0”). ) Is input as search data (that is, when the logical value of the search bus SB = “1” and the logical value of the search bus XSB = “0”), the NMOS transistor 9 Since ON, the NMOS transistor 10 is OFF, the NMOS transistor 11 is OFF, and the NMOS transistor 12 is ON, the logical value = “1” of the match line ML is maintained.

  As shown in FIG. 22, when the storage data of the memory cell 3 is “1” (that is, when the logical value of the storage node S0 is “1” and the logical value of the storage node S1 is “0”). ) Is input as search data (that is, when the logic value of the search bus SB = “0” and the logic value of the search bus XSB = “1”), the NMOS transistor 9 Since ON, NMOS transistor 10 is OFF, NMOS transistor 11 is ON, and NMOS transistor 12 is OFF, match line ML is grounded via NMOS transistors 9 and 11, and the logical value of match line ML is “0”. Transition.

  FIG. 23 is a waveform diagram showing potential changes of the search buses SB and XSB and the match line ML at the time of search for the memory cell 3, wherein (A) shows potential changes of the search buses SB and XSB, and (B) shows the match line ML. It shows the potential change. As described above, the match line ML is precharged to the power supply voltage VDD (logic 1). However, when the search data and the storage data of the memory cell 3 do not match, the match line ML includes the NMOS transistors 9 and 11. Alternatively, it is grounded via the NMOS transistors 10 and 12, the potential of the match line ML drops to 0V (logic 0), and when the search data matches the data stored in the memory cell 3, the match line ML is grounded. First, the power supply voltage VDD (logic 1) is maintained.

  FIG. 24 is a circuit diagram showing the relationship between memory cells and match lines in an actual content addressable memory. In FIG. 24, 3 (0), 3 (1), 3 (2), and 3 (n-1) are memory cells, and the memory cells 3 (3) to 3 (n-2) are not shown. Yes. SB (0), XSB (0), SB (1), XSB (1), SB (2), XSB (2), SB (n-1), and XSB (n-1) are search buses, and search The buses SB (3), XSB (3) to SB (n-2), and XSB (n-2) are not shown.

  Reference numeral 15 denotes a match line sense amplifier (MLSA) that detects a potential change of the match line ML and outputs a search result signal MSZ during the search. The match line sense amplifier 15 sets the logical value of the search result signal MSZ = “1” when the logical value of the match line ML = “1”, and searches when the logical value of the match line ML = “0”. The logical value of the result signal MSZ = “0”.

  As shown in FIG. 24, in the actual associative memory, the relationship between the memory cell and the match line is not 1: 1, and the match line ML has the same number of memory cells 3 (0 as the number of search data bits). ) To 3 (n-1) are connected. The match line ML maintains “1” when the logical value of each bit of the search data composed of n bits matches the logical value of the data stored in the corresponding memory cell. Transitions to “0” when the logical value of this bit does not match the logical value of the data stored in the corresponding memory cell.

  FIG. 25 is a block diagram showing a part of an example of a conventional content addressable memory. In FIG. 25, 16 is a memory cell array in which 512 memory cell columns in which n memory cells having the configuration shown in FIG. 18 are arranged per row (one word line) are arranged, and 17 is a word decoder (word decoder for driving word lines). WDEC) is a word decoder unit, 18 is a write amplifier (W / A) group that writes to a memory cell, and 19 is a sense amplifier (S) that amplifies the data read to the bit line. / A) is a sense amplifier unit.

  20 is a search driver section that is a group of search drivers (S / D) that drives the search bus, 21 is a match line sense amplifier section that is a group of match line sense amplifiers (MLSA) that performs level detection of match lines, An encoder (ENC) 22 encodes the search result signal MSZ output from the match line / sense amplifier unit 21 and outputs an address signal indicating an address where the same data as the search data is stored.

  Reference numeral 23 is a command decoder (COMDEC) that decodes a search command signal given from the outside, and 24 is a search command decode signal output from the command decoder 23 and generates a search driver activation signal that is given to the search driver of the search driver unit 20. A search driver activation signal generation circuit (SBGEN).

  FIG. 26 is a circuit diagram showing a part of the conventional content addressable memory shown in FIG. 25 in more detail. In the memory cell array 16, 3 (0, 0) is the first bit memory cell in the first row, 3 (0, 1) is the second bit memory cell in the first row, and 3 (0, n-1) is The nth bit memory cell in the first row, and the memory cells 3 (0, 2) -3 (0, n-2) in the third row to the (n-1) th bit in the first row are not shown. Yes. 3 (1, 0) is the first bit memory cell in the second row, 3 (1, 1) is the second bit memory cell in the second row, 3 (1, n-1) is n in the second row The memory cells 3 (1, 2) to 3 (1, n-2) of the third bit to the (n-1) th bit in the second row are not shown.

  3 (511, 0) is the first bit memory cell in the 512th row, 3 (511, 1) is the second bit memory cell in the 512th row, and 3 (511, n-1) is n in the 512th row. The memory cells 3 (511, 2) to 3 (511, n-2) of the third bit to the (n-1) th bit in the 512th row are not shown. The memory cells 3 (2, 0) to 3 (2, n−1),..., 3 (510, 0) to 3 (510, n−1) in the third to 511th rows are not shown. ing. FIG. 27 shows in more detail the portion of the memory cell array 16 shown in FIG. In this example, the address of the memory cell column in the k-th row (where k = 1, 2,..., 512, and so on) is the address k−1.

  In FIG. 26, WL0 is the word line of the first row, WL1 is the word line of the second row, WL511 is the word line of the 512th row, and the word lines WL2 to WL510 of the third to 511th rows are illustrated. Is omitted. ML0 is the first match line, ML1 is the second match line, ML511 is the 512th match line, and the third to 511th match lines ML2 to ML510 are not shown.

  In the word decoder unit 17, 25 (0) is a word decoder provided corresponding to the first word line WL0, 25 (1) is a word decoder provided corresponding to the second word line WL1, 25 (511) is a word decoder provided corresponding to the word line WL511 of the 512th row, and a word decoder 25 (2) provided corresponding to the word lines WL2 to WL510 of the third row to 511th row. -25 (510) are not shown.

  In the write amplifier unit 18, 26 (0) is a write amplifier provided corresponding to the bit line BL (0) of the first bit and XBL (0), and 26 (1) is a bit line BL (1 of the second bit). ), A write amplifier provided corresponding to XBL (1), and 26 (n-1) is a write provided corresponding to the bit line BL (n-1), XBL (n-1) of the nth bit. A write amplifier 26 (corresponding to the bit lines BL (2), XBL (2) to BL (n-2), XBL (n-2) of the third bit to the (n-1) th bit. 2) to 26 (n-2) are not shown.

  In the sense amplifier unit 19, 27 (0) is a sense amplifier provided corresponding to the first bit line BL (0) and XBL (0), and 27 (1) is a second bit line BL (1 ), A sense amplifier provided corresponding to XBL (1), 27 (n-1) is a sense provided corresponding to the bit line BL (n-1), XBL (n-1) of the nth bit. Sense amplifier 27 (corresponding to the bit lines BL (2), XBL (2) to BL (n-2), XBL (n-2) of the third bit to the (n-1) th bit. 2) to 27 (n-2) are not shown.

  In the search driver unit 20, 28 (0) is a search driver provided corresponding to the first bit search bus SB (0) and XSB (0), and 28 (1) is a second bit search bus SB (1). ), A search driver provided corresponding to XSB (1), and 28 (n-1) is a search provided corresponding to the nth bit search buses SB (n-1) and XSB (n-1). A search driver 28 (corresponding to search buses SB (2), XSB (2) to SB (n-2), and XSB (n-2) of the third to n-1th bits. 2) to 28 (n-2) are not shown.

  In the match line / sense amplifier unit 21, 15 (0) corresponds to the match line / sense amplifier provided corresponding to the first-line match line ML0, and 15 (1) corresponds to the second-line match line ML1. The provided match line sense amplifier 15 (511) is a match line sense amplifier provided corresponding to the match line ML511 in the 512th row, and is matched to the match lines ML2 to ML510 in the third to 511th rows. Match line / sense amplifiers 15 (2) to 15 (510) provided correspondingly are not shown.

  28 is a circuit diagram for explaining an example of the search operation of the conventional associative memory shown in FIG. 25, and FIGS. 29 and 30 are timing diagrams showing an example of the search operation of the conventional associative memory shown in FIG. FIG. 30 shows the case where the search data DIN matches the storage data at the address 1, and FIG. 30 shows the case where the search data DIN matches the storage data at the address 0.

  In FIG. 28, XSER is a search command signal supplied to the command decoder 23 from the outside, SERZ is a search command decode signal output by the command decoder 23, SBEZ is a search driver activation signal output by the search driver activation signal generation circuit 24, DIN is n-bit search data provided from the outside, D (0) is the first bit data of the search data DIN, D (n−1) is the nth bit data of the search data DIN, and the search data DIN The second bit to n-1 bit data D (1) to D (n-2) are not shown. MS0Z is a search result signal output from the match line sense amplifier 15 (0) in the first row, MS1Z is a search result signal output from the match line sense amplifier 15 (1) in the second row, and EA is the encoder 22. Is a 9-bit address signal output.

  29 and 30, (A) is a clock signal CLK for determining an operation cycle, (B) is a search command signal XSER, (C) is a search command decode signal SERZ, and (D) is a search driver activation signal SBEZ. , (E) are logical values of search buses SB (p), XSB (p) (where p = 0, 1,..., N−1, and so on), (F) is a match line. The logical value of ML0, (G) indicates the search result signal MS0Z, (H) indicates the logical value of the match line ML1, and (I) indicates the search result signal MS1Z.

  That is, in the conventional associative memory shown in FIG. 25, the search command signal XSER = “1”, the search command decode signal SERZ = “0”, and the search driver activation signal SBEZ = “0” before search (during standby). “, Logical values of search buses SB (p) and XSB (p) =“ 0 ”, logical values of match lines ML0 to ML511 =“ 1 ”, and search result signals MS0Z to MS511Z =“ 1 ”.

  When searching, as shown in FIGS. 29 and 30, the search command signal XSER = “0” is set, the search is instructed, and the search drivers 28 (0) to 28 (n−1). Is provided with search data D (0) to D (n-1). As a result, the command decoder 23 sets the search command decode signal SERZ = “1”, and in response to this, the search driver activation signal generation circuit 24 sets the search driver activation signal SBEZ = “1” and the search driver 28 (P) corresponds to the value of the search data D (p), and one of the search buses SB (p) and XSB (p) is set to “1” and the other is set to “0”.

  Here, the search data D (0) to D (n−1) do not match the storage data at the address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)). When the data matches the storage data at address 1 (that is, the storage data of memory cells 3 (1, 0) to 3 (1, n-1)), as shown in FIG. 29, the logical value of match line ML0 = "0" ", And the logical value of the match line ML1 =" 1 "is maintained. As a result, the match line sense amplifier 15 (0) sets the search result signal MS0Z = “0”, and the match line sense amplifier 15 (1) maintains the search result signal MS1Z = “1”. Therefore, in this case, the encoder 22 outputs [000000001] as the address signal EA indicating the first address.

  On the other hand, the search data D (0) to D (n−1) is equal to the storage data at address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)). If it does not match the storage data at address 1 (that is, the storage data of memory cells 3 (1, 0) to 3 (1, n-1)), as shown in FIG. 30, match line ML0 Of the match line ML1 is maintained at “0”. As a result, the match line sense amplifier 15 (0) maintains the search result signal MS0Z = "1", and the match line sense amplifier 15 (1) sets the logical value of the search result signal MS1Z = "0". . Therefore, in this case, the encoder 22 outputs [000000000000] as the address signal EA indicating the address 0.

The associative memory has a function of predetermining a priority order for outputting an address signal indicating which address when the search data matches the stored data at a plurality of addresses, and outputting an address signal in accordance with this. A priority match function is provided. For example, in the case of the conventional associative memory shown in FIG. 25, when the search data DIN matches the stored data at a plurality of addresses, the priority order is set such that an address signal indicating the minimum address is output. As shown in FIG. 31, when the search data DIN matches the stored data at address 0 and the stored data at address 2, the encoder 22 detects the address 0 and outputs an address signal indicating the address 0. become.
JP 2000-215678 A JP-A-7-287718 JP-A-3-212896

  In the conventional associative memory shown in FIG. 25, the search operation for the search data DIN is performed for all 512 addresses (addresses 0 to 511), but the address for storing the same data as the search data DIN is The logic value of most of the 512 match lines ML0 to ML511 transitions to “0”, so when returning to the standby state after the search, the 512 match lines ML0 to ML511 Most require charging. Here, if it is possible to reduce the number of match lines that need to be charged when returning to the standby state after searching, the current consumption can be reduced, so the development of an associative memory capable of this is required. Yes.

  In view of the above, the present invention provides an associative memory that can reduce the number of match lines that need to be charged when returning to a standby state after a search, thereby reducing current consumption. Objective.

  The associative memory disclosed in the present application includes a first memory cell unit, a second memory cell unit, and a first match that is provided corresponding to the first memory cell unit and is precharged before a search. And a second match line provided corresponding to the second memory cell portion and precharged before the search.

  The first memory cell unit discharges the first match line when search data does not match its own stored data during search, and when the search data matches its own stored data, The first match line is configured not to be discharged.

  The second memory cell unit may be configured such that when the search data does not match the storage data of the first memory cell unit when searching, the second memory cell unit When the match data is discharged and the search data matches its own stored data, the second match line is not discharged and the search data matches the storage data of the first memory cell unit Is configured so as not to discharge the second match line regardless of whether the search data matches its own stored data.

  According to the disclosed associative memory, when the search data matches the storage data of the first memory cell unit, the second memory cell unit matches or does not match the search data with its own storage data. Regardless, since the second match line is configured not to be discharged, when the search data matches the storage data of the first memory cell unit, the search returns to the standby state after the search. There is no need to charge the second match line. Therefore, it is possible to reduce the number of match lines that need to be charged when returning to the standby state after the search, thereby reducing current consumption.

(First embodiment)
FIG. 1 is a circuit diagram showing a part of the first embodiment of the present invention. In the first embodiment of the present invention, a memory cell array 31 having a configuration different from that of the memory cell array 16 included in the conventional associative memory shown in FIG. 25 is provided, and the others are configured similarly to the conventional associative memory shown in FIG. It is.

  FIG. 2 is a circuit diagram showing a configuration of the memory cell array 31. In FIG. 2, the memory cells 3 (0, 0) and 3 (0, n−1) at the first bit and the nth bit at the address 0, and the memory cells 3 (1 at the first and nth bits at the first address). , 0), 3 (1, n-1), and the first and nth bit memory cells 3 (510, 0), 3 (510, n-1), and the first bit at address 511. And n-th bit memory cells 3 (511, 0) and 3 (511, n−1) are shown, and the others are not shown.

  Here, for example, among the NMOS transistors 9 (1, p) to 12 (1, p) in the memory cell 3 (1, p) at the address 1, the gate is connected to the search bus SB (p) or XSB (p). The sources of the connected NMOS transistors 11 (1, p) and 12 (1, p) are connected to the match line ML0 at address 0 without being grounded.

  For example, among the NMOS transistors 9 (511, p) to 12 (511, p) in the memory cell 3 (511, p) at the address 511, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (511, p) and 12 (511, p) are connected to the match line ML510 at address 510 without being grounded.

  That is, the memory cell array 31 has an odd number, that is, an NMOS in the memory cell 3 (2m + 1, p) at the address 2m + 1 (where m = 0, 1, 2,..., 255, and so on). Among the transistors 9 (2m + 1, p) to 12 (2m + 1, p), NMOS transistors 11 (2m + 1, p), 12 (2m + 1, p) whose gates are connected to the search bus SB (p) or XSB (p) The source is connected to the match line ML2m at address 2m without being grounded, and the other is configured in the same manner as the memory cell array 16 shown in FIG.

  3 to 5 are timing charts for explaining an example of a search operation according to the first embodiment of the present invention. FIG. 3 shows that the search data DIN does not match the stored data at address 0 and matches the stored data at address 1. 4 shows a case where the search data DIN does not match the stored data at addresses 0 and 1, and FIG. 5 shows a case where the search data DIN matches the stored data DIN at address 0.

  3 to 5, (A) is a clock signal CLK for determining an operation cycle, (B) is a search command signal XSER, (C) is a search command decode signal SERZ, (D) is a search driver activation signal SBEZ, ( E) is the level of the search buses SB (p) and XSB (p), (F) is the level of the match line ML0, (G) is the search result signal MS0Z, (H) is the level of the match line ML1, and (I) is A search result signal MS1Z is shown.

  That is, in the first embodiment of the present invention, before search (during standby), the search command signal XSER is at H level, the search command decode signal SERZ is at L level, the search driver activation signal SBEZ is at L level, and the search bus SB (p) and XSB (p) are set to L level, match lines ML0 to ML511 are set to H level, and search result signals MS0Z to MS511Z are set to H level.

  At the time of the search, as shown in FIGS. 3 to 5, the search command signal XSER is set to the L level, the search is instructed, and the search driver 28 (0) to 28 (n-1) is searched. DIN = D (0) to D (n-1) is given. As a result, the command decoder 23 sets the search command decode signal SERZ to H level, and in response to this, the search driver activation signal generation circuit 24 sets the search driver activation signal SBEZ to H level, and the search driver 28 (p ) Sets one of the search buses SB (p) and XSB (p) to the H level and the other to the L level corresponding to the value of the search data D (p).

  Here, for example, when the search data DIN does not match the storage data at address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)), FIG. 3 and FIG. As shown, the match line ML0 is at the L level. As a result, the NMOS transistors 9 (0, 9) to 12 (0, p) in the memory cell 3 (1, p) at the address 1 are activated, and the memory cell 3 (1, p) at the address 1 is targeted. A search is performed.

  For example, if the search data DIN matches the storage data at the address 1 (that is, the storage data of the memory cells 3 (1, 0) to 3 (1, n-1)), as shown in FIG. ML1 is maintained at the H level. On the other hand, when the search data DIN does not match the storage data at the address 1 (that is, the storage data of the memory cells 3 (1, 0) to 3 (1, n-1)), as shown in FIG. In addition, the match line ML1 at address 1 is at the L level.

  Further, when address 0 is searched for search data DIN, if search data DIN matches storage data at address 0 (that is, storage data in memory cells 3 (0, 0) to 3 (0, n−1)). As shown in FIG. 5, the match line ML0 at address 0 is maintained at the H level.

  As a result, the source levels of the NMOS transistors 11 (1, p) and 12 (1, p) in the memory cell 3 (1, p) at the address 1 become the precharge levels of the match lines ML0 to ML511, and the NMOS transistor 11 (1, p) and 12 (1, p) become inactive, and the search for the memory cell 3 (1, p) at address 1 is not executed. Therefore, in this case, the match line ML1 at the first address is maintained at the H level, and the match line ML1 at the first address does not need to be charged when returning to the standby state after the search.

  That is, according to the first embodiment of the present invention, when the search data DIN matches the stored data at the address 2m, the match line ML (2m + 1) at the address 2m + 1 maintains the H level. When returning to the state, it is not necessary to charge the match line ML (2m + 1) at the address 2m + 1. Therefore, it is possible to reduce the number of match lines that need to be charged when returning to the standby state after the search, thereby reducing current consumption.

(Second Embodiment)
6 and 7 are circuit diagrams showing a part of the second embodiment of the present invention, and show the configuration of the memory cell array 32 provided in the second embodiment of the present invention. That is, the second embodiment of the present invention is provided with a memory cell array 32 having a configuration different from that of the memory cell array 16 included in the conventional associative memory shown in FIG. It is a thing.

  In FIG. 6, the memory cells 3 (0, 0) and 3 (0, n−1) at the first bit and the nth bit at the address 0, and the memory cells 3 (1 at the first and nth bits at the first address). , 0), 3 (1, n-1), memory cell 3 (2, 0), 3 (2, n-1) at the first and nth bits at address 2, and the first bit at address 3. And n-th bit memory cells 3 (3, 0), 3 (3, n−1) are shown, and the others are not shown.

  In FIG. 7, the memory cells 3 (508, 0) and 3 (508, n−1) at the first bit and the nth bit at the address 508 and the memory cell 3 (509 at the first and nth bits at the address 509 are shown. , 0), 3 (509, n-1), the first bit at address 510 and the memory cell 3 (510, 0), 3 (510, n-1) at address 510, and the first bit at address 511 And n-th bit memory cells 3 (511, 0) and 3 (511, n−1) are shown, and the others are not shown.

  Here, for example, among the NMOS transistors 9 (1, p) to 12 (1, p) in the memory cell 3 (1, p) at the address 1, the gate is connected to the search bus SB (p) or XSB (p). The sources of the connected NMOS transistors 11 (1, p) and 12 (1, p) are connected to the match line ML0 at address 0 without being grounded.

  Among the NMOS transistors 9 (2, p) to 12 (2, p) in the memory cell 3 (2, p) at the address 2, the NMOS whose gate is connected to the search bus SB (p) or XSB (p) The sources of the transistors 11 (2, p) and 12 (2, p) are not grounded but are connected to the first match line ML1.

  Among the NMOS transistors 9 (3, p) to 12 (3, p) in the memory cell 3 (3, p) at address 3, the NMOS is connected to the search bus SB (p) or XSB (p). The sources of the transistors 11 (3, p) and 12 (3, p) are connected to the match line ML2 at the second address without being grounded.

  Of the NMOS transistors 9 (509, p) to 12 (509, p) in the memory cell 3 (509, p) at address 509, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (509, p) and 12 (509, p) are connected to the match line ML508 at address 508 without being grounded.

  Among the NMOS transistors 9 (510, p) to 12 (510, p) in the memory cell 3 (510, p) at address 510, the gate is connected to the search bus SB (p) or XSB (p). The sources of the transistors 11 (510, p) and 12 (510, p) are connected to the match line ML509 at address 509 without being grounded.

  Among the NMOS transistors 9 (511, p) to 12 (511, p) in the memory cell 3 (511, p) at address 511, the NMOS has a gate connected to the search bus SB (p) or XSB (p) The sources of the transistors 11 (511, p) and 12 (511, p) are connected to the match line ML510 at address 510 without being grounded.

  That is, in the memory cell array 32, the NMOS transistor 9 (4q + 1) in the memory cell 3 (4q + 1, p) at the address 4q + 1 (however, q = 0, 1, 2,..., 127, the same applies hereinafter). , P) to 12 (4q + 1, p), the sources of the NMOS transistors 11 (4q + 1, p) and 12 (4q + 1, p) whose gates are connected to the search bus SB (p) or XSB (p) are Without being grounded, it is connected to the match line ML4q at address 4q.

  Of the NMOS transistors 9 (4q + 2, p) to 12 (4q + 2, p) in the memory cell 3 (4q + 2, p) at the address 4q + 2, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (4q + 2, p) and 12 (4q + 2, p) are connected to the match line ML (4q + 1) at address 4q + 1 without being grounded.

  Of the NMOS transistors 9 (4q + 3, p) to 12 (4q + 3, p) in the memory cell 3 (4q + 3, p) at the address 4q + 3, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (4q + 3, p) and 12 (4q + 3, p) are connected to the match line ML (4q + 2) at address 4q + 2 without being grounded. In other respects, the memory cell array 32 is configured similarly to the memory cell array 16 shown in FIG.

  Also in the second embodiment of the present invention configured as described above, before the search (during standby), the match lines ML0 to ML511 are precharged to the H level and the search buses SB (p) and XSB (p ) Is at L level. When the search data DIN coincides with the storage data at the address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)) during the search, the match line ML0 is in the H level state. Is maintained. As a result, the NMOS transistors 11 (1, p), 12 (1, p) in the memory cell 3 (1, p) at the address 1 are deactivated, and the memory cell 3 (1, p) at the address 1 is targeted. Is not executed. Accordingly, the match line ML1 at address 1 is maintained at the H level.

  As a result, the NMOS transistors 11 (2, p) and 12 (2, p) in the memory cell 3 (2, p) at the address 2 are deactivated, and the memory cell 3 (2, p) at the address 2 is deactivated. Searches for are not performed. Therefore, the match line ML2 at address 2 is maintained at the H level. As a result, the NMOS transistors 11 (3, p) and 12 (3, p) in the memory cell 3 (3, p) at address 3 are deactivated, and the memory cell 3 (3, p) at address 3 is deactivated. Searches for are not performed. Therefore, the match line ML3 at address 3 is maintained at the H level.

  On the other hand, when the search data DIN does not match the storage data at address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)), the match line ML0 is L Become a level. As a result, the NMOS transistors 11 (1, p) and 12 (1, p) in the memory cell 3 (1, p) at the address 1 are activated, and the memory cell 3 (1, p) at the address 1 is targeted. Search is performed.

  Here, for example, if the search data DIN matches the storage data at the first address (that is, the storage data of the memory cells 3 (1, 0) to 3 (1, n-1)), the match line ML1 at the first address is H. The level state is maintained. As a result, the NMOS transistors 11 (2, p) and 12 (2, p) in the memory cell 3 (2, p) at address 2 are deactivated, and the memory cell 3 (2, p) at address 2 is targeted. Is not executed. Therefore, the match line ML2 at address 2 is maintained at the H level.

  As a result, the NMOS transistors 11 (3, p) and 12 (3, p) in the memory cell 3 (3, p) at address 3 are deactivated, and the memory cell 3 (3, p) at address 3 is deactivated. Searches for are not performed. Therefore, the match line ML3 at address 3 is maintained at the H level.

  On the other hand, as a result of performing a search on the memory cells (1, 0) to 3 (1, n-1) at address 1 after address 0, search data DIN is stored data at address 1 (ie, When there is a mismatch with the memory cells 3 (1, 0) to 3 (1, n-1), the match line ML1 at address 1 is at the L level. As a result, the NMOS transistors 11 (2, p) and 12 (2, p) in the memory cell 3 (2, p) at the address 2 are activated, and the memory cell 3 (2, p) at the address 2 is targeted. Search is performed.

  Here, for example, when the search data DIN matches the storage data at the address 2 (that is, the storage data of the memory cells 3 (2, 0) to 3 (2, n-1)), the match line ML2 at the address 2 is H. The level state is maintained. As a result, the NMOS transistors 11 (3, p) and 12 (3, p) in the memory cell 3 (3, p) at address 3 are deactivated, and the memory cell 3 (3, p) at address 3 is targeted. Is not executed. In this case, the state of the match line ML3 at address 3 = H level is maintained.

  That is, in the second embodiment of the present invention, when the search data DIN matches the stored data at the address 4q, the match lines ML (4q + 1) to ML (4q + 3) at the addresses 4q + 1 to 4q + 3 maintain the H level. Therefore, when returning to the standby state after the search, the match lines ML (4q + 1) to ML (4q + 3) at addresses 4q + 1 to 4q + 3 do not need to be charged.

  When the search data DIN does not match the stored data at the address 4q and matches the stored data at the address 4q + 1, the match lines ML (4q + 2) and ML (4q + 3) at the addresses 4q + 2 and 4q + 3 maintain the H level. Therefore, when returning to the standby state after the search, it is not necessary to charge the match lines ML (4q + 2) and ML (4q + 3) at addresses 4q + 2 and 4q + 3.

  Also, if the search data DIN does not match the stored data at addresses 4q and 4q + 1 and matches the stored data at address 4q + 2, the match line ML (4q + 3) at address 4q + 3 maintains the H level. When returning to the standby state, the match line ML (4q + 3) at address 4q + 3 does not need to be charged.

  Therefore, according to the second embodiment of the present invention, after the search, the number of match lines that require charging when returning to the standby state is reduced to that of the first embodiment of the present invention, thereby reducing current consumption. be able to.

(Third embodiment)
FIG. 8 is a circuit diagram showing a part of the third embodiment of the present invention. In the third embodiment of the present invention, a memory cell array 33 having a configuration different from that of the memory cell array 16 included in the conventional associative memory shown in FIG. 25 is provided, and ground lines MGL0, MGL2,. MGL 510 is provided, and a ground line driver (MGLD) unit 34 is provided corresponding to the ground lines MGL 0, MGL 2,..., MGL 510. is there.

  FIG. 9 is a circuit diagram showing a configuration of the memory cell array 33. In FIG. 9, the first and nth bit memory cells 3 (0, 0) and 3 (0, n−1) at address 0 and the first and nth bit memory cells 3 (1 , 0), 3 (1, n-1), and the first and nth bit memory cells 3 (510, 0), 3 (510, n-1), and the first bit at address 511. And n-th bit memory cells 3 (511, 0) and 3 (511, n−1) are shown, and the others are not shown.

  Here, for example, among the NMOS transistors 9 (1, p) to 12 (1, p) in the memory cell 3 (1, p) at the address 1, the gate is connected to the search bus SB (p) or XSB (p). The sources of the connected NMOS transistors 11 (1, p) and 12 (1, p) are not grounded but are connected to the ground line MGL0 at address 0.

  For example, among the NMOS transistors 9 (511, p) to 12 (511, p) in the memory cell 3 (511, p) at the address 511, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (511, p) and 12 (511, p) are connected to the ground line MGL 510 at the address 510 without being grounded.

  That is, the memory cell array 33 is provided with ground lines MGL2m corresponding to addresses 0 and even, that is, addresses 2m, and NMOS transistors 9 (2m + 1, p) to 12m in the memory cell 3 (2m + 1, p) at address 2m + 1. Of (2m + 1, p), the sources of the NMOS transistors 11 (2m + 1, p) and 12 (2m + 1, p) whose gates are connected to the search bus SB (p) or XSB (p) are not grounded. It is connected to the ground line MGL2m at address 2m, and the others are configured similarly to the memory cell array 16 shown in FIG.

  FIG. 10 is a circuit diagram showing a configuration of the ground line driver unit 34. In FIG. 10, 35 (0) is a ground line driver provided corresponding to the ground line MGL0, 35 (2) is a ground line driver provided corresponding to the ground line MGL2, and 35 (510) is ground. A ground line driver provided corresponding to the line MGL 510, and ground line drivers 35 (4), 35 (6),... Provided corresponding to the ground line drivers MGL4, MGL6,. 35 (508) is not shown.

  The ground line driver 35 (0) includes an inverter 36 (0) and an NMOS transistor 37 (0). The inverter 36 (0) has an input terminal connected to the search result signal line 38 (0). The NMOS transistor 37 (0) has a gate connected to the output terminal of the inverter 36 (0), a drain connected to the ground line MGL0, and a source grounded.

  The ground line driver 35 (2) includes an inverter 36 (2) and an NMOS transistor 37 (2). The inverter 36 (2) has an input terminal connected to the search result signal line 38 (2). The NMOS transistor 37 (2) has a gate connected to the output terminal of the inverter 36 (2), a drain connected to the ground line MGL2, and a source grounded.

  The ground line driver 35 (510) includes an inverter 36 (510) and an NMOS transistor 37 (510). The inverter 36 (510) has an input terminal connected to the search result signal line 38 (510). The NMOS transistor 37 (510) has a gate connected to the output terminal of the inverter 36 (510), a drain connected to the ground line MGL510, and a source grounded. The ground line drivers 35 (4), 35 (6),..., 35 (508) are similarly configured.

  That is, the ground line driver unit 34 includes a ground line driver 35 (2m) corresponding to the ground line MGL2m. The ground line driver 35 (2m) includes an inverter 36 (2m) and an NMOS transistor 37 ( 2m). The inverter 36 (2m) has its input terminal connected to the search result signal line 38 (2m), the NMOS transistor 37 (2m) has its gate connected to the output terminal of the inverter 36 (2m), and its drain connected to the ground line. It is connected to MGL2m and the source is grounded.

  Here, for example, when the search result signal MS2mZ is H level, the output of the inverter 36 (2m) is L level, the NMOS transistor 37 (2m) is OFF, and the ground line MGL2m is floating. On the other hand, when the search result signal MS2mZ is L level, the output of the inverter 36 (2m) is H level, the NMOS transistor 37 (2m) is ON, and the ground line MGL2m is connected via the NMOS transistor 37 (2m). Grounded.

  11 and 12 are timing charts showing an example of a search operation according to the third embodiment of the present invention. FIG. 11 shows a case where the search data DIN does not match the stored data at addresses 0 and 1, and FIG. 12 shows a case where the search data DIN matches the stored data at address 0.

  11A and 12B, (A) is a clock signal CLK that determines an operation cycle, (B) is a search command signal XSER, (C) is a search command decode signal SERZ, (D) is a search driver activation signal SBEZ, ( E) is the level of the search buses SB (p) and XSB (p), (F) is the level of the match line ML0, (G) is the search result signal MS0Z, (H) is the level of the match line ML1, and (I) is A search result signal MS1Z is shown.

  That is, in the third embodiment of the present invention, before search (during standby), the search command signal XSER is at H level, the search command decode signal SERZ is at L level, the search driver activation signal SBEZ is at L level, and the search bus SB (p) and XSB (p) are set to L level, match lines ML0 to ML511 are set to H level, and search result signals MS0Z to MS511Z are set to H level.

  At the time of the search, as shown in FIGS. 11 and 12, the search command signal XSER is set to the L level, the search is instructed, and the search data DIN = is supplied to the search drivers 28 (0) to 28 (n−1). D (0) to D (n-1) are given. As a result, the command decoder 23 sets the search command decode signal SERZ to H level, and in response to this, the search driver activation signal generation circuit 24 sets the search driver activation signal SBEZ to H level, and the search driver 28 (p ) Sets one of the search buses SB (p) and XSB (p) to the H level and the other to the L level corresponding to the value of the search data D (p).

  Here, for example, when the search data DIN does not match the storage data at address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)), as shown in FIG. Since the match line ML0 at address 0 is at L level and the search result signal MS0Z is at L level, the output of the inverter 36 (0) is H level, the NMOS transistor 37 (0) is ON, and the ground line MGL0 is NMOS It is grounded through transistor 37 (0).

  As a result, the NMOS transistors 11 (1, p) and 12 (1, p) in the memory cell 3 (1, p) at the address 1 are activated, and the memory cell 3 (1, p) at the address 1 is targeted. A search is performed. As a result of the search, if the search data DIN does not match the storage data at the address 1 (that is, the storage data of the memory cells 3 (1, 0) to 3 (1, n-1)), as shown in FIG. The match line ML1 at address 1 is at L level, and the search result signal MS1Z is at L level.

  On the other hand, if the search data DIN matches the storage data at address 0 (that is, the storage data of memory cells 3 (0, 0) to 3 (0, n−1)), as shown in FIG. Since the match line ML0 at the address is maintained at the H level and the search result signal MS0Z is also maintained at the H level, the output of the inverter 36 (0) is maintained at the L level and the NMOS transistor 37 (0) is maintained OFF. The ground line MGL0 maintains the floating state.

  As a result, the NMOS transistors 11 (1, p), 12 (1, p) in the memory cell 3 (1, p) at the address 1 are deactivated, and the memory cell 3 (1, p) at the address 1 is targeted. Is not executed. Therefore, in this case, the match line ML1 at the first address is maintained at the H level, and the match line ML1 at the first address does not need to be charged when returning to the standby state after the search.

  That is, according to the third embodiment of the present invention, when the search data DIN matches the stored data at the address 2m, the match line ML (2m + 1) at the address 2m + 1 maintains the H level. When returning to the state, there is no need to charge the match line ML (2m + 1) at address 2m + 1. Therefore, after searching, the number of match lines that need to be charged when returning to the standby state is reduced, and the current consumption is reduced. Can be achieved.

(Fourth embodiment)
FIG. 13 is a circuit diagram showing a part of the fourth embodiment of the present invention. In the fourth embodiment of the present invention, a memory cell array 40 having a configuration different from that of the memory cell array 16 included in the conventional associative memory shown in FIG. 25 is provided. The other components are the same as those of the conventional associative memory shown in FIG.

  FIG. 14 is a circuit diagram showing a configuration of the memory cell array 40. In FIG. 14, the memory cells 3 (0, 0) and 3 (0, n−1) at the first bit and the nth bit at address 0, and the memory cell 3 (1 at the first and nth bits at address 1). , 0), 3 (1, n-1), memory cell 3 (2, 0), 3 (2, n-1) at the first and nth bits at address 2, and the first bit at address 3. And n-th bit memory cells 3 (3, 0), 3 (3, n−1) are shown, and the others are not shown.

  Here, for example, among the NMOS transistors 9 (1, p) to 12 (1, p) in the memory cell 3 (1, p) at the address 1, the gate is connected to the search bus SB (p) or XSB (p). The sources of the connected NMOS transistors 11 (1, p) and 12 (1, p) are not grounded but are connected to the ground line MGL0 at address 0.

  Of the NMOS transistors 9 (2, p) to 12 (2, p) in the memory cell 3 (2, p) at the address 2, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (2, p) and 12 (2, p) are connected to the ground line MGL1 at the first address without being grounded.

  Of the NMOS transistors 9 (3, p) to 12 (3, p) in the memory cell 3 (3, p) at address 3, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (3, p), 12 (3, p) are connected to the second ground line MGL2.

  That is, in the memory cell array 40, among the NMOS transistors 9 (4q + 1, p) to 12 (4q + 1, p) in the memory cell 3 (4q + 1, p) at the address 4q + 1, the gate is the search bus SB (p) or XSB ( The sources of the NMOS transistors 11 (4q + 1, p) and 12 (4q + 1, p) connected to p) are not grounded but are connected to the ground line MGL4q at address 4q.

  Of the NMOS transistors 9 (4q + 2, p) to 12 (4q + 2, p) in the memory cell 3 (4q + 2, p) at the address 4q + 2, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (4q + 2, p) and 12 (4q + 2, p) are connected to the ground line MGL (4q + 1) at address 4q + 1 without being grounded.

  Of the NMOS transistors 9 (4q + 3, p) to 12 (4q + 3, p) in the memory cell 3 (4q + 3, p) at the address 4q + 3, the gate is connected to the search bus SB (p) or XSB (p). The sources of the NMOS transistors 11 (4q + 3, p) and 12 (4q + 3, p) are connected to the ground line MGL (4q + 2) at address 4q + 2 without being grounded. In other respects, the memory cell array 40 is configured in the same manner as the memory cell array 16 shown in FIG.

  FIG. 15 is a circuit diagram showing a configuration of the ground line driver unit 41. In FIG. 15, 42 (0) is a ground line driver provided corresponding to the ground line MGL0, 42 (1) is a ground line driver provided corresponding to the ground line MGL1, and 42 (2) is a ground. A ground line driver provided corresponding to the line MGL2, and ground line drivers 42 (4) to 42 (6) provided corresponding to the ground lines MGL4 to MGL6, MGL8 to MGL10,..., MGL508 to MGL510. ), 42 (8) to 42 (10),..., 42 (508) to 42 (510) are not shown.

  Here, for example, the ground line driver 42 (0) includes an inverter 43 (0) and an NMOS transistor 44 (0). The inverter 43 (0) has an input terminal connected to the search result signal line 38 (0). The NMOS transistor 44 (0) has a gate connected to the output terminal of the inverter 43 (0), a drain connected to the ground line MGL0, and a source grounded.

  The ground line driver 42 (1) includes an inverter 43 (1) and an NMOS transistor 44 (1). The inverter 43 (1) has an input terminal connected to the search result signal line 38 (1). The NMOS transistor 44 (1) has a gate connected to the output terminal of the inverter 43 (1), a drain connected to the ground line MGL1, and a source grounded.

  The ground line driver 42 (2) includes an inverter 43 (2) and an NMOS transistor 44 (2). The inverter 43 (2) has an input terminal connected to the search result signal line 38 (2). The NMOS transistor 44 (2) has a gate connected to the output terminal of the inverter 43 (2), a drain connected to the ground line MGL2, and a source grounded.

  That is, the ground line driver unit 41 is provided with a ground line driver 42 (4q) corresponding to the ground line MGL4q, and is provided with a ground line driver 42 (4q + 1) corresponding to the ground line MGL (4q + 1). A ground line driver 42 (4q + 2) is provided corresponding to the line MGL (4q + 2).

  The ground line driver 42 (4q) includes an inverter 43 (4q) and an NMOS transistor 44 (4q). The inverter 43 (4q) has an input terminal connected to the search result signal line 38 (4q). The NMOS transistor 44 (4q) has a gate connected to the output terminal of the inverter 43 (4q), a drain connected to the ground line MGL4q, and a source grounded.

  The ground line driver 42 (4q + 1) includes an inverter 43 (4q + 1) and an NMOS transistor 44 (4q + 1). The inverter 43 (4q + 1) has an input terminal connected to the search result signal line 38 (4q + 1). The NMOS transistor 44 (4q + 1) has a gate connected to the output terminal of the inverter 43 (4q + 1), a drain connected to the ground line MGL (4q + 1), and a source grounded.

  The ground line driver 42 (4q + 2) includes an inverter 43 (4q + 2) and an NMOS transistor 44 (4q + 2). The inverter 43 (4q + 2) has an input terminal connected to the search result signal line 38 (4q + 2). The NMOS transistor 44 (4q + 2) has a gate connected to the output terminal of the inverter 43 (4q + 2), a drain connected to the ground line MGL (4q + 2), and a source grounded.

  Here, for example, when the search result signal MS4qZ is H level, the output of the inverter 43 (4q) is L level, the NMOS transistor 44 (4q) is OFF, and the ground line MGL4q is floating. On the other hand, when the search result signal MS4qZ is L level, the output of the inverter 43 (4q) is H level, the NMOS transistor 44 (4q) is ON, and the ground line MGL4q is connected via the NMOS transistor 44 (4q). Grounded.

  For example, when the search result signal MS (4q + 1) Z is at the H level, the output of the inverter 43 (4q + 1) is at the L level, the NMOS transistor 44 (4q + 1) is OFF, and the ground line MGL (4q + 1) is in a floating state. On the other hand, when the search result signal MS (4q + 1) Z is L level, the output of the inverter 43 (4q + 1) is H level, the NMOS transistor 44 (4q + 1) is ON, and the ground line MGL (4q + 1) is NMOS transistor 44 (4q + 1).

  For example, when the search result signal MS (4q + 2) Z is at the H level, the output of the inverter 43 (4q + 2) is at the L level, the NMOS transistor 44 (4q + 2) is OFF, and the ground line MGL (4q + 2) is in a floating state. On the other hand, when the search result signal MS (4q + 2) Z is L level, the output of the inverter 43 (4q + 2) is H level, the NMOS transistor 44 (4q + 2) is ON, and the ground line MGL (4q + 2) is NMOS transistor 44 (4q + 2).

  In the fourth embodiment of the present invention configured as described above, before the search (during standby), the match lines ML0 to ML511 are precharged to the H level, and the search buses SB (p) and XSB (p ) Is at L level. When the search data DIN coincides with the storage data at the address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)) during the search, the match line ML0 is in the H level state. And the search result signal MS0Z is also maintained at the H level, the output of the inverter 43 (0) is maintained at the L level, the NMOS transistor 44 (0) is maintained OFF, and the ground line MGL0 is maintained in the floating state. To do.

  As a result, the NMOS transistors 11 (1, p), 12 (1, p) in the memory cell 3 (1, p) at the address 1 are deactivated, and the memory cell 3 (1, p) at the address 1 is targeted. Is not executed. Accordingly, the match line ML1 at address 1 is maintained at the H level, and the search result signal MS1Z is also maintained at the H level. Therefore, the output of the inverter 43 (1) is at the L level, and the NMOS transistor 44 (1) OFF is maintained, and the ground line MGL1 is maintained in a floating state.

  As a result, the NMOS transistors 11 (2, p) and 12 (2, p) in the memory cell 3 (2, p) at address 2 are deactivated, and the memory cell 3 (2, p) at address 2 is targeted. Is not executed. Therefore, the match line ML2 at address 2 is maintained at the H level, and the search result signal MS2Z is also maintained at the H level. Therefore, the output of the inverter 43 (2) is at the L level, and the NMOS transistor 44 (2) OFF is maintained, and the ground line MGL2 maintains a floating state. As a result, the NMOS transistors 11 (3, p) and 12 (3, p) in the memory cell 3 (3, p) at address 3 are deactivated, and the memory cell 3 (3, p) at address 3 is targeted. Is not executed. Therefore, the match line ML3 at address 3 is maintained at the H level.

  On the other hand, if the search data DIN does not match the storage data at the address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)), the match line at the address 0 ML0 is L level, the search result signal MS0Z is L level, the output of the inverter 43 (0) is H level, the NMOS transistor 44 (0) is ON, and the ground line MGL0Z is grounded via the NMOS transistor 44 (0). Is done. As a result, the NMOS transistors 11 (1, p) and 12 (1, p) in the memory cell 3 (1, p) at the address 1 are activated, and the memory cell 3 (1, p) at the address 1 is targeted. Search is performed.

  Here, for example, if the search data DIN matches the storage data at the address 1 (that is, the storage data of the memory cells 3 (1, 0) to 3 (1, n-1)), the match line ML1 at the address 1 is H. Since the level state is maintained and the search result signal MS1Z is also maintained at the H level, the output of the inverter 43 (1) is maintained at the L level, the NMOS transistor 44 (1) is maintained OFF, and the ground line MGL1 is floating. Maintain state.

  As a result, the NMOS transistors 11 (2, p) and 12 (2, p) in the memory cell 3 (2, p) at address 2 are deactivated, and the memory cell 3 (2, p) at address 2 is targeted. Is not executed. Therefore, the match line ML2 at address 2 is maintained at the H level, and the search result signal MS2Z is also maintained at the H level. Therefore, the output of the inverter 43 (2) is at the L level, and the NMOS transistor 44 (2) OFF is maintained, and the ground line MGL2 maintains a floating state. As a result, the NMOS transistors 11 (3, p) and 12 (3, p) in the memory cell 3 (3, p) at address 3 are deactivated, and the memory cell 3 (3, p) at address 3 is targeted. Is not executed. Therefore, the match line ML3 at address 3 is maintained at the H level.

  On the other hand, as a result of performing a search on the memory cells (1, 0) to 3 (1, n-1) at address 1 after address 0, search data DIN is stored data at address 1 (ie, If there is a mismatch with the memory cells 3 (1, 0) to 3 (1, n-1), the match line ML1 at address 1 is at the L level, the search result signal MS1Z is at the L level, and the inverter 43 (1 ) Is at the H level, the NMOS transistor 44 (1) is turned on, and the ground line MGL2 is grounded via the NMOS transistor 44 (1). As a result, the NMOS transistors 11 (2, p) and 12 (2, p) in the memory cell 3 (2, p) at the address 2 are activated, and the memory cell 3 (2, p) at the address 2 is targeted. Search is performed.

  Here, for example, if the search data DIN matches the storage data at the address 2 (that is, the storage data of the memory cells 3 (2, 0) to 3 (2, n-1)), the match line ML2 at the address 2 is H. Since the level state is maintained and the search result signal MS2Z is also maintained at the H level, the output of the inverter 43 (2) is maintained at the L level, the NMOS transistor 44 (2) is maintained OFF, and the ground line MGL2 is in the floating state. maintain. As a result, the NMOS transistors 11 (3, p) and 12 (3, p) in the memory cell 3 (3, p) at address 3 are deactivated, and the memory cell 3 (3, p) at address 3 is targeted. Is not executed. Therefore, the match line ML3 at address 3 is maintained at the H level.

  That is, in the fourth embodiment of the present invention, when the search data DIN matches the stored data at the address 4q, the match lines ML (4q + 1) to ML (4q + 3) at the addresses 4q + 1 to 4q + 3 maintain the H level. Therefore, when returning to the standby state after the search, the match lines ML (4q + 1) to ML (4q + 3) at addresses 4q + 1 to 4q + 3 do not need to be charged.

  When the search data DIN does not match the stored data at the address 4q and matches the stored data at the address 4q + 1, the match lines ML (4q + 2) and ML (4q + 3) at the addresses 4q + 2 and 4q + 3 maintain the H level. Therefore, when returning to the standby state after the search, it is not necessary to charge the match lines ML (4q + 2) and ML (4q + 3) at addresses 4q + 2 and 4q + 3.

  Also, if the search data DIN does not match the stored data at addresses 4q and 4q + 1 and matches the stored data at address 4q + 2, the match line ML (4q + 3) at address 4q + 3 maintains the H level. When returning to the standby state, the match line ML (4q + 3) at address 4q + 3 does not need to be charged.

  Therefore, according to the fourth embodiment of the present invention, after the search, the number of match lines that require charging when returning to the standby state is reduced to more than the third embodiment of the present invention, thereby reducing current consumption. be able to.

(Other)
In the first to fourth embodiments of the present invention, the case where a binary type memory cell is used has been described. In addition, the present invention, for example, uses a ternary (as shown in FIG. A ternary type memory cell can also be used. In FIG. 16, 46 is a flip-flop which is one storage medium, and 47 and 48 are inverters. Further, S0 and S1 are storage nodes, and 49 and 50 are NMOS transistors whose ON and OFF are controlled by the potential of the word line WL. 51 is a flip-flop which is the other storage medium, and 52 and 53 are inverters. S3 and S4 are storage nodes, and 54 and 55 are NMOS transistors whose ON and OFF are controlled by the potential of the word line WL.

  56 is an NMOS transistor whose ON / OFF is controlled by the potential of the storage node S1, 57 is an NMOS transistor whose ON / OFF is controlled by the potential of the storage node S4, and 58 is ON / OFF controlled by the potential of the search bus SB. An NMOS transistor 59 is an NMOS transistor whose ON and OFF are controlled by the potential of the search bus XSB.

  16 uses the word line WL, the bit lines BL0, XBL0, BL1, and XBL1 and the NMOS transistors 49, 50, 54, and 55 for writing data to and reading data from the memory cell shown in FIG. Done. Table 3 shows the relationship between the memory cell storage data and the logical values of the bit lines BL0, XBL0, BL1, and XBL1 when data is written to and read from the memory cell shown in FIG. Yes.

  The search for the memory cell shown in FIG. 16 is performed using the search buses SB and XSB, the NMOS transistors 56 to 59, and the match line ML. Table 4 shows the relationship between the data stored in the memory cell and the logical values of the search buses SB and XSB at the time of search.

  In the first to fourth embodiments of the present invention, for the NMOS transistors 9 to 12 used in the search, the NMOS transistors 9 and 10 whose gates are connected to the storage node S0 or S1 are in the upper stage, The case where the NMOS transistors 11 and 12 connected to the search bus SB or XSB are connected so as to be in the lower stage has been described. The NMOS transistors 9 and 10 connected to may be connected at the lower stage.

  In the first to fourth embodiments of the present invention, the case where the SRAM cell is used as the memory cell has been described. However, the present invention is also applicable to the case where a memory cell other than the SRAM cell is used. Of course you can.

  In the first and third embodiments of the present invention, the level control of the match line at the higher address is performed in units of two consecutive addresses. In the second and fourth embodiments of the present invention, In the above description, the level control of the upper address match line is performed in units of four consecutive addresses. However, the number of addresses constituting the unit for performing the level control of the upper address match line is not limited to these. For example, 8 addresses, 16 addresses, 32 addresses, etc. can be used as a unit.

It is a circuit diagram showing a part of a 1st embodiment of the present invention. 1 is a circuit diagram showing a configuration of a memory cell array included in a first embodiment of the present invention. It is a timing diagram for demonstrating the example of search operation of 1st Embodiment of this invention. It is a timing diagram for demonstrating the example of search operation of 1st Embodiment of this invention. It is a timing diagram for demonstrating the example of search operation of 1st Embodiment of this invention. It is a circuit diagram which shows a part of 2nd Embodiment of this invention. It is a circuit diagram which shows a part of 2nd Embodiment of this invention. It is a circuit diagram which shows a part of 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the memory cell array with which 3rd Embodiment of this invention is provided. It is a circuit diagram which shows the structure of the ground line driver part with which 3rd Embodiment of this invention is provided. It is a timing diagram for demonstrating the search operation example of 3rd Embodiment of this invention. It is a timing diagram for demonstrating the search operation example of 3rd Embodiment of this invention. It is a circuit diagram which shows a part of 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the memory cell array with which 4th Embodiment of this invention is provided. It is a circuit diagram which shows the structure of the ground line driver part with which 4th Embodiment of this invention is provided. It is a circuit diagram which shows the other example of the memory cell which can be used for this invention. It is a figure for demonstrating the function of an associative memory compared with RAM. It is a circuit diagram which shows an example of the memory cell with which an associative memory is provided. FIG. 19 is a circuit diagram for illustrating a search operation for the memory cell shown in FIG. 18. FIG. 19 is a circuit diagram for illustrating a search operation for the memory cell shown in FIG. 18. FIG. 19 is a circuit diagram for illustrating a search operation for the memory cell shown in FIG. 18. FIG. 19 is a circuit diagram for illustrating a search operation for the memory cell shown in FIG. 18. FIG. 19 is a waveform diagram showing potential changes of a search bus and a match line during a search for the memory cell shown in FIG. 18. It is a circuit diagram which shows the relationship between the memory cell in an actual associative memory, and a match line. It is a block diagram which shows a part of example of the conventional associative memory. FIG. 26 is a circuit diagram showing a part of the conventional content addressable memory shown in FIG. 25 in more detail. FIG. 26 is a circuit diagram showing in more detail a portion of a memory cell array included in the conventional content addressable memory shown in FIG. 25. FIG. 26 is a circuit diagram for explaining a search operation example of the conventional associative memory shown in FIG. 25. FIG. 26 is a timing diagram for explaining an example of a search operation of the conventional associative memory shown in FIG. 25. FIG. 26 is a timing diagram for explaining an example of a search operation of the conventional associative memory shown in FIG. 25. It is a figure for demonstrating the priority matching function which the conventional associative memory shown in FIG. 25 has.

Explanation of symbols

1 ... RAM
2 ... Associative memory (CAM)
3 ... Memory cell (MC)
4 ... flip-flop 5, 6 ... inverter 7-12 ... NMOS transistor 15 ... match line sense amplifier (MLSA)
DESCRIPTION OF SYMBOLS 16 ... Memory cell array 17 ... Word decoder (WDEC) part 18 ... Write amplifier (W / A) part 19 ... Sense amplifier (S / A) part 20 ... Search driver (S / D) part 21 ... Match line sense amplifier ( MLSA) 22: Encoder (ENC)
23 ... Command decoder (COMDEC)
24 ... Search driver activation signal generation circuit (SBBEGEN)
25 ... Word driver (WDEC)
26 ... Light amplifier (W / A)
27 ... Sense amplifier (S / A)
28 ... Search driver (S / D)
31-33 ... Memory cell array 34 ... Ground line driver unit 35 ... Ground line driver 36 ... Inverter 37 ... NMOS transistor 40 ... Memory cell array 41 ... Ground line driver unit 42 ... Ground line driver 43 ... Inverter 44 ... NMOS transistor 46 ... flip-flop 47, 48 ... inverter 49, 50 ... NMOS transistor 51 ... flip-flop 52, 53 ... inverter 54-59 ... NMOS transistor

Claims (5)

A first memory cell portion;
A second memory cell portion to which search data is given simultaneously with the first memory cell portion;
A first match line provided corresponding to the first memory cell portion and precharged before search;
A second match line provided corresponding to the second memory cell portion and precharged before search;
With
Said first memory cell unit, when the search data to the search time does not match the own storage data, to discharge the first match line, when the search data matches the own storage data, the Configured to not discharge the first match line,
When the search data does not match the stored data of the first memory cell unit when the search data does not match the stored data of the first memory cell unit during the search, the second memory cell unit When the line is discharged and the search data matches its own storage data, the second match line is not discharged, and when the search data matches the storage data of the first memory cell unit, An associative memory characterized in that the second match line is not discharged regardless of whether the search data and its stored data match or not. The memory cells of the first memory cell portion are
A first switch element having one end connected to the first match line and controlled to be turned on and off by a potential of the first storage node;
A second switch element having one end connected to the first match line and controlled to be turned on and off by a potential of a second storage node;
A third switch element having one end connected to the other end of the first switch element, the other end grounded, and being controlled to be turned on / off by the potential of one search bus;
A fourth switch element having one end connected to the other end of the second switch element, the other end grounded, and on / off controlled by the potential of the other search bus;
With
The memory cells of the second memory cell portion are
A fifth switch element having one end connected to the second match line and controlled to be turned on and off by a potential of a third storage node;
A sixth switch element having one end connected to the second match line and controlled to be turned on / off by the potential of the fourth storage node;
A seventh switch element having one end connected to the other end of the fifth switch element, the other end connected to the first match line, and being controlled to be turned on and off by the potential of the one search bus;
An eighth switch element having one end connected to the other end of the sixth switch element, the other end connected to the first match line, and on / off controlled by the potential of the other search bus;
The associative memory according to claim 1, further comprising: The memory cells of the first memory cell portion are
A first switch element having one end connected to the first match line and controlled to be turned on and off by a potential of the first storage node;
A second switch element having one end connected to the first match line and controlled to be turned on and off by a potential of a second storage node;
A third switch element having one end connected to the other end of the first switch element, the other end grounded, and being controlled to be turned on / off by the potential of one search bus;
A fourth switch element having one end connected to the other end of the second switch element, the other end grounded, and on / off controlled by the potential of the other search bus;
With
The memory cells of the second memory cell portion are
A fifth switch element having one end connected to the second match line and controlled to be turned on and off by a potential of a third storage node;
A sixth switch element having one end connected to the second match line and controlled to be turned on / off by the potential of the fourth storage node;
A seventh switch element having one end connected to the other end of the fifth switch element, the other end connected to a ground line, and being turned on and off by the potential of the one search bus;
An eighth switch element having one end connected to the other end of the sixth switch element, the other end connected to the ground line, and on / off controlled by the potential of the other search bus;
With
Further, during the search, when the first match line maintains the precharge potential, the ground line is set to a floating state. When the first match line falls to the ground potential, the ground line is set to the ground potential. A ground line driver to
The associative memory according to claim 1, further comprising: The memory cells of the first memory cell portion are
A first switch element having one end connected to the first match line and controlled to be turned on and off by a potential of one search bus;
A second switch element having one end connected to the first match line and controlled to be turned on and off by the potential of the other search bus;
A third switch element having one end connected to the other end of the first switch element, the other end grounded, and being controlled to be turned on and off by the potential of the first storage node;
A fourth switch element having one end connected to the other end of the second switch element, the other end grounded, and being turned on and off by the potential of the second storage node;
With
The memory cells of the second memory cell portion are
A fifth switch element having one end connected to the second match line and controlled to be turned on / off by the potential of the one search bus;
A sixth switch element having one end connected to the second match line and controlled to be turned on / off by the potential of the other search bus;
A seventh switch element having one end connected to the other end of the fifth switch element, the other end connected to the first match line, and on / off controlled by a potential of a third storage node;
An eighth switch element having one end connected to the other end of the sixth switch element, the other end connected to the first match line, and being controlled to be turned on and off by a potential of a fourth storage node;
The associative memory according to claim 1, further comprising: The memory cells of the first memory cell portion are
A first switch element having one end connected to the first match line and controlled to be turned on and off by a potential of one search bus;
A second switch element having one end connected to the first match line and controlled to be turned on and off by the potential of the other search bus;
A third switch element having one end connected to the other end of the first switch element, the other end grounded, and being controlled to be turned on and off by the potential of the first storage node;
A fourth switch element having one end connected to the other end of the second switch element, the other end grounded, and being turned on and off by the potential of the second storage node;
With
The memory cells of the second memory cell portion are
A fifth switch element having one end connected to the second match line and controlled to be turned on / off by the potential of the one search bus;
A sixth switch element having one end connected to the second match line and controlled to be turned on / off by the potential of the other search bus;
A seventh switch element having one end connected to the other end of the fifth switch element, the other end connected to a ground line, and being controlled to be turned on / off by the potential of the third storage node;
An eighth switch element having one end connected to the other end of the sixth switch element, the other end connected to the ground line, and being controlled to be turned on / off by a potential of a fourth storage node;
With
Further, during the search, when the first match line maintains the precharge potential, the ground line is set to a floating state. When the first match line falls to the ground potential, the ground line is set to the ground potential. A ground line driver to
The associative memory according to claim 1, further comprising:

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