JP5119912B2 - Associative memory - Google Patents

Description

  The present invention retrieves an associative memory (CAM: Content Addressable Memory), that is, an address for storing the same data as search data given from the outside, and externally sends an address signal indicating the address for storing the same data as the search data. The present invention relates to a memory having an output function (so-called search function).

  FIG. 17 is a diagram for explaining the function of the associative memory in comparison with a RAM (Random Access Memory). In FIG. 17, 1 is a RAM and 2 is an associative memory. The RAM 1 is capable of writing and reading. As shown in (A), when a write command, an address signal, and data are given, data is written to the address indicated by the address signal, and (B ), When a read command and an address signal are given, data is read from the address indicated by the address signal and output.

  The associative memory 2 is capable of writing, reading, and searching. As shown in (C), when a write command, an address signal, and data are given, data writing to an address indicated by the address signal is performed. When a read command and an address signal are given as shown in (D), data is read out from the address indicated by the address signal and output, and as shown in (E), when a search command and data are given The address storing the same data as the given data is searched, and an address signal indicating the searched address is output.

  FIG. 18 is a circuit diagram showing an example of a memory cell provided in the associative memory. In FIG. 18, WL is a word line for selecting a memory cell at the time of writing / reading, BL and XBL are transmitted to the memory cell of complementary write data output from the write amplifier at the time of writing, and memory at the time of reading. Bit lines SB and XSB for transmitting the complementary read data read from the cell to the sense amplifier, the data obtained by complementing the search data given from the outside is transmitted from the search driver to the memory cell. A search bus ML is a match line for detecting a match or mismatch between the search data and the stored data of the memory cell, and 3 is a memory cell composed of SRAM (Static Random Access Memory) cells.

  In the memory cell 3, reference numeral 4 denotes a flip-flop forming a storage medium, reference numerals 5 and 6 denote inverters, and reference numerals S0 and S1 denote storage nodes. 7 and 8 are NMOS transistors whose ON / OFF is controlled by the potential of the word line WL, 9 is an NMOS transistor whose ON / OFF is controlled by the potential of the storage node S0, and 10 is ON / OFF by the potential of the storage node S1. An NMOS transistor to be controlled, 11 is an NMOS transistor whose ON / OFF is controlled by the potential of the search bus XSB, and 12 is an NMOS transistor whose ON / OFF is controlled by the potential of the search bus SB.

  In this example, data writing to the memory cell 3 and data reading from the memory cell 3 are performed using the word line WL, the bit lines BL and XBL, and the NMOS transistors 7 and 8. Table 1 shows the relationship between the data stored in the memory cell 3, the logical values of the storage nodes S0 and S1, and the logical values of the bit lines BL and XBL when data is written to and read from the memory cell 3. Yes.

  Here, when data “0” is written to the memory cell 3, the logical value of the word line WL = “1”, the state of the NMOS transistors 7 and 8 = ON, the logical value of the bit line BL = “0”, the bit By setting the logical value of the line XBL = “1”, the logical value of the storage node S0 = “0”, the logical value of the storage node S1 = “1”, and then the logical value of the word line WL = “0”, The state of the NMOS transistors 7 and 8 is set to OFF.

  On the other hand, when data “1” is written in the memory cell 3, the logical value of the word line WL = “1”, the state of the NMOS transistors 7 and 8 = ON, and the logical value of the bit line BL = “1”. By setting the logical value of the bit line XBL = “0”, the logical value of the storage node S0 = “1”, the logical value of the storage node S1 = “0”, and then the logical value of the word line WL = “0” "The state of the NMOS transistors 7 and 8 is set to OFF."

  When the storage data of the memory cell 3 is “0”, that is, when the logical value of the storage node S0 = “0” and the logical value of the storage node S1 = “1”, the logical value of the word line WL When the value = “1”, the state of the NMOS transistors 7 and 8 = ON, and data is read from the memory cell 3, the logical value of the bit line BL = “0” and the logical value of the bit line XBL = “1”.

  On the other hand, when the storage data of the memory cell 3 is “1”, that is, when the logical value of the storage node S0 = “1” and the logical value of the storage node S1 = “0”, the word line When the logical value of WL is “1”, the state of the NMOS transistors 7 and 8 is ON, and data is read from the memory cell 3, the logical value of the bit line BL is “1” and the logical value of the bit line XBL is “0”. It becomes.

  The search for the memory cell 3 is performed using the search buses SB and XSB, the NMOS transistors 9 to 12 and the match line ML. Table 2 shows the relationship between the storage data of the memory cell 3, the logical values of the storage nodes S0 and S1, the search data, the logical values of the search buses SB and XSB, and the logical value of the match line ML at the time of retrieval. FIG. 22 is a circuit diagram for explaining a search operation for the memory cell 3.

  In this example, at the time of non-search, the logical values of the search buses SB and XSB = “0”, and the states of the NMOS transistors 11 and 12 are OFF. On the other hand, at the time of search, the match line ML is precharged to the power supply voltage VDD, and its logical value is set to “1”. When the search data = "0", the logical value of the search bus SB = "0" and the logical value of the search bus XSB = "1". When the search data = "1", the search bus The logical value of SB = “1” and the logical value of search bus XSB = “0”.

  Here, as shown in FIG. 19, when the storage data of the memory cell 3 is “0” (that is, the logical value of the storage node S0 = “0” and the logical value of the storage node S1 = “1”). In this case, when “0” is input as the search data (that is, when the logical value of the search bus SB = “0” and the logical value of the search bus XSB = “1”), the NMOS transistor 9 Is OFF, the NMOS transistor 10 is ON, the NMOS transistor 11 is ON, and the NMOS transistor 12 is OFF, so that the logic value = “1” of the match line ML is maintained.

  On the other hand, as shown in FIG. 20, when the storage data of the memory cell 3 = “0” (that is, the logical value of the storage node S0 = “0” and the logical value of the storage node S1 = “1”). When “1” is input as search data (ie, when the logical value of the search bus SB = “1” and the logical value of the search bus XSB = “0”), the NMOS Since the transistor 9 is OFF, the NMOS transistor 10 is ON, the NMOS transistor 11 is OFF, and the NMOS transistor 12 is ON, the match line ML is grounded via the NMOS transistors 10 and 12, and the logical value of the match line ML is “ Transition to 0 ".

  Further, as shown in FIG. 21, when the storage data of the memory cell 3 is “1” (that is, the logical value of the storage node S0 is “1” and the logical value of the storage node S1 is “0”). ) Is input as search data (that is, when the logical value of the search bus SB = “1” and the logical value of the search bus XSB = “0”), the NMOS transistor 9 Since ON, the NMOS transistor 10 is OFF, the NMOS transistor 11 is OFF, and the NMOS transistor 12 is ON, the logical value = “1” of the match line ML is maintained.

  As shown in FIG. 22, when the storage data of the memory cell 3 is “1” (that is, when the logical value of the storage node S0 is “1” and the logical value of the storage node S1 is “0”). ) Is input as search data (that is, when the logic value of the search bus SB = “0” and the logic value of the search bus XSB = “1”), the NMOS transistor 9 Since ON, NMOS transistor 10 is OFF, NMOS transistor 11 is ON, and NMOS transistor 12 is OFF, match line ML is grounded via NMOS transistors 9 and 11, and the logical value of match line ML is “0”. Transition.

  FIG. 23 is a waveform diagram showing potential changes of the search buses SB and XSB and the match line ML at the time of search for the memory cell 3, wherein (A) shows potential changes of the search buses SB and XSB, and (B) shows the match line ML. It shows the potential change. As described above, the match line ML is precharged to the power supply voltage VDD (logic 1). However, when the search data and the storage data of the memory cell 3 do not match, the match line ML includes the NMOS transistors 9 and 11. Alternatively, it is grounded via the NMOS transistors 10 and 12, the potential of the match line ML drops to 0V (logic 0), and when the search data matches the data stored in the memory cell 3, the match line ML is grounded. First, the power supply voltage VDD (logic 1) is maintained.

  FIG. 24 is a circuit diagram showing the relationship between memory cells and match lines in an actual content addressable memory. In FIG. 24, 3 (0), 3 (1), 3 (2), and 3 (n-1) are memory cells, and the memory cells 3 (3) to 3 (n-2) are not shown. Yes. SB (0), XSB (0), SB (1), XSB (1), SB (2), XSB (2), SB (n-1), and XSB (n-1) are search buses, and search The buses SB (3), XSB (3) to SB (n-2), and XSB (n-2) are not shown.

  Reference numeral 15 denotes a match line sense amplifier (MLSA) that detects a potential change of the match line ML and outputs a search result signal MSZ during the search. The match line sense amplifier 15 sets the logical value of the search result signal MSZ = “1” when the logical value of the match line ML = “1”, and searches when the logical value of the match line ML = “0”. The logical value of the result signal MSZ = “0”.

  As shown in FIG. 24, in the actual associative memory, the relationship between the memory cell and the match line is not 1: 1, and the match line ML has the same number of memory cells 3 (0 as the number of search data bits). ) To 3 (n-1) are connected. The match line ML maintains “1” when the logical value of each bit of the search data composed of n bits matches the logical value of the data stored in the corresponding memory cell. Transitions to “0” when the logical value of this bit does not match the logical value of the data stored in the corresponding memory cell.

  FIG. 25 is a block diagram showing a part of an example of a conventional content addressable memory. In FIG. 25, 16 is a memory cell array in which 512 memory cell columns in which n memory cells having the configuration shown in FIG. 18 are arranged per row (one word line) are arranged, and 17 is a word decoder (word decoder for driving word lines). WDEC) is a word decoder unit, 18 is a write amplifier (W / A) group that writes to a memory cell, and 19 is a sense amplifier (S) that amplifies the data read to the bit line. / A) is a sense amplifier unit.

  20 is a search driver section that is a group of search drivers (S / D) that drives the search bus, 21 is a match line sense amplifier section that is a group of match line sense amplifiers (MLSA) that performs level detection of match lines, An encoder (ENC) 22 encodes the search result signal MSZ output from the match line / sense amplifier unit 21 and outputs an address signal indicating an address where the same data as the search data is stored.

  Reference numeral 23 is a command decoder (COMDEC) that decodes a search command signal given from the outside, and 24 is a search command decode signal output from the command decoder 23 and generates a search driver activation signal that is given to the search driver of the search driver unit 20. A search driver activation signal generation circuit (SBGEN).

  FIG. 26 is a circuit diagram showing a part of the conventional content addressable memory shown in FIG. 25 in more detail. In the memory cell array 16, 3 (0, 0) is the first bit memory cell in the first row, 3 (0, 1) is the second bit memory cell in the first row, and 3 (0, n-1) is The nth bit memory cell in the first row, and the memory cells 3 (0, 2) -3 (0, n-2) in the third row to the (n-1) th bit in the first row are not shown. Yes. 3 (1, 0) is the first bit memory cell in the second row, 3 (1, 1) is the second bit memory cell in the second row, 3 (1, n-1) is n in the second row The memory cells 3 (1, 2) to 3 (1, n-2) of the third bit to the (n-1) th bit in the second row are not shown.

  3 (511, 0) is the first bit memory cell in the 512th row, 3 (511, 1) is the second bit memory cell in the 512th row, and 3 (511, n-1) is n in the 512th row. The memory cells 3 (511, 2) to 3 (511, n-2) of the third bit to the (n-1) th bit in the 512th row are not shown. The memory cells 3 (2, 0) to 3 (2, n−1),..., 3 (510, 0) to 3 (510, n−1) in the third to 511th rows are not shown. ing. FIG. 27 shows in more detail the portion of the memory cell array 16 shown in FIG. In this example, the address of the memory cell column in the m-th row (however, m = 1, 2,..., 512, and so on) is the m−1 address.

  In FIG. 26, WL0 is the word line of the first row, WL1 is the word line of the second row, WL511 is the word line of the 512th row, and the word lines WL2 to WL510 of the third to 511th rows are illustrated. Is omitted. ML0 is the first match line, ML1 is the second match line, ML511 is the 512th match line, and the third to 511th match lines ML2 to ML510 are not shown.

  In the word decoder unit 17, 25 (0) is a word decoder provided corresponding to the first word line WL0, 25 (1) is a word decoder provided corresponding to the second word line WL1, 25 (511) is a word decoder provided corresponding to the word line WL511 of the 512th row, and a word decoder 25 (2) provided corresponding to the word lines WL2 to WL510 of the third row to 511th row. -25 (510) are not shown.

  In the write amplifier unit 18, 26 (0) is a write amplifier provided corresponding to the bit line BL (0) of the first bit and XBL (0), and 26 (1) is a bit line BL (1 of the second bit). ), A write amplifier provided corresponding to XBL (1), and 26 (n-1) is a write provided corresponding to the bit line BL (n-1), XBL (n-1) of the nth bit. A write amplifier 26 (corresponding to the bit lines BL (2), XBL (2) to BL (n-2), XBL (n-2) of the third bit to the (n-1) th bit. 2) to 26 (n-2) are not shown.

  In the sense amplifier unit 19, 27 (0) is a sense amplifier provided corresponding to the first bit line BL (0) and XBL (0), and 27 (1) is a second bit line BL (1 ), A sense amplifier provided corresponding to XBL (1), 27 (n-1) is a sense provided corresponding to the bit line BL (n-1), XBL (n-1) of the nth bit. Sense amplifier 27 (corresponding to the bit lines BL (2), XBL (2) to BL (n-2), XBL (n-2) of the third bit to the (n-1) th bit. 2) to 27 (n-2) are not shown.

  In the search driver unit 20, 28 (0) is a search driver provided corresponding to the first bit search bus SB (0) and XSB (0), and 28 (1) is a second bit search bus SB (1). ), A search driver provided corresponding to XSB (1), and 28 (n-1) is a search provided corresponding to the nth bit search buses SB (n-1) and XSB (n-1). A search driver 28 (corresponding to search buses SB (2), XSB (2) to SB (n-2), and XSB (n-2) of the third to n-1th bits. 2) to 28 (n-2) are not shown.

  In the match line / sense amplifier unit 21, 15 (0) corresponds to the match line / sense amplifier provided corresponding to the first-line match line ML0, and 15 (1) corresponds to the second-line match line ML1. The provided match line sense amplifier 15 (511) is a match line sense amplifier provided corresponding to the match line ML511 in the 512th row, and is matched to the match lines ML2 to ML510 in the third to 511th rows. Match line / sense amplifiers 15 (2) to 15 (510) provided correspondingly are not shown.

  28 is a circuit diagram for explaining an example of the search operation of the conventional associative memory shown in FIG. 25, and FIGS. 29 and 30 are timing diagrams showing an example of the search operation of the conventional associative memory shown in FIG. FIG. 30 shows the case where the search data DIN matches the storage data at the address 1, and FIG. 30 shows the case where the search data DIN matches the storage data at the address 0.

  In FIG. 28, XSER is a search command signal supplied to the command decoder 23 from the outside, SERZ is a search command decode signal output by the command decoder 23, SBEZ is a search driver activation signal output by the search driver activation signal generation circuit 24, DIN is n-bit search data provided from the outside, D (0) is the first bit data of the search data DIN, D (n−1) is the nth bit data of the search data DIN, and the search data DIN The second bit to n-1 bit data D (1) to D (n-2) are not shown. MS0Z is a search result signal output from the match line sense amplifier 15 (0) in the first row, MS1Z is a search result signal output from the match line sense amplifier 15 (1) in the second row, and EA is the encoder 22. Is a 9-bit address signal output.

  29 and 30, (A) is a clock signal CLK for determining an operation cycle, (B) is a search command signal XSER, (C) is a search command decode signal SERZ, and (D) is a search driver activation signal SBEZ. , (E) are logical values of search buses SB (p), XSB (p) (where p = 0, 1,..., N−1, and so on), (F) is a match line. The logical value of ML0, (G) indicates the search result signal MS0Z, (H) indicates the logical value of the match line ML1, and (I) indicates the search result signal MS1Z.

  That is, in the conventional associative memory shown in FIG. 25, the search command signal XSER = “1”, the search command decode signal SERZ = “0”, and the search driver activation signal SBEZ = “0” before search (during standby). “, Logical values of search buses SB (p) and XSB (p) =“ 0 ”, logical values of match lines ML0 to ML511 =“ 1 ”, and search result signals MS0Z to MS511Z =“ 1 ”.

  When searching, as shown in FIGS. 29 and 30, the search command signal XSER = “0” is set, the search is instructed, and the search drivers 28 (0) to 28 (n−1). Is provided with search data D (0) to D (n-1). As a result, the command decoder 23 sets the search command decode signal SERZ = “1”, and in response to this, the search driver activation signal generation circuit 24 sets the search driver activation signal SBEZ = “1” and the search driver 28 (P) corresponds to the value of the search data D (p), and one of the search buses SB (p) and XSB (p) is set to “1” and the other is set to “0”.

  Here, the search data D (0) to D (n−1) do not match the storage data at the address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)). When the data matches the storage data at address 1 (that is, the storage data of memory cells 3 (1, 0) to 3 (1, n-1)), as shown in FIG. 29, the logical value of match line ML0 = "0" ", And the logical value of the match line ML1 =" 1 "is maintained. As a result, the match line sense amplifier 15 (0) sets the search result signal MS0Z = “0”, and the match line sense amplifier 15 (1) maintains the search result signal MS1Z = “1”. Therefore, in this case, the encoder 22 outputs [000000001] as the address signal EA indicating the first address.

  On the other hand, the search data D (0) to D (n−1) is equal to the storage data at address 0 (that is, the storage data of the memory cells 3 (0, 0) to 3 (0, n−1)). If it does not match the storage data at address 1 (that is, the storage data of memory cells 3 (1, 0) to 3 (1, n-1)), as shown in FIG. 30, match line ML0 Of the match line ML1 is maintained at “0”. As a result, the match line sense amplifier 15 (0) maintains the search result signal MS0Z = "1", and the match line sense amplifier 15 (1) sets the logical value of the search result signal MS1Z = "0". . Therefore, in this case, the encoder 22 outputs [000000000000] as the address signal EA indicating the address 0.

The associative memory has a function of predetermining a priority order for outputting an address signal indicating which address when the search data matches the stored data at a plurality of addresses, and outputting an address signal in accordance with this. A priority match function is provided. For example, in the case of the conventional associative memory shown in FIG. 25, when the search data DIN matches the stored data at a plurality of addresses, the priority order is set such that an address signal indicating the minimum address is output. As shown in FIG. 31, when the search data DIN matches the stored data at address 0 and the stored data at address 2, the encoder 22 detects the address 0 and outputs an address signal indicating the address 0. become.
JP 2000-215678 A JP-A-7-287718 JP-A-3-212896

  In the conventional associative memory shown in FIG. 25, the search operation for the search data DIN is performed for all 512 addresses (addresses 0 to 511), but the address for storing the same data as the search data DIN is The logic value of most of the 512 match lines ML0 to ML511 transitions to “0”, so when returning to the standby state after the search, the 512 match lines ML0 to ML511 Most require charging. Here, if it is possible to reduce the number of match lines that need to be charged when returning to the standby state after searching, the current consumption can be reduced, so the development of an associative memory capable of this is required. Yes.

  In view of the above, the present invention provides an associative memory that can reduce the number of match lines that need to be charged when returning to a standby state after a search, thereby reducing current consumption. Objective.

  The associative memory disclosed in the present application performs a search for a plurality of memory cell arrays that are sequentially searched for search data given from the outside and a memory cell array that stores the same data as the search data. A control unit that controls a search operation so as not to execute a search for a memory cell array that is to be searched after the memory cell array that stores the same data as the data is provided.

  According to the disclosed associative memory, when the control unit executes a search for a memory cell array that stores the same data as the search data, the control unit is set as a search target after the memory cell array that stores the same data as the search data. Since the search operation is controlled so as not to execute the search for the memory cell array in the memory cell array, when returning to the standby state after the search, the memory cell array that stores the same data as the search data after the memory cell array is searched. There is no need to charge the match line provided. Therefore, it is possible to reduce the number of match lines that need to be charged when returning to the standby state after the search, thereby reducing current consumption.

(First embodiment)
FIG. 1 is a circuit diagram showing a part of the first embodiment of the present invention. In FIG. 1, reference numerals 31 and 32 denote memory cell arrays (MCAs) each including 256 memory cell columns in which n memory cells having the configuration shown in FIG. 18 are arranged per row (one word line). These memory cell arrays 31 and 32 are obtained by dividing the memory cell array 16 included in the conventional associative memory shown in FIG. 25 into a portion from addresses 0 to 255 and a portion from addresses 256 to 512. The portion from address 0 to address 255 and the memory cell array 32 are the portion from address 256 to address 512.

  In the first embodiment of the present invention, bit lines BL (0), XBL (0) to BL (n−1), and XBL (n−1) are common to the memory cell arrays 31 and 32 in the first embodiment of the present invention. Although the search bus is provided for the memory cell array 31, search buses SB0 (0), XSB0 (0) to SB0 (n-1), and XSB0 (n-1) are provided. Are provided with search buses SB1 (0), XSB1 (0) to SB1 (n-1), and XSB1 (n-1).

  Reference numeral 33 denotes a word decoder unit that is a group of word decoders that drive the word lines WL0 to WL255 arranged in the memory cell array 31 and the word lines WL256 to WL511 arranged in the memory cell array 32, and 34 denotes the memory cell arrays 31 and 32. A write amplifier unit 35, which is a group of write amplifiers for writing to the memory cells, includes bit lines BL (0), XBL (0) to BL (n-1), XBL (n- 1 is a sense amplifier unit that is a group of sense amplifiers that amplify the read data.

  Reference numeral 36 denotes a search driver section which is a group of search drivers for driving search buses SB0 (0), XSB0 (0) to SB0 (n-1), XSB0 (n-1) arranged in the memory cell array 31. A search driver unit 38, which is a group of search drivers for driving search buses SB1 (0), XSB1 (0) to SB1 (n-1), XSB1 (n-1) arranged in the memory cell array 32, is a memory cell array 31 is a flip-flop that takes in the logical values of the search buses SB0 (0), XSB0 (0) to SB0 (n-1), and XSB0 (n-1) arranged at 31 and transfers them to the search driver of the search driver unit 37. FF) is a flip-flop unit.

  Reference numeral 39 denotes a match line / sense amplifier unit which is a group of match line / sense amplifiers for detecting the levels of the match lines ML0 to ML255 arranged in the memory cell array 31, and 40 denotes match lines ML256 to. This is a match line / sense amplifier unit that is a group of match line / sense amplifiers that detect the level of the ML 511.

  41 receives search result signals MS0Z to MS255Z output from the matchline / sense amplifier unit 39 and search result signals MS256Z to MS511Z output from the matchline / sense amplifier unit 40, and stores the same data as the search data DIN. This is an encoder that generates a 9-bit address signal EA indicating the address that is present. The encoder 41 outputs the address signal EA indicating the minimum address among the plurality of addresses when the search data DIN matches the stored data at the plurality of addresses.

  A command decoder 42 decodes a search command signal XSER given from the outside and outputs a search command decode signal SERZ. 43 receives a search command decode signal SERZ output from the command decoder 42 and searches a search driver of the search driver unit 36. Is a search driver activation signal generation circuit for generating a search driver activation signal SBE0Z to be applied to the flip-flop, and 44 is a flip-flop that takes in the search driver activation signal SBE0Z output from the search driver activation signal generation circuit 43 in synchronization with the clock signal CLK. is there.

  45 receives the search result signals MS0Z to MS255Z output from the match line / sense amplifier unit 39. When the search result signals MS0Z to MS255Z are all "0" (that is, the search data DIN is stored in the memory cell array 31). Or when any of the search result signals MS0Z to MS255Z is “1” (that is, the search data DIN matches any of the data stored in the memory cell array 31). A search result determination circuit (DET) that outputs a search result determination signal DET0Z.

  When the search result signals MS0Z to MS255Z are all “0” (that is, when the search data DIN does not match all the data stored in the memory cell array 31), the search result determination circuit 45 When DET0Z = “1” and any of the search result signals MS0Z to MS255Z is “1” (that is, when the search data DIN matches any of the data stored in the memory cell array 31), the search result The determination signal DET0Z = “0”.

  46 receives the search result determination signal DET0Z output from the search result determination circuit 45 and the search driver activation signal SBE0Z output from the flip-flop 44, and receives the search driver activation signal SBE1Z to be given to the search driver of the search driver unit 37. A search driver activation signal buffer (SBEBUF) to be output. When the search result determination signal DET0Z = “1”, the search driver activation signal buffer 46 outputs the search driver activation signal SBE0Z output from the flip-flop 44 as the search driver activation signal SBE1Z, and the search result determination signal DET0Z. When = "0", the search driver activation signal SBE1Z = "0".

  FIG. 2 is a circuit diagram showing a part of the first embodiment of the present invention in more detail. The memory cell arrays 31, 32, write amplifier section 34, sense amplifier section 35, search driver sections 36, 37, and flip-flop section 38 are shown. Is shown in more detail.

  In the memory cell array 31, 50 (0, 0) is the first bit memory cell in the first row, 50 (0, n-1) is the n bit memory cell in the first row, and 2 in the first row. The memory cells 50 (0, 1) to 50 (0, n-2) of the bit to the (n-1) th bit are not shown. 50 (255, 0) is the first bit memory cell in the 256th row, 50 (255, n−1) is the nth bit memory cell in the 256th row, and the second bit to n− in the second row. The memory cells 50 (255, 1) to 50 (255, n-2) of the first bit are not shown. The memory cells 50 (1, 0) to 50 (1, n−1),..., 50 (254, 0) to 50 (254, n−1) in the second to 255th rows are not shown. ing. FIG. 3 shows the memory cell array 31 in more detail.

  In the memory cell array 32, 50 (256, 0) is the 1st bit memory cell in the 257th row, 50 (256, n-1) is the nth bit memory cell in the 257th row, and 2nd in the 257th row. The memory cells 256 (0, 1) to 256 (0, n-2) of the bit to n-1 bits are not shown. 50 (511, 0) is the first bit memory cell in the 512th row, 50 (511, n−1) is the nth bit memory cell in the 512th row, and the second bit to n− in the 512th row. The memory cells 50 (511, 1) to 50 (511, n-2) of the first bit are not shown. The memory cells 50 (257, 0) to 50 (257, n−1),..., 50 (510, 0) to 50 (510, n−1) in the 258th to 511th rows are also not shown. ing. FIG. 4 shows the memory cell array 32 in more detail.

  WL0 is the first word line, WL255 is the 256th word line, and the second to 255th word lines WL1 to WL254 are not shown. WL256 is the word line of the 257th row, WL511 is the word line of the 512th row, and the word lines WL257 to WL510 of the 258th to 511th rows are not shown.

  ML0 is the first match line, ML255 is the 256th match line, and the second to 255th match lines ML1 to ML254 are not shown. ML256 is a match line of the 257th row, ML511 is a matchline of the 512th row, and matchlines ML257 to ML510 of the 258th to 511th rows are not shown.

  In the write amplifier unit 34, 51 (0) is a write amplifier provided corresponding to the bit line BL (0) of the first bit and XBL (0), and 51 (n−1) is the bit line BL of the nth bit. (N−1) and XBL (n−1) corresponding to the write amplifiers, which are bit lines BL (1) and XBL (1) to BL (n−) of the 2nd to n−1th bits. 2), write amplifiers 51 (1) to 51 (n-2) provided corresponding to XBL (n-2) are not shown.

  In the sense amplifier 35, 52 (0) is a sense amplifier provided corresponding to the bit line BL (0) of the first bit and XBL (0), and 52 (n-1) is a bit line BL of the nth bit. Sense amplifiers provided corresponding to (n-1) and XBL (n-1), which are bit lines BL (1) and XBL (1) to BL (n-th) of the second bit to the (n-1) th bit. 2), sense amplifiers 52 (1) to 52 (n-2) provided corresponding to XBL (n-2) are not shown.

  In the search driver unit 36, 53 (0) is a search driver provided corresponding to the first bit search bus SB0 (0) and XSB0 (0), and 53 (n−1) is the nth bit search bus SB0. (N-1), a search bus provided corresponding to XSB0 (n-1), the second to n-1th bit search buses SB0 (1), XSB0 (1) to SB0 (n- 2) Search drivers 53 (2) to 53 (n-2) provided corresponding to XSB0 (n-2) are not shown.

  The search driver 53 (p) is activated when the search driver activation signal SBE0Z = “1”, and corresponds to the search data D (p) applied to the search buses SB0 (p) and XSB0 (p). When the search driver activation signal SBE0Z = "0" and one of the logic values = "1" and the other logic value = "0", the signal is deactivated and the search buses SB0 (p) and XSB0 (p) Logical value = “0”.

  In the search driver unit 37, 54 (0) is a search driver provided corresponding to the first bit search bus SB1 (0) and XSB1 (0), and 54 (n-1) is the nth bit search bus SB1. (N-1), search buses provided corresponding to XSB1 (n-1), the second to n-1th bit search buses SB1 (1), XSB1 (1) to SB1 (n- 2) Search drivers 54 (2) to 54 (n-2) provided corresponding to XSB1 (n-2) are not shown.

  The search driver 54 (p) is activated when the search driver activation signal SBE1Z = “1”, and the logical values (searches) of the search buses SB0 (p) and XSB0 (p) given through the flip-flop unit 38 Corresponding to the data DIN), one of the search buses SB1 (p) and XSB1 (p) is set to “1”, the other is set to “0”, and the search driver activation signal SBE1Z = “0”. In some cases, it is inactive, and the logical values of the search buses SB1 (p) and XSB1 (p) are set to “0”.

  FIG. 5 is a circuit diagram showing a part of the first embodiment of the present invention in more detail, and shows parts of the word decoder 33 and the match line / sense amplifiers 39 and 40 in more detail. In the word decoder 33, 55 (0) is a word decoder provided corresponding to the first word line WL0, and 55 (255) is a word decoder provided corresponding to the 256th word line WL255. Yes, the word decoders 55 (1) to 55 (254) provided corresponding to the word lines WL1 to WL254 in the second to 255th rows are not shown.

  55 (256) is a word decoder provided corresponding to the word line WL256 of the 257th row, and 55 (511) is a word decoder provided corresponding to the word line WL511 of the 512th row. The word decoders 55 (257) to 55 (510) provided corresponding to the word lines WL257 to WL510 in the first to 511th rows are not shown.

  In the match line / sense amplifier unit 39, 56 (0) corresponds to the match line / sense amplifier provided corresponding to the first line match line ML0, and 56 (255) corresponds to the 256th match line ML255. Match line sense amplifiers provided, and match line sense amplifiers 56 (1) to 56 (254) provided corresponding to the match lines ML1 to ML254 in the second to 255th rows are not shown. ing.

  In the match line / sense amplifier unit 40, 56 (256) is a match line sense amplifier provided corresponding to the match line ML256 in the 257th row, and 56 (511) corresponds to the match line ML511 in the 512th row. Match line sense amplifiers 56 (257) to 56 (510) provided corresponding to the match lines ML 257 to ML 510 in the 258th to 511th rows are not shown. ing.

  6 and 7 are timing diagrams showing an example of a search operation according to the first embodiment of the present invention. FIG. 6 shows a case where the search data DIN does not match all the data stored in the memory cell array 31, and FIG. This is a case where the search data DIN matches any data stored in the memory cell array 31.

  6A and 7B, (A) is a clock signal CLK that determines an operation cycle, (B) is a search command signal XSER, (C) is a search command decode signal SERZ, (D) is a search driver activation signal SBE0Z, ( E) is a logical value of the search buses SB0 (p) and XSB0 (p), (F) is a logical value of the match lines ML0 to ML255, (G) is a search result signal MS0Z to MS255Z, (H) is a search result determination signal. DET0Z, (I) is the search driver activation signal SBE1Z, (J) is the logical value of the search bus SB1 (p), XSB1 (p), (K) is the logical value of the match lines ML256 to ML511, (L) is the search The result determination signals MS256Z to MS511Z are shown.

  That is, in the first embodiment of the present invention, the search command signal XSER = “1”, the search command decode signal SERZ = “0”, and the search driver activation signal SBE0Z = “0” before the search (during standby). , Logical values of search buses SB0 (p) and XSB0 (p) = “0”, logical values of match lines ML0 to ML255 = “1”, search result signals MS0Z to MS255Z = “1”, search result determination signal DET0Z = “0”, search driver activation signal SBE1Z = “0”, search bus SB1 (p), logical value of XSB1 (p) = “0”, logical value of match lines ML256 to ML511 = “1”, search result signal MS256Z to MS511Z = “1”.

Then, when performing a search, as shown in FIG. 6 (B) and FIG. 7 (B), the example, in cycle S _w, is the search command signal XSER = "0", with the search is instructed, Search data D (0) to D (n-1) is given to the search drivers 53 (0) to 53 (n-1). As a result, as shown in FIGS. 6C and 7C, the command decoder 42 sets the search command decode signal SERZ = “1”, and in response to this, the search driver activation signal generation circuit 43 As shown in FIGS. 6D and 7D, the search driver activation signal SBE0Z = “1” and the search driver 53 (p) corresponds to the value of the search data D (p). As shown in FIGS. 6E and 7E, one of the search buses SB0 (p) and XSB0 (p) is set to “1” and the other is set to “0”.

  If the search data D (0) to D (n−1) does not match all the data stored in the memory cell array 31, the match lines ML0 to ML255 are shown in FIG. 6 (F). The logical value of “= 0”. As a result, the match line sense amplifiers 56 (0) to 56 (255) set the search result signals MS0Z to MS255Z = “0” as shown in FIG. As shown in FIG. 6H, the circuit 45 sets the search result determination signal DET0Z = “1”.

Therefore, as shown in FIG. 6 (I), the search driver activation signal generation circuit 43 sets the search driver activation signal SBE1Z = “1” and activates the search driver 54 (p) in the cycle Sw _{+ 1} . To do. Further, the logical values of the search buses SB0 (p) and XSB0 (p) are supplied to the search driver 54 (p) via the flip-flop 55 (p). As a result, as shown in FIG. 6 (J), the search driver 54 (p) corresponds to the value of the search data D (p), and the logical value of one of the search buses SB1 (p) and XSB1 (p) = “1” and the other logical value = “0”.

  When the search data D (0) to D (n−1) matches any of the data stored in the memory cell array 32, the search is performed among the match lines ML255 to ML511 as shown in FIG. Since the logical value of the match line of the address storing the same data as the data D (0) to D (n−1) is maintained at “1”, the match line sense amplifiers 56 (256) to 56 (511) As shown in FIG. 6L, among the search result signals MS256Z to MS511Z, the search result signal of the address storing the same data as the search data D (0) to D (n-1) is maintained at "1". To do.

  On the other hand, when the search data D (0) to D (n−1) match any of the data stored in the memory cell array 31, the match lines ML0 to ML255 are displayed as shown in FIG. Among them, the logical value of the match line of the address storing the same data as the search data D (0) to D (n−1) is maintained at “1”. As a result, as shown in FIG. 7G, the match line sense amplifiers 56 (0) to 56 (255) search data D (0) to D (n−1) among the search result signals MS0Z to MS255Z. The search result signal of the address that stores the same data as (1) is maintained at “1”, and the search result determination circuit 45 maintains the search result determination signal DET0Z = “0” as shown in FIG.

Therefore, in this case, the search driver activation signal generation circuit 43 maintains the search driver activation signal SBE1Z = “0” even in the cycle Sw _{+ 1} as shown in FIG. The driver 54 (p) is not activated and the logical values of the search buses SB1 (p) and XSB1 (p) are maintained at “0” as shown in FIG. 7 (J). As shown in FIG. 7, the logical values of the match lines ML256 to ML511 are maintained at “1”, and the logical values of the search result signals MS256Z to MS511Z are maintained at “1” as shown in FIG.

  Here, the encoder 41 also has the case shown in FIG. 6 (when all logical values of the search result signals MS0Z to MS255Z = “0” and any logical value of the search result signals MS256Z to MS511Z = “1”). In the case shown in FIG. 7 (when any one of the search result signals MS0Z to MS255Z is “1” and all the logical values of the search result signals MS256Z to MS511Z are “1”), the search result signals MS0Z to MS511Z are input. Then, an address signal EA indicating an address for storing the same data as the search data DIN is output. In the first embodiment of the present invention, the flip-flop 44, the search result determination circuit 45, and the search bus activation signal buffer 46 constitute a control unit that controls the search operation for the memory cell array 32. .

  As described above, according to the first embodiment of the present invention, when the search command signal XSER is set to “0” and the search data DIN is given, the search is executed on the memory cell array 31 and the search data If DIN matches any of the data stored in memory cell array 31, the search for memory cell array 32 is not executed, and search data DIN does not match all of the data stored in memory cell array 31. Only in this case, the search operation for the memory cell array 32 is executed.

  As a result, if the search data DIN matches any of the data stored in the memory cell array 31 and the search for the memory cell array 32 is not executed, the memory cell array 32 is returned to the standby state. There is no need to charge the match lines ML256 to ML511 provided in FIG. Therefore, it is possible to reduce the number of match lines that need to be charged when returning to the standby state after the search, thereby reducing current consumption.

(Second Embodiment)
FIG. 8 is a circuit diagram showing a part of the second embodiment of the present invention. In FIG. 8, reference numerals 61 to 64 denote memory cell arrays in which 128 memory cell columns in which n memory cells having the configuration shown in FIG. 18 are arranged per row (one word line) are arranged. These memory cell arrays 61 to 64 are the same as the memory cell array 16 included in the conventional associative memory shown in FIG. 25, the part from address 0 to 127, the part from address 128 to 255, and the part from address 256 to 383. , The memory cell array 61 is a portion from addresses 0 to 127, the memory cell array 62 is a portion from addresses 128 to 255, and the memory cell array 63 is addresses 256 to 383. The memory cell array 64 is a portion from addresses 384 to 511.

  In the second embodiment of the present invention, as shown in FIGS. 9 and 10, the bit lines are bit lines BL (0), XBL (0) to BL (n−1) with respect to the memory cell arrays 61 to 64. , XBL (n−1) are provided in common, but the search bus for the memory cell array 61 is, as shown in FIG. 9, search buses SB0 (0), XSB0 (0) to SB0 (n−1). ), XSB0 (n-1) are provided, and for the memory cell array 62, as shown in FIG. 9, search buses SB1 (0), XSB1 (0) to SB1 (n-1), XSB1 (n -1) is provided, and search buses SB2 (0), XSB2 (0) to SB2 (n-1), and XSB2 (n-1) are provided for the memory cell array 63 as shown in FIG. , For memory cell array 64 , As also shown in FIG. 10, search buses SB3 (0), XSB3 (0) ~SB3 (n-1), is provided XSB3 (n-1).

  65, word lines WL0 to WL127 arranged in the memory cell array 61, word lines WL128 to WL255 arranged in the memory cell array 62, word lines WL256 to WL383 arranged in the memory cell array 63, and the memory cell array 64. A word decoder unit that is a group of word decoders that drive the word lines WL384 to WL511, 66 is a write amplifier unit that is a group of write amplifiers that write data to the memory cells of the memory cell arrays 61 to 64, and 67 is a bit line BL ( 0), XBL (0) to BL (n-1), and a sense amplifier unit that is a group of sense amplifiers that amplify data read to XBL (n-1).

  68 denotes a search driver unit which is a group of search drivers for driving search buses SB0 (0), XSB0 (0) to SB0 (n-1), XSB0 (n-1) arranged in the memory cell array 61; A search driver section, which is a group of search drivers for driving search buses SB1 (0), XSB1 (0) to SB1 (n-1), XSB1 (n-1) arranged in the memory cell array 62, and 70 is a memory cell array 63, a search driver unit 71, which is a group of search drivers for driving search buses SB2 (0), XSB2 (0) to SB2 (n-1), XSB2 (n-1) arranged in 63, Search drivers for driving the arranged search buses SB3 (0), XSB3 (0) to SB3 (n-1), XSB3 (n-1) It is a search driver unit is a group of server.

  72 takes in the logical values of the search buses SB0 (0), XSB0 (0) to SB0 (n-1), XSB0 (n-1) arranged in the memory cell array 61 and transfers them to the search driver of the search driver unit 69. The flip-flop unit 73, which is a group of flip-flops, performs the logical values of the search buses SB 1 (0), XSB 1 (0) to SB 1 (n−1), XSB 1 (n−1) arranged in the memory cell array 62. Flip-flop units 74, which are groups of flip-flops that take in and transfer to the search driver of the search driver unit 70, are search buses SB2 (0), XSB2 (0) to SB2 (n-1) arranged in the memory cell array 63. , XSB2 (n-1) which takes in the logical value and transfers it to the search driver of the search driver unit 71 Tsu is a flip-flop unit is a group of flops.

  Reference numeral 75 denotes a match line / sense amplifier unit which is a group of match line / sense amplifiers for detecting the levels of the match lines ML0 to ML127 arranged in the memory cell array 61. Reference numeral 76 denotes match lines ML128 to 128 arranged in the memory cell array 62. A match line sense amplifier unit 77, which is a group of match line sense amplifiers for detecting the level of ML 255, is a group of match line sense amplifiers for detecting the levels of match lines ML 256 to ML 383 arranged in the memory cell array 63. A certain match line / sense amplifier section 78 is a match line / sense amplifier section which is a group of match line / sense amplifiers for detecting the levels of the match lines ML384 to ML511 arranged in the memory cell array 64.

  Reference numeral 79 denotes search result signals MS0Z to MS127Z output from the match line sense amplifier unit 75, search result signals MS128Z to MS255Z output from the match line sense amplifier unit 76, and search results output from the match line sense amplifier unit 77. The signals MS256Z to MS383Z and the search result signals MS384Z to MS511Z output from the match line sense amplifier unit 78 are input, and a 9-bit address signal EA indicating the address storing the same data as the search data DIN is generated. It is an encoder. The encoder 79 outputs the address signal EA indicating the minimum address among the plurality of addresses when the search data DIN matches the stored data at the plurality of addresses.

  A command decoder 80 decodes a search command signal XSER given from the outside and outputs a search command decode signal SERZ. 81 receives a search command decode signal SERZ output from the command decoder 80, and a search driver of the search driver unit 68. Is a search driver activation signal generating circuit for generating a search driver activation signal SBE0Z to be applied to the flip-flop, and 82 is a flip-flop that takes in the search driver activation signal SBE0Z output from the search driver activation signal generation circuit 81 in synchronization with the clock signal CLK. is there.

  83, search result signals MS0Z to MS127Z output from the match line / sense amplifier unit 75 are input. When the search result signals MS0Z to MS127Z are all “0” (that is, the search data DIN is stored in the memory cell array 61). Or the search result signals MS0Z to MS127Z are “1” (that is, the search data DIN matches any of the data stored in the memory cell array 61). And a search result determination circuit that outputs a search result determination signal DET0Z.

  When the search result signals MS0Z to MS127Z are all “0” (that is, when the search data DIN does not match all the data stored in the memory cell array 61), the search result determination circuit 83 When DET0Z = “1” and any of the search result signals MS0Z to MS127Z is “1” (that is, the search data DIN matches any of the data stored in the memory cell array 61), the search result The determination signal DET0Z = “0”.

  84 is a flip-flop that takes in the search result determination signal DET0Z output from the search result determination circuit 83 in synchronization with the clock signal CLK, and 85 is a search driver activation signal SBE0Z output from the flip-flop 82 and a search result output from the flip-flop 84. This is a search driver activation signal buffer that receives the determination signal DET0Za and outputs a search driver activation signal SBE1Z to be supplied to the search driver of the search driver unit 69.

  The search driver activation signal buffer 85 outputs the search driver activation signal SBE0Z given from the flip-flop 82 as the search driver activation signal SBE1Z when the logical value of the search result determination signal DET0Za is “1”. When the logical value of the result determination signal DET0Za = “0”, the logical value of the search driver activation signal SBE1Z = “0”.

  86 is a flip-flop that fetches the search driver activation signal SBE1Z output from the search driver activation signal buffer 85 in synchronization with the clock, and 87 is a search result signal MS128Z to MS255Z output from the match line sense amplifier unit 76. The search result signals MS128Z to MS255Z are all “0” (that is, the search data DIN does not match all the data stored in the memory cell array 62), or any of the search result signals MS128Z to MS255Z Is a search result determination circuit that determines whether the search data DIN matches any of the data stored in the memory cell array 62 and outputs a search result determination signal DET1Z. is there.

  When the search result signals MS128Z to MS255Z are all “0” (that is, when the search data DIN does not match all the data stored in the memory cell array 62), the search result determination circuit 87 When DET1Z = “1” and any of the search result signals MS128Z to MS255Z is “1” (that is, when the search data DIN matches any of the data stored in the memory cell array 62), the search result The determination signal DET1Z = “0”.

  Reference numeral 88 denotes a flip-flop that takes in the search result determination signal DET1Z output from the search result determination circuit 87 in synchronization with the clock signal CLK. Reference numeral 89 denotes a search driver activation signal SBE1Z output from the flip-flop 86 and a search result output from the flip-flop 88. This is a search driver activation signal buffer that receives the determination signal DET1Za and outputs a search driver activation signal SBE2Z to be supplied to the search driver of the search driver unit 70.

  The search driver activation signal buffer 89 outputs the search driver activation signal SBE1Z given from the flip-flop 86 as the search driver activation signal SBE2Z when the logical value of the search result determination signal DET1Za = “1”. When the logical value of the result determination signal DET1Za = “0”, the logical value of the search driver activation signal SBE2Z = “0”.

  90 is a flip-flop that takes in the search driver activation signal SBE2Z output from the search driver activation signal buffer 89 in synchronization with the clock, 91 is an input of the search result signals MS256Z to MS383Z output from the match line sense amplifier unit 77, Whether the search result signals MS256Z to MS383Z are all “0” (that is, the search data DIN does not match all the data stored in the memory cell array 63), or any of the search result signals MS256Z to MS383Z Is a search result determination circuit that determines whether the search data DIN matches any of the data stored in the memory cell array 63 and outputs a search result determination signal DET2Z. is there.

  When the search result signals MS256Z to MS383Z are all “0” (that is, when the search data DIN does not match all the data stored in the memory cell array 63), the search result determination circuit 91 When DET2Z = “1” and any of the search result signals MS256Z to MS383Z is “1” (that is, when the search data DIN matches any of the data stored in the memory cell array 63), the search result The determination signal DET2Z = “0”.

  92 is a flip-flop that takes in the search result determination signal DET2Z output from the search result determination circuit 91 in synchronization with the clock signal CLK, and 93 is a search driver activation signal SBE2Z output from the flip-flop 90 and a search result output from the flip-flop 92. This is a search driver activation signal buffer that receives the determination signal DET2Za and outputs a search driver activation signal SBE3Z to be supplied to the search driver of the search driver unit 71.

  When the logical value of the search result determination signal DET2Za is “1”, the search driver activation signal buffer 93 outputs the search driver activation signal SBE2Z given from the flip-flop 90 as the search driver activation signal SBE3Z, and the search result When the logical value of the determination signal DET2Za = “0”, the logical value of the search driver activation signal SBE3Z = “0”.

  FIG. 9 is a circuit diagram showing a part of the second embodiment of the present invention in more detail. Memory cell arrays 61 and 62, a write amplifier section 66, a sense amplifier section 67, search driver sections 68 and 69, and a flip-flop section 72 Is shown in more detail.

  In the memory cell array 61, 96 (0, 0) is the first bit memory cell in the first row, 96 (0, n-1) is the n bit memory cell in the first row, and 2 in the first row. The memory cells 96 (0, 1) to 96 (0, n-2) of the bit to n-1 bits are not shown. 96 (127, 0) is the first bit memory cell in the 128th row, 96 (127, n-1) is the nth bit memory cell in the 128th row, and the second bit to n− in the 128th row. The memory cells 96 (127, 1) to 96 (127, n-2) of the first bit are not shown. The memory cells 96 (1, 0) to 96 (1, n-2),..., 96 (126, 0) to 96 (126, n-2) in the second to 127th rows are not shown. ing.

  In the memory cell array 62, 96 (128, 0) is the 1st bit memory cell in the 129th row, and 96 (128, n−1) is the nth bit memory cell in the 129th row, and 2 in the 129th row. The memory cells 96 (128, 1) to 96 (128, n-2) of the bit to n-1 bit are not shown. 96 (255, 0) is the first bit memory cell in the 256th row, and 96 (255, n−1) is the nth bit memory cell in the 256th row, and the second bit to n− in the 256th row. The first bit memory cells 96 (255, 1) to 96 (255, n-2) are not shown. The memory cells 96 (129, 0) to 96 (129, n-2),..., 96 (254, 0) to 96 (254, n-2) in the 130th to 255th rows are also not shown. ing.

  WL0 is the first word line, WL127 is the 128th word line, and the second to 127th word lines WL1 to WL126 are not shown. WL128 is the word line of the 129th row, WL255 is the wordline of the 256th row, and the word lines WL129 to WL254 of the 130th to 255th rows are not shown.

  ML0 is the first match line, ML127 is the 128th match line, and the second to 127th match lines ML1 to ML126 are not shown. ML128 is a match line of the 129th row, ML255 is a matchline of the 256th row, and matchlines ML129 to ML254 of the 130th to 255th rows are not shown.

  In the write amplifier unit 66, 97 (0) is a write amplifier provided corresponding to the bit line BL (0) of the first bit and XBL (0), and 97 (n−1) is the bit line BL of the nth bit. (N−1) and XBL (n−1) corresponding to the write amplifiers, which are bit lines BL (1) and XBL (1) to BL (n−) of the 2nd to n−1th bits. 2), write amplifiers 97 (1) to 97 (n-2) provided corresponding to XBL (n-2) are not shown.

  In the sense amplifier section 67, 98 (0) is a sense amplifier provided corresponding to the bit line BL (0) of the first bit and XBL (0), and 98 (n-1) is a bit line BL of the nth bit. Sense amplifiers provided corresponding to (n-1) and XBL (n-1), which are bit lines BL (1) and XBL (1) to BL (n-th) of the second bit to the (n-1) th bit. 2), sense amplifiers 98 (1) to 98 (n-2) provided corresponding to XBL (n-2) are not shown.

  In the search driver unit 68, 99 (0) is a search driver provided corresponding to the first bit search bus SB0 (0) and XSB0 (0), and 99 (n-1) is the nth bit search bus SB0. (N-1), a search bus provided corresponding to XSB0 (n-1), the second to n-1th bit search buses SB0 (1), XSB0 (1) to SB0 (n- 2) Search drivers 99 (1) to 99 (n-2) provided corresponding to XSB0 (n-2) are not shown.

  The search driver 99 (p) is activated when the search driver activation signal SBE0Z = "1", and corresponds to the search data D (p) given from the outside, and the search buses SB0 (p), XSB0 (p ) Is inactive when the search driver activation signal SBE0Z = “0”, the search bus SB0 (p), XSB0 (p) The logical value of “= 0”.

  In the search driver unit 69, 100 (0) is a search driver provided corresponding to the first bit search bus SB1 (0) and XSB1 (0), and 100 (n-1) is the nth bit search bus SB1. (N-1), a search driver provided corresponding to XSB1 (n-1), the search buses SB1 (1), XSB1 (1) to SB1 (n- 2) Search drivers 100 (1) to 100 (n-2) provided corresponding to XSB1 (n-2) are not shown.

  The search driver 100 (p) is activated when the search driver activation signal SBE1Z = “1”, and the search data D () provided via the search buses SB1 (p), XSB1 (p) and the flip-flop unit 72. Corresponding to p), when one of the search buses SB1 (p) and XSB1 (p) is set to “1” and the other is set to “0”, the search driver activation signal SBE1Z = “0”. Is inactive, and the logical values of the search buses SB1 (p) and XSB1 (p) = “0”.

  In the flip-flop unit 72, 101 (0) is a flip-flop provided corresponding to the search buses SB0 (0) and XSB0 (0), and the search buses SB0 (0) and XSB0 ( 0) is fetched and transferred to the search driver 100 (0). Reference numeral 101 (n-1) denotes a flip-flop provided corresponding to the search buses SB0 (n-1) and XSB0 (n-1), and the search buses SB0 (n-1), The logical value of XSB0 (n-1) is fetched and transferred to the search driver 100 (n-1). Flip-flops 101 (1) to 101 (n-2) provided corresponding to the search buses SB0 (1), XSB0 (1) to SB0 (n-2), and XSB0 (n-2) are not shown. is doing.

  FIG. 10 is a circuit diagram showing a part of the second embodiment of the present invention in more detail, and shows memory cell arrays 63 and 64, search driver units 70 and 71, and flip-flop units 73 and 74 in more detail.

  In the memory cell array 63, 96 (256, 0) is a 1st bit memory cell in the 257th row, and 96 (256, n-1) is an nth bit memory cell in the 257th row, and 2nd in the 257th row. The memory cells 96 (256, 1) to 96 (256, n-2) of the bit to the (n-1) th bit are not shown. 96 (383, 0) is the first bit memory cell in the 384th row, 96 (383, n-1) is the nth bit memory cell in the 384th row, and the second bit to n− in the 384th row. The first bit memory cells 96 (383, 1) to 96 (383, n-2) are not shown. The memory cells 96 (257, 0) to 96 (257, n-2),..., 96 (382, 0) to 96 (382, n-2) in the 258th to 383th rows are also not shown. ing.

  In the memory cell array 64, 96 (384, 0) is the 1st bit memory cell in the 385th row, and 96 (384, n-1) is the nth bit memory cell in the 385th row. The memory cells 96 (384, 1) to 96 (384, n-2) of the bit to n-1 bit are not shown. 96 (511, 0) is the first bit memory cell in the 512th row, and 96 (511, n-1) is the nth bit memory cell in the 512th row. The memory cells 96 (511, 1) to 96 (511, n-2) of the first bit are not shown. The memory cells 96 (385, 0) to 96 (385, n-2),..., 96 (510, 0) to 96 (510, n-2) in the 386th to 511th rows are also not shown. ing.

  WL256 is the word line of the 257th row, WL383 is the word line of the 384th row, and the word lines WL257 to WL382 of the 258th to 383th rows are not shown. WL384 is the word line of the 385th row, WL511 is the word line of the 512th row, and the word lines WL385 to WL510 of the 386th to 511th rows are not shown.

  ML256 is a match line of the 257th row, ML383 is a match line of the 384th row, and match lines ML257 to ML382 of the 258th to 383th rows are not shown. ML384 is a match line of the 385th row, ML511 is a match line of the 512th row, and match lines ML385 to ML510 of the 386th to 511th rows are not shown.

  In the search driver unit 70, 102 (0) is a search driver provided corresponding to the first bit search bus SB2 (0) and XSB2 (0), and 102 (n-1) is the nth bit search bus SB2. (N-1), a search driver provided corresponding to XSB2 (n-1), the search buses SB2 (1), XSB2 (1) to SB2 (n- 2) Search drivers 102 (2) to 102 (n-2) provided corresponding to XSB2 (n-2) are not shown.

  The search driver 102 (p) is activated when the search driver activation signal SBE2Z = “1”, and the search data D () provided via the search buses SB1 (p) and XSB1 (p) and the flip-flop unit 73. Corresponding to p), when one of the search buses SB2 (p) and XSB2 (p) is set to “1” and the other is set to “0”, the search driver activation signal SBE2Z = “0”. Are inactive, and the logical values of the search buses SB2 (p) and XSB2 (p) = “0”.

  In the search driver unit 71, 103 (0) is a search driver provided corresponding to the first bit search bus SB3 (0) and XSB3 (0), and 103 (n-1) is the nth bit search bus SB3. (N-1), a search driver provided corresponding to XSB3 (n-1), the search buses SB3 (1), XSB3 (1) to SB3 (n- 2) Search drivers 103 (2) to 103 (n-2) provided corresponding to XSB3 (n-2) are not shown.

  The search driver 103 (p) is activated when the search driver activation signal SBE3Z = “1”, and the search data D () provided via the search buses SB2 (p), XSB2 (p) and the flip-flop unit 74. Corresponding to p), when one of the search buses SB3 (p) and XSB3 (p) is “1”, the other is logic “0”, and the search driver activation signal SBE3Z is “0” Are inactive and the logical values of the search buses SB3 (p) and XSB3 (p) are set to “0”.

  In the flip-flop unit 73, 104 (0) is a flip-flop provided corresponding to the search buses SB1 (0) and XSB1 (0), and in synchronization with the clock signal CLK, the search buses SB1 (0) and XSB1 ( 0) is fetched and transferred to the search driver 102 (0). Reference numeral 104 (n-1) denotes a flip-flop provided corresponding to the search buses SB1 (n-1) and XSB1 (n-1), and the search buses SB1 (n-1), The logical value of XSB1 (n-1) is fetched and transferred to the search driver 102 (n-1). Flip-flops 104 (1) to 104 (n-2) provided corresponding to the search buses SB1 (1), XSB1 (1) to SB1 (n-2), and XSB1 (n-2) are not shown. is doing.

  In the flip-flop unit 74, 105 (0) is a flip-flop provided corresponding to the search buses SB2 (0) and XSB2 (0). The search buses SB2 (0) and XSB2 ( 0) is fetched and transferred to the search driver 103 (0). Reference numeral 105 (n-1) denotes a flip-flop provided corresponding to the search buses SB2 (n-1) and XSB2 (n-1), and the search buses SB2 (n-1), The logical value of XSB2 (n-1) is fetched and transferred to the search driver 103 (n-1). Flip-flops 105 (1) to 105 (n-2) provided corresponding to the search buses SB2 (1), XSB2 (1) to SB2 (n-2), and XSB2 (n-2) are not shown. is doing.

  FIG. 11 is a circuit diagram showing a part of the second embodiment of the present invention in more detail, and shows parts of the memory cell arrays 61 to 64, the word decoder unit 65, and the match line / sense amplifier units 75 to 78 in more detail. .

  In the word decoder unit 65, 106 (0) is a word decoder provided corresponding to the first word line WL0, and 106 (127) is a word decoder provided corresponding to the 128th word line WL127. Yes, the word decoders 106 (1) to 106 (126) provided corresponding to the word lines WL1 to WL126 in the second to 127th rows are not shown. 106 (128) is a word decoder provided corresponding to the word line WL128 of the 129th row, and 106 (255) is a word decoder provided corresponding to the word line WL255 of the 256th row. The word decoders 106 (129) to 106 (254) provided corresponding to the word lines WL129 to WL254 in the 255th row are not shown.

  106 (256) is a word decoder provided corresponding to the word line WL256 of the 257th row, and 106 (383) is a word decoder provided corresponding to the word line WL383 of the 384th row. The word decoders 106 (257) to 106 (382) provided corresponding to the word lines WL257 to WL382 in the 383th row are not shown. 106 (384) is a word decoder provided corresponding to the word line WL384 in the 385th row, and 106 (511) is a word decoder provided corresponding to the word line WL511 in the 512th row. The word decoders 106 (385) to 106 (510) provided corresponding to the word lines WL385 to WL510 in the 511th row are not shown.

  In the match line / sense amplifier unit 75, 107 (0) corresponds to the match line / sense amplifier provided corresponding to the first line match line ML0, and 107 (127) corresponds to the 128th line match line ML127. Match line sense amplifiers 107 (1) to 107 (126) provided corresponding to the match lines ML1 to ML126 of the second to 127th rows are not shown. ing.

  In the match line / sense amplifier section 76, 107 (128) corresponds to the match line ML 128 provided corresponding to the 129th match line ML128, and 107 (255) corresponds to the 256th match line ML255. Match line sense amplifiers provided, and match line sense amplifiers 107 (129) to 107 (254) provided corresponding to the match lines ML129 to ML254 in the 130th to 255th rows are not shown. ing.

  In the match line / sense amplifier section 77, 107 (256) is a match line sense amplifier provided corresponding to the match line ML256 in the 257th row, and 107 (383) corresponds to the match line ML383 in the 384th row. The match line sense amplifiers 107 (257) to 107 (382) provided corresponding to the match lines ML257 to ML382 in the 258th to 383th rows are not shown. ing.

  In the match line / sense amplifier section 78, 107 (384) is a match line sense amplifier provided corresponding to the match line ML384 in the 385th row, and 107 (511) corresponds to the match line ML511 in the 512th row. Match line sense amplifiers provided, and match line sense amplifiers 107 (385) to 107 (510) provided corresponding to the match lines ML385 to ML510 in the 386th to 511th rows are not shown. ing.

  FIG. 12 is a timing chart showing an example of a search operation according to the second embodiment of the present invention. Search data DIN = D (0) to D (n−1) matches any of the data stored in the memory cell array 61. This is an example.

  12, (A) is a clock signal CLK that determines an operation cycle, (B) is a search command signal XSER, (C) is a search command decode signal SERZ, (D) is a search driver activation signal SBE0Z, (E) is Search buses SB0 (p) and XSB0 (p) are logical values, (F) is a logical value of match lines ML0 to ML127, (G) is a search result signal MS0Z to MS127Z, (H) is a search result determination signal DET0Z, ( I) is a search driver activation signal SBE1Z, (J) is a logical value of search bus SB1 (p), XSB1 (p), (K) is a logical value of match lines ML128 to ML255, and (L) is a search result signal MS128Z. MS255Z, (M) is search result determination signal DET1Z, (N) is search driver activation signal SBE2Z, (O) is search bus B2 (p) and XSB2 (p) are logical values, (P) is a logical value of the match lines ML256 to ML383, (Q) is a search result signal MS256Z to MS383Z, (R) is a search result determination signal DET2Z, (S) Is a search driver activation signal SBE3Z, (T) is a logical value of the search buses SB3 (p) and XSB3 (p), (U) is a logical value of the match lines ML384 to ML511, and (V) is a search result signal MS384Z to MS511Z. Is shown.

  That is, in the second embodiment of the present invention, the search command signal XSER = “1”, the search command decode signal SERZ = “0”, and the search driver activation signal SBE0Z = “0” before search (during standby). , Search buses SB0 (p), XSB0 (p) to SB3 (p), XSB3 (p) logical value = “0”, match lines ML0 to ML511 logical value = “1”, search result signals MS0Z to MS511Z = “1”, search result determination signals DET0Z to DET2Z = “0”, and search driver activation signals SBE1Z to SBE3Z = “0”.

Then, when performing a search, for example, in a cycle S _w, search command signal XSER = set to "0", the search data together with the search is instructed, the search driver 99 (0) ~99 (n- 1) D (0) to D (n-1) are given. As a result, the command decoder 80 sets the search command decode signal SERZ = “1”, and in response to this, the search driver activation signal generation circuit 81 sets the search driver activation signal SBE0Z = “1” and the search The driver 99 (p) sets one logical value = “1” of the search buses SB0 (p) and XSB0 (p) corresponding to the value of the search data D (p) and the other logical value = “0”. .

Here, when the search data D (0) to D (n−1) matches any of the data stored in the memory cell array 61, the search data D (0) to D (n) out of the match lines ML0 to ML127. The logical value of the match line of the address storing the same data as -1) is maintained at “1”. As a result, the match line sense amplifiers 107 (0) to 107 (127) search for addresses that store the same data as the search data D (0) to D (n-1) among the search result signals MS0Z to MS127Z. The result signal = "1" is maintained, and the search result determination circuit 83 maintains the search result determination signal DET0Z = "0". Therefore, the search driver activation signal buffer 85 maintains the search driver activation signal SBE1Z = “0” in the cycles S _w and S _{w + 1} and sets the search drivers 100 (0) to 100 (n−1). Does not activate.

As a result, in the cycles S _w and S _{w + 1} , the logic values of the match lines ML128 to ML255 are maintained at “1”, so that the matchline sense amplifiers 107 (128) to 107 (255) The search result signals MS128Z to MS255Z = "1" are maintained, and the search result determination circuit 87 maintains the search result determination signal DET1Z = "0". Therefore, the search driver activation signal buffer 89 maintains the search driver activation signal SBE2Z = “0” in the cycles S _{w to} S _{w + 2} and sets the search drivers 102 (0) to 102 (n−1). Does not activate.

As a result, in the cycles S _{w to} S _{w + 2} , the logic values of the match lines ML 256 to ML 383 = “1” are maintained, so that the match line sense amplifiers 107 (256) to 107 (383) The search result signals MS256Z to MS383Z = "1" are maintained, and the search result determination circuit 91 maintains the search result determination signal DET2Z = "0". Therefore, the search driver activation signal buffer 93 maintains the search driver activation signal SBE3Z = “0” in the cycles S _{w to} S _{w + 3} and sets the search drivers 103 (0) to 103 (n−1). Does not activate.

  On the other hand, although illustration is omitted, the search data D (0) to D (n−1) does not match all of the data stored in the memory cell array 61 and is stored in the memory cell array 62. If it matches, the logical value of the match lines ML0 to ML127 becomes “0”. As a result, the match line sense amplifiers 107 (0) to 107 (127) set the search result signals MS0Z to MS127Z = “0”, and the search result determination circuit 83 sets the search result determination signal DET0Z = “1”.

Therefore, the search driver activation signal buffer 85 sets the search driver activation signal SBE1Z = “1” and activates the search driver 99 (p) in the cycle Sw _{+ 1} . Further, the logical values of the search buses SB1 (p) and XSB1 (p) are supplied to the search driver 100 (p) via the flip-flop 101 (p). As a result, the search driver 100 (p) corresponds to the value of the search data D (p), and one of the search buses SB1 (p) and XSB1 (p) is “1” and the other is “=”. 0 ”.

Here, when the search data D (0) to D (n−1) matches any of the data stored in the memory cell array 62, the search data D (0) to D (n) out of the match lines ML128 to ML255. The logical value of the match line of the address storing the same data as -1) is maintained at “1”. As a result, the match line sense amplifiers 107 (128) to 107 (255) search for addresses that store the same data as the search data D (0) to D (n-1) among the search result signals MS128Z to MS255Z. The result signal = "1" is maintained, and the search result determination circuit 87 maintains the search result determination signal DET1Z = "0". Therefore, the search driver activation signal buffer 89 maintains the search driver activation signal SBE2Z = “0” in the cycles S _{w to} S _{w + 2} and sets the search drivers 102 (0) to 102 (n−1). Does not activate.

As a result, in the cycles S _{w to} S _{w + 2} , the logical values = “1” of the match lines ML 256 to ML 383 are maintained. As a result, the match line sense amplifiers 107 (256) to 107 (383) maintain the search result signals MS256Z to MS383Z = “1”, and the search result determination circuit 87 sets the search result determination signal DET2Z = “0”. maintain. Therefore, the search driver activation signal buffer 93 maintains the search driver activation signal SBE3Z = “0” in the cycles S _{w to} S _{w + 3} and sets the search drivers 103 (0) to 103 (n−1). Does not activate.

  Although not shown, the search data D (0) to D (n−1) does not match all the data stored in the memory cell arrays 61 and 62 and matches the data stored in the memory cell array 63. In this case, the logical values of the match lines ML0 to ML127 are “0”. As a result, the match line sense amplifiers 107 (0) to 107 (127) have search result signals MS0Z to MS127Z = “0”, and the search result determination circuit 83 sets the search result determination signal DET0Z = “1”.

Therefore, search driver activation signal buffer 85 activates search driver 100 (p) by setting search driver activation signal SBE1Z = “1” in cycle Sw _{+ 1} . Further, the logical values of the search buses SB0 (p) and XSB0 (p) are supplied to the search driver 100 (p) via the flip-flop 101 (p). As a result, the search driver 100 (p) corresponds to the value of the search data D (p), and one of the search buses SB1 (p) and XSB1 (p) is “1” and the other is “=”. 0 ”.

  However, in this case, since the logical values of the match lines ML128 to ML255 are “0”, the match line sense amplifiers 107 (128) to 107 (255) set the search result signals MS128Z to MS255Z = “0”. The search result determination circuit 87 sets the search result determination signal DET1Z = “1”.

Therefore, the search driver activation signal buffer 89 sets the search driver activation signal SBE2Z = “1” and activates the search driver 102 (p) in the cycle Sw _{+ 2} . Further, the logical values of the search buses SB1 (p) and XSB1 (p) are supplied to the search driver 102 (p) via the flip-flop 104 (p). As a result, the search driver 102 (p) corresponds to the value of the search data D (p), and one of the search buses SB2 (p) and XSB2 (p) is “1” and the other is “=”. 0 ”.

Here, when the search data D (0) to D (n−1) matches any of the data stored in the memory cell array 63, the search data D (0) to D (n) out of the match lines ML256 to ML383. The logical value of the match line of the address storing the same data as -1) is maintained at “1”. As a result, the match line sense amplifiers 107 (256) to 107 (383) search for addresses that store the same data as the search data D (0) to D (n-1) among the search result signals MS256Z to MS383Z. The result signal = "1" is maintained, and the search result determination circuit 91 maintains the search result determination signal DET2Z = "0". Therefore, the search driver activation signal buffer 93 maintains the search driver activation signal SBE3Z = “0” in the cycles S _{w to} S _{w + 3} and sets the search drivers 103 (0) to 103 (n−1). Does not activate.

  Although not shown, the search data D (0) to D (n−1) does not match all the data stored in the memory cell arrays 61 to 63 and matches the data stored in the memory cell array 64. To do so, first, the logical values of the match lines ML0 to ML127 are “0”. As a result, the search result signals MS0Z to MS127Z = “0” output from the match line sense amplifiers 107 (0) to 107 (127) become “0”, and the search result determination signal DET0Z output from the search result determination circuit 83 becomes “1”. Become.

Therefore, search driver activation signal buffer 85 activates search driver 100 (p) by setting search driver activation signal SBE1Z = “1” in cycle Sw _{+ 1} . Further, the logical values of the search buses SB0 (p) and XSB0 (p) are supplied to the search driver 100 (p) via the flip-flop 101 (p). As a result, the search driver 100 (p) corresponds to the value of the search data D (p), and one of the search buses SB1 (p) and XSB1 (p) is “1” and the other is “=”. 0 ”.

  However, in this case, since the logical values of the match lines ML128 to ML255 are “0”, the match line sense amplifiers 107 (128) to 107 (255) set the search result signals MS128Z to MS255Z = “0”. The search result determination circuit 87 sets the search result determination signal DET1Z = “1”.

Therefore, the search driver activation signal buffer 89 sets the search driver activation signal SBE2Z = “1” and activates the search driver 102 (p) in the cycle Sw _{+ 2} . Further, the logical values of the search buses SB1 (p) and XSB1 (p) are supplied to the search driver 102 (p) via the flip-flop 104 (p). As a result, the search driver 102 (p) corresponds to the value of the search data D (p), and one of the search buses SB2 (p) and XSB2 (p) is “1” and the other is “=”. 0 ”.

  However, in this case, since the logical values of the match lines ML256 to ML383 are “0”, the match line sense amplifiers 107 (256) to 107 (383) set the search result signals MS256Z to MS383Z = “0”. The search result determination signal DET2Z output from the search result determination circuit 91 is set to “1”.

Therefore, the search driver activation signal buffer 93 sets the search driver activation signal SBE3Z = “1” and activates the search driver 103 (p) in the cycle Sw _{+ 3} . Further, the logical values of the search buses SB2 (p) and XSB2 (p) are supplied to the search driver 103 (p) via the flip-flop 105 (p). As a result, the search driver 103 (p) corresponds to the value of the search data D (p), and one of the search buses SB3 (p) and XSB3 (p) is “1” and the other is “=”. 0 ”.

  Here, the encoder 79 determines whether or not the search data DIN matches any of the data stored in the memory cell array 61 and whether or not the search data DIN matches any of the data stored in the memory cell array 62. The search result signals MS0Z to MS511Z are inputted and matched with any of the data stored in the memory cell array 64 regardless of whether the data matches with any of the data stored in the memory cell array 64. An address signal EA indicating an address for storing data is output.

  In the second embodiment of the present invention, the flip-flop units 72 to 74, the search result determination circuits 83, 87, 91, and the search bus activation signal buffers 85, 89, 93 include the memory cell arrays 62 to 64. A control unit for controlling the search operation for is configured.

  As described above, according to the second embodiment of the present invention, when the search command signal XSER is set to “0” and the search data DIN is given, the search is performed on the memory cell array 61, and the search data When DIN matches any of the data stored in the memory cell array 61, the search for the memory cell arrays 62 to 64 is not executed.

  When the search is performed on the memory cell array 61 and the search data DIN does not match all the data stored in the memory cell array 61, the search on the memory cell array 62 is executed. When the search data DIN matches any of the data stored in the memory cell array 62, the search for the memory cell arrays 63 and 64 is not executed.

  When the search is performed on the memory cell arrays 61 and 62 and the search data DIN does not match all the data stored in the memory cell arrays 61 and 62, the search on the memory cell array 63 is performed. When the search data DIN matches any of the data stored in the memory cell array 63, the search for the memory cell array 64 is not executed.

  Therefore, if the search data DIN matches any of the data stored in the memory cell array 61 and the search for the memory cell arrays 62 to 64 is not executed, the memory cell array is returned to the standby state. The match lines ML128 to ML511 provided in 62 to 64 do not need to be charged, and the search data DIN matches any of the data stored in the memory cell array 62, and the memory cell arrays 63 and 64 are targeted. If the search is not executed, the match lines ML256 to ML511 provided in the memory cell arrays 63 and 64 do not need to be charged when returning to the standby state, and the search data DIN is stored in the memory cell array. Matches any of the data stored in 63 When the search for the memory cell array 64 is not executed, the match lines ML384 to ML511 provided in the memory cell array 64 do not need to be charged when returning to the standby state. It is possible to reduce the number of match lines that require charging when returning to the standby state, thereby reducing current consumption.

(Third embodiment)
FIG. 13 is a circuit diagram showing a part of the third embodiment of the present invention. In the third embodiment of the present invention, encoders 110 to 120 and flip-flops 118 to 120 are provided in place of the encoder 79 included in the second embodiment of the present invention, and the others are the second embodiment of the present invention. The same circuit unit as the circuit unit included in is provided.

  The encoder 110 receives and encodes the search result signals MS0Z to MS127Z output from the match line sense amplifiers 107 (0) to 107 (127), outputs a 7-bit address signal EAA0, and the address signal EAA0 A 1-bit valid / invalid signal C0 indicating whether or not it is valid is output, and when the search data DIN matches the stored data at a plurality of addresses, an address indicating the minimum address among the plurality of addresses The signal EAA0 is output.

  Here, when any of the search result signals MS0Z to MS127Z is “1” (that is, when the search data DIN matches any of the data stored in the memory cell array 61), the encoder 110 performs the search. The address signal EAA0 indicating the address in the memory cell array 61 that stores the same data as the data DIN is output, and the valid / invalid signal C0 = "1", indicating that the address signal EAA0 is valid. On the other hand, when all of the search result signals MS0Z to MS127Z are “0” (that is, when the search data DIN does not match all of the data stored in the memory cell array 61), the valid / invalid signal C0 = "0", indicating that the address signal EAA0 is invalid.

  The encoder 111 receives and encodes the search result signals MS128Z to MS255Z output from the match line sense amplifiers 107 (128) to 107 (255), outputs a 7-bit address signal EAA1, and the address signal EAA1 A 1-bit valid / invalid signal C1 indicating whether or not it is valid is output, and when the search data DIN matches the stored data at a plurality of addresses, an address indicating the minimum address among the plurality of addresses The signal EAA1 is output.

  Here, when any of the search result signals MS128Z to MS255Z is “1” (that is, when the search data DIN matches any of the data stored in the memory cell array 62), the encoder 111 performs the search. The address signal EAA1 indicating the address in the memory cell array 62 at the address where the same data as the data DIN is stored is output, and the valid / invalid signal C1 = “1”, indicating that the address signal EAA1 is valid. Show. On the other hand, when all of the search result signals MS128Z to MS255Z are “0” (that is, when the search data DIN does not match all of the data stored in the memory cell array 62), the valid / invalid signal C1 = "0", indicating that the address signal EAA1 is invalid.

  The encoder 112 receives and encodes the search result signals MS256Z to MS383Z output from the match line sense amplifiers 107 (256) to 107 (383), outputs a 7-bit address signal EAA2, and the address signal EAA2 A 1-bit valid / invalid signal C2 indicating whether or not it is valid is output, and when the search data DIN matches the stored data at a plurality of addresses, an address indicating a minimum address among the plurality of addresses The signal EAA2 is output.

  Here, when any of the search result signals MS256Z to MS383Z is “1” (that is, when the search data DIN matches any of the data stored in the memory cell array 63), the encoder 112 performs the search. The address signal EAA2 indicating the address in the memory cell array 63 that stores the same data as the data DIN is output, and the valid / invalid signal C2 = "1", indicating that the address signal EAA2 is valid. Show. On the other hand, when all of the search result signals MS256Z to MS383Z are “0” (that is, when the search data DIN does not match all the data stored in the memory cell array 63), the valid / invalid signal C2 = "0", indicating that the address signal EAA2 is invalid.

  The encoder 113 receives and encodes the search result signals MS384Z to MS511Z output from the match line sense amplifiers 107 (384) to 107 (511), outputs a 7-bit address signal EAA3, and the address signal EAA3 is valid. 1-bit valid / invalid signal C3 indicating whether or not the address is stored, and when the search data DIN matches the stored data at a plurality of addresses, an address signal indicating the minimum address among the plurality of addresses EAA3 is output.

  Here, when any of the search result signals MS384Z to MS511Z is “1” (that is, when the search data DIN matches any of the data stored in the memory cell array 64), the encoder 113 performs the search. The address signal EAA3 indicating the address in the memory cell array 64 at the address storing the same data as the data DIN is output, and the valid / invalid signal C3 = "1", indicating that the address signal EAA3 is valid. Show. On the other hand, when all of the search result signals MS384Z to MS511Z are “0” (that is, when the search data DIN does not match all of the data stored in the memory cell array 64), the valid / invalid signal C3 = "0", indicating that the address signal EAA3 is invalid.

  If q = 0, 1,..., 127, the addresses in the memory cell array 61 of the memory cells 96 (q, 0) to 96 (q, n−1) in the memory cell array 61 are q addresses. Yes, the addresses in the memory cell array 62 of the memory cells 96 (q + 128, 0) to 96 (q + 128, n−1) in the memory cell array 62 are the addresses q, and the memory cells 96 (q + 256) in the memory cell array 63 , 0) to 96 (q + 256, n−1) in the memory cell array 63 is the address q, and the memory cells 96 (q + 384, 0) to 96 (q + 384, n−1) in the memory cell array 64 are addressed. The address in the memory cell array 64 of the portion is q address.

  The encoder 114 receives the address signal EAA0 and the valid / invalid signal C0 output from the encoder 110, sets the ninth and eighth bits in the address signal EAA0, and sets “00” to the ninth and eighth bits. Is added to output a 9-bit address signal EAB0 and a 1-bit valid / invalid signal CB0 indicating whether or not the address signal EAB0 is valid. When the valid / invalid signal C0 = "1", the encoder 114 sets the valid / invalid signal CB0 = "1" to indicate that the address signal EAB0 is valid, and the valid / invalid signal C0 = "0". In this case, the valid / invalid signal CB0 = "0", indicating that the address signal EAB0 is invalid.

  As described above, when the search data DIN matches any of the data stored in the memory cell array 61, the encoder 114 sets the memory cell arrays 61 to 64 in the memory cell portion storing the same data as the search data DIN. An address signal EAB0 indicating the address (address in the third embodiment of the present invention) when viewed as one memory cell array is output. The flip-flop 118 takes in the address signal EAB0 and the valid / invalid signal CB0 output from the encoder 114 in synchronization with the clock signal CLK and transfers them to the encoder 115.

  The encoder 115 receives the address signal EAB0 and valid / invalid signal CB0 output from the flip-flop 118, the address signal EAA1 and valid / invalid signal C1 output from the encoder 111, and outputs a 9-bit address signal EAB1. The 1-bit valid / invalid signal CB1 indicating whether or not the address signal EAB1 is valid is output.

  When the valid / invalid signal CB0 = "1" and the valid / invalid signal C1 = "0", the encoder 115 outputs the address signal EAB1 having the same value as the address signal EAB0 and the valid / invalid signal CB1 = " 1 "indicates that the address signal EAB1 is valid. On the other hand, when the valid / invalid signal CB0 = “0” and the valid / invalid signal C1 = “1”, the encoder 115 sets the ninth and eighth bits in the address signal EAA1. An address signal EAB1 in which "01" is added to the bit and the eighth bit is output, and the valid / invalid signal CB1 = "1" is set to indicate that the address signal EAB1 is valid. When the valid / invalid signal CB0 = "0" and the valid / invalid signal C1 = "0", the encoder 115 sets the valid / invalid signal CB1 = "0", indicating that the address signal EAB1 is invalid. Show.

  Thus, when the search data DIN matches any of the data stored in the memory cell array 62, the encoder 115 sets the memory cell arrays 61 to 64 of the memory cell portion storing the same data as the search data DIN. An address signal EAB1 indicating an address (address in the third embodiment of the present invention) when viewed as one memory cell array is output. The flip-flop 119 takes in the address signal EAB1 and the valid / invalid signal CB1 output from the encoder 115 in synchronization with the clock signal CLK and transfers them to the encoder 116.

  The encoder 116 receives the address signal EAB1 and valid / invalid signal CB1 output from the flip-flop 119, the address signal EAA2 and valid / invalid signal C2 output from the encoder 112, and outputs a 9-bit address signal EAB2. A 1-bit valid / invalid signal CB2 indicating whether or not the address signal EAB2 is valid is output.

  When the valid / invalid signal CB1 = "1" and valid / invalid signal C2 = "0", the encoder 116 outputs the address signal EAB2 having the same value as the address signal EAB1, and the valid / invalid signal CB2 = " 1 "indicates that the address signal EAB2 is valid. On the other hand, when the valid / invalid signal CB1 = "0" and the valid / invalid signal C2 = "1", the encoder 116 sets the ninth bit and the eighth bit in the address signal EAA2. An address signal EAB2 in which “10” is added to the bit and the 8th bit is output, and the valid / invalid signal CB2 = “1”, indicating that the address signal EAB2 is valid. When the valid / invalid signal CB1 = "0" and the valid / invalid signal C2 = "0", the encoder 116 sets the valid / invalid signal CB2 = "0", indicating that the address signal EAB2 is invalid. Show.

  In this way, the encoder 116 sets the memory cell arrays 61 to 64 of the memory cell portion storing the same data as the search data DIN when the search data DIN matches any of the data stored in the memory cell array 63. An address signal EAB2 indicating an address (address in the third embodiment of the present invention) when viewed as one memory cell array is output. The flip-flop 120 takes in the address signal EAB2 and the valid / invalid signal CB2 output from the encoder 116 in synchronization with the clock signal CLK and transfers them to the encoder 117.

  The encoder 117 receives the address signal EAB2 and valid / invalid signal CB2 output from the flip-flop 120, the address signal EAA3 and valid / invalid signal C3 output from the encoder 113, and outputs a 9-bit address signal EA. A valid / invalid signal CB3 indicating whether or not the address signal EA is valid is output.

  When the valid / invalid signal CB2 = "1" and the valid / invalid signal C3 = "0", the encoder 117 outputs the address signal EA having the same value as the address signal EAB2, and the valid / invalid signal CB3 = " 1 "indicates that the address signal EA is valid. On the other hand, when the valid / invalid signal CB2 = "0" and valid / invalid signal C3 = "1", the encoder 117 sets the ninth and eighth bits in the address signal EAA3. An address signal EA in which “11” is added to the bit and the eighth bit is output, and a valid / invalid signal CB3 = “1” is set to indicate that the address signal EA is valid. When the valid / invalid signal CB2 = "0" and the valid / invalid signal C3 = "0", the encoder 117 sets the valid / invalid signal CB3 = "0" and indicates that the address signal EA is invalid. Show.

  Thus, when the search data DIN matches any of the data stored in the memory cell array 64, the encoder 117 sets the memory cell arrays 61 to 64 of the memory cell portion storing the same data as the search data DIN. An address signal EA indicating an address (address in the third embodiment of the present invention) when viewed as one memory cell array is output.

  In the third embodiment of the present invention, the search driver 99 (p) is activated when the search driver activation signal SBE0Z = "1" and the clock signal CLK = "1", and the search data D Corresponding to the value of (p), one of the search buses SB0 (p) and XSB0 (p) is set to “0”, the other is set to “1”, and the search driver activation signal SBE0Z = “0”. Or when the clock signal CLK = "0", the inactive state is set, and the logical values of the search buses SB0 (p) and XSB0 (p) are "0".

  The search driver 100 (p) is activated when the search driver activation signal SBE1Z = “1” and the clock signal CLK = “1”, and corresponds to the value of the search data D (p), One of the search buses SB1 (p) and XSB1 (p) is set to “0”, the other is set to “1”, and the search driver activation signal SBE1Z = “0” or the clock signal CLK = “0”. In some cases, the inactive state is set, and the logical values of the search buses SB1 (p) and XSB1 (p) are set to “0”.

  The search driver 102 (p) is activated when the search driver activation signal SBE2Z = “1” and the clock signal CLK = “1”, and corresponds to the value of the search data D (p), One of the search buses SB2 (p) and XSB2 (p) is set to “0”, the other is set to “1”, and the search driver activation signal SBE2Z = “0” or the clock signal CLK = “0”. In some cases, the inactive state is set, and the logical values of the search buses SB2 (p) and XSB2 (p) are set to “0”.

  The search driver 103 (p) is activated when the search driver activation signal SBE3Z = “1” and the clock signal CLK = “1”, and corresponds to the value of the search data D (p), One of the search buses SB3 (p) and XSB3 (p) is set to “0”, the other is set to “1”, and the search driver activation signal SBE3Z = “0” or the clock signal CLK = “0”. At this time, the state is inactivated, and the logical values of the search buses SB3 (p) and XSB3 (p) are set to “0”.

  The match lines ML0 to ML511 are precharged when the level is detected when the clock signal CLK = "0". About others, it is comprised similarly to 2nd Embodiment of this invention.

  14 and 15 are timing charts showing an example of a search operation according to the third embodiment of the present invention. Search data DIN1 to DIN6 are successively given, and the search data DIN1 is stored in the memory cell array 61. The search data DIN2 matches any of the data stored in the memory cell array 62, the search data DIN3 matches any of the data stored in the memory cell array 63, and the search data DIN4 matches the memory cell array 64. Matches the data stored in the memory cell array 61, the search data DIN5 does not match all the data stored in the memory cell arrays 61 to 64, and the search data DIN6 matches any of the data stored in the memory cell array 61. The case where they match is taken as an example.

  14, (A) is a clock signal CLK that determines an operation cycle, (B) is search data DIN1 to DIN6, (C) is a search command signal XSER, (D) is a search driver activation signal SBE0Z, (E) is Search buses SB0 (p) and XSB0 (p) are logical values, (F) is a logical value of match lines ML0 to ML127, (G) is a search result signal MS0Z to MS127Z, and (H) is a search output from flip-flop 84. The result determination signal DET0Za, (I) is the search driver activation signal SBE1Z, (J) is the logic value of the search bus SB1 (p), XSB1 (p), (K) is the logic value of the match lines ML128 to ML255, (L ) Is a search result signal MS128Z to MS255Z, (M) is a search result determination signal DET1Za output from the flip-flop 88, ( ) Is the search driver activation signal SBE2Z, (O) is the logical value of the search bus SB2 (p), XSB2 (p), (P) is the logical value of the match lines ML256 to ML383, and (Q) is the search result signal MS256Z to MS383Z, (R) is a search result determination signal DET2Za output from the flip-flop 92, (S) is a search driver activation signal SBE3Z, (T) is a logical value of the search buses SB3 (p), XSB3 (p), (U ) Represents the logical values of the match lines ML384 to ML511, and (V) represents the search result signals MS384Z to MS511Z.

  15, (A) is a clock signal CLK, (B) is search data DIN1 to DIN6, (C) is an address signal EAA0 output from the encoder 110, (D) is an address signal EAB0 output from the encoder 114, (E ) Is an address signal EAA1 output from the encoder 111, (F) is an address signal EAB1 output from the encoder 115, (G) is an address signal EAA2 output from the encoder 112, (H) is an address signal EAB2 output from the encoder 116, (I) shows an address signal EAA3 output from the encoder 113, and (J) shows an address signal EA output from the encoder 117.

  A1 is an address (any of addresses 0 to 127) in the memory cell array 61 of the memory cell portion of the memory cell array 61 that stores the same data as the search data DIN1, and is indicated by the address signal EAA0. . A1C is an address when the memory cell array 61 to 64 is regarded as one memory cell array at the address A1 (address in the third embodiment of the present invention = any of addresses A1 = 0 to 127), and the address signal EAB0 , EAB1, EAB2, and EA.

  A2 is an address (any one of addresses 0 to 127) in the memory cell array 62 of the memory cell portion in the memory cell array 62 that stores the same data as the search data DIN2, and is indicated by the address signal EAA1. A2C is an address when the memory cell array 61 to 64 is regarded as one memory cell array at the address A2 (address in the third embodiment of the present invention = A2 + 128 = any of addresses 128 to 255), and the address signal EAB1 , EAB2, and EA.

  A3 is an address (any one of addresses 0 to 127) in the memory cell array 63 of the memory cell portion in the memory cell array 63 storing the same data as the search data DIN3, and is indicated by the address signal EAA2. A3C is an address when the memory cell array 61 to 64 is regarded as one memory cell array at the address A3 (address in the third embodiment of the present invention = A3 + 256 = any of addresses 256 to 383), and the address signal EAB2 , EA.

  A4 is an address (any one of addresses 0 to 127) in the memory cell array 64 of the memory cell portion in the memory cell array 64 storing the same data as the search data DIN4, and is indicated by the address signal EAA3. A4C is an address when the memory cell array 61 to 64 is regarded as one memory cell array at the address A4 (address in the third embodiment of the present invention = A4 + 384 = any one of addresses 384 to 511), and the address signal EA Is shown.

  A6 is an address (any one of addresses 0 to 127) in the memory cell array 64 of the memory cell portion in the memory cell array 61 that stores the same data as the search data DIN6, and is indicated by the address signal EAA0. A6C is an address when the memory cell array 61 to 64 at the address A6 is regarded as one memory cell array (address in the third embodiment of the present invention = any of addresses A6 = 0 to 127), and the address signal EAB0, EAB1, EAB2, and EA indicate this.

That is, in the third embodiment of the present invention, for example, the cycle S together with the search command signal XSER is "0" in the second half when _w, cycle S late time and cycle S _{w + 1} in the first half time of the search data for _w When DIN1 is input, the search drivers 99 (0) to 99 (n-1) are activated in the first half of the cycle Sw _{+ 1} , and the search buses SB0 (0) and XSB0 (0) to the memory cell array 61 are activated. SB0 (n-1) and XSB0 (n-1) are driven.

Here, since the search data DIN1 matches any of the data stored in the memory cell array 61, any one of the logical values = “1” of the match lines ML0 to ML127 and any of the search result signals MS0Z to MS127Z. The logic value = “1” is maintained, and in the cycles S _{w + 1} and S _{w + 2} , the search result determination signal DET0Za = “0” and the search driver activation signal SBE1Z = “0” are maintained, and the search driver 100 (0) to 100 (n-1) are inactive.

As a result, in the cycles S _{w + 1} and S _{w + 2} , the logical values of the match lines ML128 to ML255 = “1” and the logical values of the search result signals MS128Z to MS255Z = “1” are maintained, and the cycle S _{w + In 1 to} Sw _{+ 3} , the search result determination signal DET1Za = "0" and the search driver activation signal SBE2Z = "0" are maintained, and the search drivers 102 (0) to 102 (n-1) are inactive. Is done.

As a result, in the cycles S _{w + 1 to} S _{w + 3} , the logical values of the match lines ML256 to ML383 = “1” and the logical values of the search result signals MS256Z to MS383Z = “1” are maintained. _{In w + 1 to} S _{w + 4} , the search result determination signal DET2Za = “0” and the search driver activation signal SBE3Z = “0” are maintained, and the search drivers 103 (0) to 103 (n−1) are not. It is considered active.

Then, the cycle S when _{w + 1} of the second half time and cycle S _{w + 2} search in the first half time of data DIN2 is inputted, during the first half of the cycle S _{w + 2,} search driver 99 (0) ~99 (n- 1 ) Is activated to drive the search buses SB0 (0), XSB0 (0) to SB0 (n-1), XSB0 (n-1) of the memory cell array 61.

Here, since the search data DIN2 does not match all the data stored in the memory cell array 61, the logical values of the match lines ML0 to ML127 = “0” and the logical values of the search result signals MS0Z to MS127Z = “0”. In the cycle S _{w + 3} , the search result determination signal DET0Za = “1” and the search driver activation signal SBE1Z = “1”, and the search drivers 100 (0) to 100 (n−1) _In the first half of _{w + 3} , the search buses SB1 (0), XSB1 (0) to SB1 (n-1), and XSB1 (n-1) of the memory cell array 62 are activated.

Here, since the search data DIN2 matches any of the data stored in the memory cell array 62, any one of the logical values = “1” of the match lines ML128 to ML255 and any of the search result signals MS128Z to MS255Z. The logic value = “1” is maintained, and in the cycles S _{w + 1 to} S _{w + 4} , the search result determination signal DET1Za = “0” and the search driver activation signal SBE2Z = “0” are maintained, and the search driver 102 (0) to 102 (n-1) are inactive.

As a result, in the cycles S _{w + 1 to} S _{w + 4} , the logical values of the match lines ML256 to ML383 = “1” and the logical values of the search result signals MS256Z to MS383Z = “1” are maintained, and the cycle S _{In w + 1 to} S _{w + 5} , the search result determination signal DET2Za = "0" and the search driver activation signal SBE3Z = "0" are maintained, and the search drivers 103 (0) to 103 (n-1) are not It is considered active.

Then, the cycle S when _{w + 2} in the second half of the time and cycle S _{w + 3} in the first half time of the search data DIN3 is input, in the first half time of the cycle S _{w + 3,} search driver 99 (0) ~99 (n- 1 ) Is activated to drive the search buses SB0 (0), XSB0 (0) to SB0 (n-1), XSB0 (n-1) of the memory cell array 61.

Here, the search data DIN3 does not match all of the data stored in the memory cell array 61. Therefore, the logical values of the match lines ML0 to ML127 = “0” and the logical values of the search result signals MS0Z to MS127Z = “0”. In the cycle S _{w + 4} , the search result determination signal DET0Za = “1” and the search driver activation signal SBE1Z = “1”. In the first half of the cycle S _{w + 4} , the search drivers 100 (0) to 100 (N-1) is activated and drives the search buses SB1 (0), XSB1 (0) to SB1 (n-1), and XSB1 (n-1) of the memory cell array 62.

Here, since the search data DIN3 does not match all the data stored in the memory cell array 62, the logical values of the match lines ML128 to ML255 = “0” and the logical values of the search result signals MS128Z to MS255Z = “0”. In cycle S _{w + 5} , search result determination signal DET1Za = “1”, search driver activation signal SBE2Z = “1”, and in the first half of cycle S _{w + 5} , search drivers 102 (0) -102 (N-1) is activated and drives the search buses SB2 (0), XSB2 (0) to SB2 (n-1), and XSB2 (n-1) of the memory cell array 63.

Here, since the search data DIN3 matches any of the data stored in the memory cell array 63, any one of the logical values of the match lines ML256 to ML383 = “1” and any of the search result signals MS256Z to MS383Z. The logic value = “1” is maintained, and in the cycles S _{w + 1 to} S _{w + 6} , the search result determination signal DET2Za = “0” and the search driver activation signal SBE3Z = “0” are maintained, and the search driver 103 (0) to 103 (n-1) are inactive.

Then, the cycle S when _{w +} search data DIN4 late time and during the first half of the cycle S _{w + 4 3} is input, when the first half of the cycle S _{w + 4,} search driver 99 (0) ~99 (n- 1 ) Is activated to drive the search buses SB0 (0), XSB0 (0) to SB0 (n-1), XSB0 (n-1) of the memory cell array 61.

Here, since the search data DIN4 does not match all the data stored in the memory cell array 61, the logical values of the match lines ML0 to ML127 = “0” and the logical values of the search result signals MS0Z to MS127Z = “0”. ”Is maintained, and in the cycle S _{w + 5} , the search result determination signal DET0Za =“ 1 ”and the search driver activation signal SBE1Z =“ 1 ”, and in the first half of the cycle S _{w + 5} , the search driver 100 (0) ˜100 (n−1) is activated and drives the search buses SB1 (0), XSB1 (0) to SB1 (n−1), and XSB1 (n−1) of the memory cell array 62.

Here, since the search data DIN4 does not match all the data stored in the memory cell array 62, the logical values of the match lines ML128 to ML255 = “0” and the logical values of the search result signals MS128Z to MS255Z = “0”. In the cycle S _{w + 6} , the search result determination signal DET1Za = “1”, the search driver activation signal SBE2Z = “1”, and in the first half of the cycle S _{w + 6} , the search drivers 102 (0) to 102 (N-1) is activated and drives the search buses SB2 (0), XSB2 (0) to SB2 (n-1), and XSB2 (n-1) of the memory cell array 63.

Here, since the search data DIN4 does not match all the data stored in the memory cell array 63, the logical values of the match lines ML256 to ML383 = “0” and the logical values of the search result signals MS256Z to MS383Z = “0”. In cycle S _{w + 7} , search result determination signal DET2Za = “1”, search driver activation signal SBE3Z = “1”, and in the first half of cycle S _{w + 7} , search drivers 103 (0) to 103 (N−1) is activated and drives the search buses SB3 (0), XSB3 (0) to SB3 (n−1), and XSB3 (n−1) of the memory cell array 64. Here, the search data DIN4 coincides with all of the data stored in the memory cell array 64. Therefore, any one of the logical values of the match lines ML384 to ML511 = “1” and the search result signals MS384Z to MS511Z. The logical value of “= 0”.

Next, the search data DIN5 the first half time of the cycle S _{w + 4} of the second half time and cycle S _{w + 5} is input, when the first half of the cycle S _{w + 5,} the search driver 99 (0) ~99 (n- 1 ) Is activated to drive the search buses SB0 (0), XSB0 (0) to SB0 (n-1), XSB0 (n-1) of the memory cell array 61.

Here, the search data DIN5 does not match all of the data stored in the memory cell array 61. Therefore, the logical values of the match lines ML0 to ML127 = “0” and the logical values of the search result signals MS0Z to MS127Z = “0”. In the cycle S _{w + 6} , the search result determination signal DET0Za = “1”, the search driver activation signal SBE1Z = “1”, and in the first half of the cycle S _{w + 6} , the search drivers 100 (0) to 100 (N−1) is activated and drives the search buses SB1 (0), XSB1 (0) to SB1 (n−1), and XSB1 (n−1) of the memory cell array 62.

Here, since the search data DIN5 does not match all the data stored in the memory cell array 62, the logical values of the match lines ML128 to ML255 = “0” and the logical values of the search result signals MS128Z to MS255Z = “0”. In cycle S _{w + 7} , search result determination signal DET1Za = “1”, search driver activation signal SBE2Z = “1”, and in the first half of cycle S _{w + 7} , search drivers 102 (0) -102 (N-1) is activated and drives the search buses SB2 (0), XSB2 (0) to SB2 (n-1), and XSB2 (n-1) of the memory cell array 63.

Here, since the search data DIN5 does not match all the data stored in the memory cell array 63, the logical values of the match lines ML256 to ML383 = “0” and the logical values of the search result signals MS256Z to MS383 = “0”. In the cycle S _{w + 8} , the search result determination signal DET2Za = “1”, the search driver activation signal SBE3Z = “1”, and in the first half of the cycle S _{w + 8} , the search drivers 103 (0) to 103 (N-1) is activated and drives the search buses SB3 (0), XSB3 (0) to SB3 (n-1), XSB3 (n-1) of the memory cell array 64.

Next, the search data DIN6 in the first half time of the cycle S _{w + 5} in the second half of the time and cycle S _{w + 6} is input, when the first half of the cycle S _{w + 6,} the search driver 99 (0) ~99 (n- 1 ) Is activated to drive the search buses SB0 (0), XSB0 (0) to SB0 (n-1), XSB0 (n-1) of the memory cell array 61.

Here, since the search data DIN6 matches any of the data stored in the memory cell array 61, any one of the logical values = “1” of the match lines ML0 to ML127 and any of the search result signals MS0Z to MS127Z. The logic value = “1” is maintained, and in the cycle Sw _{+ 7} , the search result determination signal DET0Za = “0” and the search driver activation signal SBE1Z = “0” are maintained, and the search drivers 100 (0) to 100 (N-1) is inactivated.

As a result, in the cycle S _{w + 7} , the logical values of the match lines ML128 to ML255 = “1” and the logical values of the search result signals MS128 to MS255Z = “1” are maintained. In the cycle S _{w + 8} , the search is performed. The result determination signal DET1Za = "0" and the search driver activation signal SBE2Z = "0" are maintained, and the search drivers 102 (0) to 102 (n-1) are deactivated.

As a result, in the cycle S _{w + 8} , the logical values of the match lines ML256 to ML383 = “1” and the logical values of the search result signals MS256 to ML383 = “1” are maintained, and in the cycle S _{w + 9} The search result determination signal DET2Za = "0" and the search driver activation signal SBE3Z = "0" are maintained, and the search drivers 103 (0) to 103 (n-1) are deactivated.

In the third embodiment of the present invention, the search drivers 99 (0) to 99 (n-1) are activated in the first half of the cycle Sw _{+ 1} , and the search data DIN1 is stored in the memory cell array 61. If the data coincides with any one of the data, the encoder 110, as shown in FIG. 15C, shows an address signal indicating the address A1 which is the address in the memory cell array 61 of the memory cell portion storing the same data as the search data DIN1. Outputs EAA0.

As a result, the encoder 114 inputs the address signal EAA0 indicating the address A1 in the cycle Sw _{+ 1} , and the address A1 which is the address in the memory cell array 61 is stored in the memory cell array 61 as shown in FIG. ... To 64 are converted into addresses when viewed as one memory cell array, and an address signal EAB0 indicating the converted address A1C is output.

As a result, the encoder 115 inputs the address signal EAB0 indicating the A1C address via the flip-flop 118 in the cycle S _{w + 2} and the address signal EAB1 indicating the A1C address as shown in FIG. 15 (F). Is output. In the cycle S _{w + 3} , the encoder 116 inputs the address signal EAB1 indicating the A1C address via the flip-flop 119, and outputs the address signal EAB2 indicating the A1C address as shown in FIG. In the cycle S _{w + 4} , the encoder 117 receives the address signal EAB2 indicating the A1C address via the flip-flop 120, and outputs the address signal EA indicating the A1C address as shown in FIG.

When the search drivers 100 (0) to 100 (n-1) are activated in the first half of the cycle S _{w + 3} and the search data DIN2 matches any of the data stored in the memory cell array 62, the encoder 111 As shown in FIG. 15E, an address signal EAA1 indicating the address A2 which is the address in the memory cell array 62 of the memory cell portion storing the same data as the search data DIN2 is output.

As a result, the encoder 115 inputs the address signal EAB1 indicating the address A2 in the cycle S _{w + 3} , and the address A2 which is the address in the memory cell array 62 as shown in FIG. ... To 64 are converted into addresses when viewed as one memory cell array, and an address signal EAB1 indicating the converted address A2C is output.

As a result, the encoder 116 inputs the address signal EAB1 indicating the address A2C via the flip-flop 119 in the cycle SW _{+ 4} , and the address signal EAB2 indicating the address A2C as shown in FIG. 15 (H). Is output. In the cycle SW _{+ 5} , the encoder 117 receives the address signal EAB2 indicating the A2C address via the flip-flop 120, and outputs the address signal EA indicating the A2C address as shown in FIG.

When the search drivers 102 (0) to 102 (n-1) are activated during the first half of the cycle S _{w + 5} and the search data DIN3 matches any of the data stored in the memory cell array 63, the encoder 112 15G outputs an address signal EAA2 indicating the address A3 which is the address in the memory cell array 63 of the memory cell portion storing the same data as the search data DIN3, as shown in FIG.

As a result, the encoder 116 inputs the address signal EAA2 indicating the address A3 in the cycle S _{w + 5} , and the address A3 which is the address in the memory cell array 63 as shown in FIG. ... To 64 are converted into addresses when viewed as one memory cell array, and an address signal EAB2 indicating the converted address A3C is output. In the cycle S _{w + 6} , the encoder 117 receives the address signal EAB2 indicating the A3C address via the flip-flop 120, and outputs the address signal EA indicating the A3C address as shown in FIG.

When the search drivers 103 (0) to 103 (n-1) are activated in the first half of the cycle S _{w + 7} and the search data DIN4 matches any of the data stored in the memory cell array 64, the encoder 113 Outputs an address signal EAA3 indicating the address A4 which is the address in the memory cell array 64 of the memory cell portion storing the same data as the search data DIN4, as shown in FIG. In the cycle S _{w + 7} , the encoder 117 receives the address signal EAA3 indicating the A4 address, and outputs the address signal EA indicating the A4C address as shown in FIG.

When the search drivers 99 (0) to 99 (n-1) are activated in the first half of the cycle S _{w + 6} and the search data DIN6 matches any of the data stored in the memory cell array 61, the encoder 110 15C outputs an address signal EAA0 indicating the address A6 which is the address in the memory cell array 61 of the memory cell portion storing the same data as the search data DIN6, as shown in FIG.

As a result, the encoder 114 inputs the address signal EAA0 indicating the address A6 in the cycle Sw _{+ 6} , and the address A6, which is the address in the memory cell array 61, is input to the memory cell array 61 as shown in FIG. ... To 64 are converted into addresses when viewed as one memory cell array, and an address signal EAB0 indicating the converted address A6C is output.

As a result, the encoder 115 inputs the address signal EAB0 indicating the A6C address via the flip-flop 118 in the cycle S _{w + 7} , and the address signal EAB1 indicating the A6C address as shown in FIG. 15 (F). Is output. In the cycle S _{w + 8} , the encoder 116 inputs the address signal EAB1 indicating the A6C address via the flip-flop 119, and outputs the address signal EAB2 indicating the A6C address as shown in FIG. In cycle S _{w + 9} , encoder 117 receives address signal EAB2 indicating address A6C via flip-flop 120, and outputs address signal EA indicating address A6C as shown in FIG. 15 (J).

  As described above, in the third embodiment of the present invention, the encoder 110 is provided, and if the search data DIN matches any of the data stored in the memory cell array 61, the same data as the search data DIN is stored. An address signal EAA0 indicating the address in the memory cell array 61 of the memory cell portion to be output is output. Also, an encoder 111 is provided, and when the search data DIN matches any of the data stored in the memory cell array 62, the address in the memory cell array 62 of the memory cell portion storing the same data as the search data DIN is set. The address signal EAA1 shown is output.

  Further, an encoder 112 is provided, and when the search data DIN matches any of the data stored in the memory cell array 63, the address in the memory cell array 63 of the memory cell portion storing the same data as the search data DIN is set. The address signal EAA2 shown is output. Further, an encoder 113 is provided, and if the search data DIN matches any of the data stored in the memory cell array 64, the address in the memory cell array 64 of the memory cell portion that stores the same data as the search data DIN is set. The address signal EAA3 shown is output.

  When the address signal EAA0 is valid, the address in the memory cell array 61 indicated by the address signal EAA0 is converted into an address when the memory cell arrays 61 to 64 are viewed as one memory cell array, and the address signals EAB0, EAB1, EAB2 is pipeline-transferred from the encoder 114 to the encoder 117 via the encoders 115 and 116, and output from the encoder 117 as the address signal EA.

  When the address signal EAA1 is valid, the address in the memory cell array 62 indicated by the address signal EAA1 is converted to the address when the memory cell arrays 61 to 64 are viewed as one memory cell array, and the address signals EAB1 and EAB2 are used. Pipeline transfer is performed from the encoder 115 to the encoder 117 via the encoder 116, and is output from the encoder 117 as the address signal EA.

  When the address signal EAA2 is valid, the address in the memory cell array 63 indicated by the address signal EAA2 is converted to an address when the memory cell arrays 61 to 64 are viewed as one memory cell array, and the encoder 116 serves as the address signal EAB2. To the encoder 117. When the address signal EAA3 is valid, the encoder 117 converts the address in the memory cell array 64 indicated by the address signal EAA3 into an address when the memory cell arrays 61 to 64 are viewed as one memory cell array. Output as EA.

  According to the third embodiment of the present invention, as in the second embodiment of the present invention shown in FIG. 8, after the search, the number of match lines that need to be charged when returning to the standby state is reduced. In addition to being able to reduce the number of data, the memory cell arrays 61 to 64 can perform different search operations for different search data at the same time, thereby increasing the speed of successive search operations.

(Other)
In the first to third embodiments of the present invention, the case where a binary type memory cell is used has been described. In addition, the present invention, for example, uses a ternary (as shown in FIG. A ternary type memory cell can also be used. In FIG. 16, 123 is a flip-flop which is one storage medium, and 124 and 125 are inverters. S0 and S1 are storage nodes, and 126 and 127 are NMOS transistors whose ON and OFF are controlled by the potential of the word line WL. Reference numeral 128 denotes a flip-flop which is the other storage medium, and reference numerals 129 and 130 denote inverters. S3 and S4 are storage nodes, and 131 and 132 are NMOS transistors whose ON and OFF are controlled by the potential of the word line WL.

  133 is an NMOS transistor whose ON / OFF is controlled by the potential of the storage node S1, 134 is an NMOS transistor whose ON / OFF is controlled by the potential of the storage node S4, and 135 is ON / OFF controlled by the potential of the search bus SB. The NMOS transistor 136 is an NMOS transistor whose ON and OFF are controlled by the potential of the search bus XSB.

  16 uses the word line WL, the bit lines BL0, XBL0, BL1, and XBL1 and the NMOS transistors 126, 127, 131, and 132 for writing data to and reading data from the memory cell shown in FIG. Done. Table 3 shows the storage data of the memory cell shown in FIG. 16 and the logical values of the bit lines BL0, XBL0, BL1, and XBL1 at the time of data writing to and reading from the memory cell shown in FIG. Showing the relationship.

  Further, the search for the memory cell shown in FIG. 16 is performed using the search buses SB and XSB, the NMOS transistors 133 to 136, and the match line ML. Table 4 shows the relationship between the data stored in the memory cell shown in FIG. 16 and the logical values of the search buses SB and XSB during the search.

  In the first to third embodiments of the present invention, the case where the SRAM cell is used as the memory cell has been described. However, the present invention is also applicable to the case where a memory cell other than the SRAM cell is used. Of course you can.

It is a circuit diagram showing a part of a 1st embodiment of the present invention. It is a circuit diagram which shows a part of 1st Embodiment of this invention in more detail. 2 is a circuit diagram showing in more detail a portion of one memory cell array included in the first embodiment of the present invention; FIG. FIG. 3 is a circuit diagram showing in more detail a portion of the other memory cell array included in the first embodiment of the present invention. It is a circuit diagram which shows a part of 1st Embodiment of this invention in more detail. It is a timing diagram which shows the example of search operation | movement of 1st Embodiment of this invention. It is a timing diagram which shows the example of search operation | movement of 1st Embodiment of this invention. It is a circuit diagram which shows a part of 2nd Embodiment of this invention. It is a circuit diagram which shows a part of 2nd Embodiment of this invention in more detail. It is a circuit diagram which shows a part of 2nd Embodiment of this invention in more detail. It is a circuit diagram which shows a part of 2nd Embodiment of this invention in more detail. It is a timing diagram which shows the example of search operation of 2nd Embodiment of this invention. It is a circuit diagram which shows a part of 3rd Embodiment of this invention. It is a timing diagram which shows the example of search operation | movement of 3rd Embodiment of this invention. It is a timing diagram which shows the example of search operation | movement of 3rd Embodiment of this invention. It is a circuit diagram which shows the other example of the memory cell which can be used for this invention. It is a figure for demonstrating the function of an associative memory compared with RAM. It is a circuit diagram which shows an example of the memory cell with which an associative memory is provided. FIG. 19 is a circuit diagram for illustrating a search operation for the memory cell shown in FIG. 18. FIG. 19 is a circuit diagram for illustrating a search operation for the memory cell shown in FIG. 18. FIG. 19 is a circuit diagram for illustrating a search operation for the memory cell shown in FIG. 18. FIG. 19 is a circuit diagram for illustrating a search operation for the memory cell shown in FIG. 18. FIG. 19 is a waveform diagram showing potential changes of a search bus and a match line during a search for the memory cell shown in FIG. 18. It is a circuit diagram which shows the relationship between the memory cell in an actual associative memory, and a match line. It is a block diagram which shows a part of example of the conventional associative memory. FIG. 26 is a circuit diagram showing a part of the conventional content addressable memory shown in FIG. 25 in more detail. FIG. 26 is a circuit diagram showing in more detail a portion of a memory cell array included in the conventional content addressable memory shown in FIG. 25. FIG. 26 is a circuit diagram for explaining a search operation example of the conventional associative memory shown in FIG. 25. FIG. 26 is a timing diagram for explaining an example of a search operation of the conventional associative memory shown in FIG. 25. FIG. 26 is a timing diagram for explaining an example of a search operation of the conventional associative memory shown in FIG. 25. It is a figure for demonstrating the priority matching function which the conventional associative memory shown in FIG. 25 has.

Explanation of symbols

1 ... RAM
2 ... Associative memory (CAM)
3 ... Memory cell (MC)
4 ... flip-flop 5, 6 ... inverter 7-12 ... NMOS transistor 15 ... match line sense amplifier (MLSA)
DESCRIPTION OF SYMBOLS 16 ... Memory cell array 17 ... Word decoder (WDEC) part 18 ... Write amplifier (W / A) part 19 ... Sense amplifier (S / A) part 20 ... Search driver (S / D) part 21 ... Match line sense amplifier ( MLSA) 22: Encoder (ENC)
23 ... Command decoder (COMDEC)
24 ... Search driver activation signal generation circuit (SBBEGEN)
25 ... Word driver (WDEC)
26 ... Light amplifier (W / A)
27 ... Sense amplifier (S / A)
28 ... Search driver (S / D)
31, 32 ... Memory cell array (MCA)
33 ... Word decoder (WDEC) unit 34 ... Line amplifier (W / A) unit 35 ... Sense amplifier (S / A) unit 36, 37 ... Search driver (S / D) unit 38 ... Flip-flop (FF) unit 39, 40: Match line sense amplifier (MLSA) 41: Encoder (ENC)
42 ... Command decoder (COMDEC)
43 ... Search driver activation signal generation circuit (SBBEGEN)
44 ... flip-flop (FF)
45 ... Search result judgment circuit (DET)
46 ... Search driver activation signal buffer (SBEBUF)
50 ... Memory cell (MC)
51 ... Light amplifier (W / A)
52. Sense amplifier (S / A)
53, 54 ... Search driver (S / D)
55. Flip-flop (FF)
56 ... Match line sense amplifier (MLSA)
61-64 ... Memory cell array (MCA)
65: Word decoder (WDEC) unit 66: Write amplifier (W / A) unit 67 ... Sense amplifier (S / A) unit 68-71 ... Search driver (S / D) unit 72-74 ... Flip-flop (FF) unit 75 to 78 ... match line sense amplifier (MLSA) section 79 ... encoder (ENC)
80 ... Command decoder (COMDEC)
81 ... Search driver activation signal generation circuit (SBBEGEN)
82. Flip-flop (FF)
83 ... Search result judgment circuit (DET)
84 ... flip-flop (FF)
85 ... Search driver activation signal buffer (SBEBUF)
86 ... Flip-flop (FF)
87 ... Search result judgment circuit (DET)
88 ... flip-flop (FF)
89 ... Search driver activation signal buffer (SBEBUF)
90 ... flip-flop (FF)
91 ... Search result judgment circuit (DET)
92 ... flip-flop (FF)
93 ... Search driver activation signal buffer (SBEBUF)
96 ... Memory cell (MC)
97 ... Light amplifier (W / A)
98 ... Sense amplifier (S / A)
99, 100 ... Search driver (S / D)
101 ... flip-flop (FF)
102, 103 ... Search driver (S / D)
104, 105 ... flip-flop (FF)
106: Word decoder (WDEC)
107 ... Match line sense amplifier (MLSA)
110-117 ... Encoder (ENC)
118-120 ... flip-flop (FF)
123 ... flip-flop (FF)
124, 125 ... inverter 126, 127 ... NMOS transistor 128 ... flip-flop 129, 130 ... inverter 131-136 ... NMOS transistor

Claims (3)

First, second,..., K-th (where k is an integer equal to or greater than 2) memory cell arrays that are sequentially searched for search data given from the outside;
An i-th match line sense amplifier provided corresponding to the i-th (where i = 1, 2,..., K) memory cell array;
The output value of the j-th (where j = 1,..., K−1) match line sense amplifier is not the memory cell array in which the j-th memory cell array stores the same data as the search data. only if they represent a control unit of the j-th control the search operation to perform a search for the (j + 1) of the memory cell array,
If the output value of the i-th match line sense amplifier indicates that the search data matches any of the data stored in the i-th memory cell array, the same data as the search data A first-type i-th encoder that outputs a first-type i-th address signal indicating an address in the i-th memory cell array of a memory cell portion that stores
The first-type i-th address signal is input, and the address indicated by the first-type i-th address signal is converted into an address when the first to k-th memory cell arrays are viewed as one memory cell array. And a second type i-th encoder that outputs a second type i-th address signal indicating the converted address,
The first, second,..., Kth encoders of the second type are the first,..., K-1th of the second types output by the first, first,. An associative memory characterized by being connected so that an address signal can be pipeline-transferred toward a second type k-th encoder . An i-th search bus provided corresponding to the i-th memory cell array and connected to the memory cells in the i-th memory cell array;
An i-th search driver unit provided corresponding to the i-th memory cell array and driving the i-th search bus to set the memory cells in the i-th memory cell array to a search operation state;
The j-th control unit is
The jth search result for determining whether or not the jth memory cell array is not a memory cell array storing the same data as the search data, based on the output value of the jth match line sense amplifier A determination circuit;
When the j-th search result determination circuit determines that the j-th memory cell array is not a memory cell array storing the same data as the search data, the j-th search result determination circuit activates the j + 1-th search driver unit, and when the memory cell array of the first j is determined to be a memory cell array that stores the search data and the same data, and the (j + 1) of the search driver activating circuit to the (j + 1) th search driver inactive The associative memory according to claim 1 , further comprising: The logical value of the search buses of the j comprises a transfer means for transferring the search driver portion of the first j + 1,
The first search driver unit drives the first search bus based on the search data given from the outside,
Search driver unit of the (j + 1) th, the claim 2, characterized in that the logical value of the j + 1 of the search buses to drive the (j + 1) th search bus so as to become the same as the logical value of the search buses of the first j The associative memory described in 1.

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