JP2003132686A - Associative memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an associative memory device in which operation speed is increased and power consumption is reduced. SOLUTION: A pair of bit lines 33- n, 33- nN for retrieving is held at an intermediate potential at the standby of retrieving, while a coincidence line 14- m is put in a discharged state at timing of start of applying of retrieving data by a coincidence line control section 50, after that, the prescribed electric charges are injected to the coincidence line 14- m, after that, a word memory in which data corresponding to retrieving data on the pair of bit lines 33- n, 33- nN for retrieving based on a potential of the coincidence line 14- m is stored is detected by an coincidence detecting section 40.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an associative memory.

[0002]

2. Description of the Related Art Conventionally, both functions of an ordinary semiconductor memory have a function of writing stored data in a word memory at a designated address and a function of reading stored data stored in a word memory at a designated address. In addition, an associative memory (Asso memory) having a function of detecting a word memory in which stored data corresponding to search data is stored
content memory, content addressable memory; Content Addressable Mem
ory) is known.

FIG. 4 is a circuit block diagram showing an example of a conventional associative memory.

This associative memory 100 has N bits of 1
N bits × M, which has M word memories as words
A CAM cell array 11 having a word structure is provided.

The associative memory 100 is also provided with a bit line control circuit 12 to which one word of data DATA is input.
And bit line pairs 13_0, 13_0N; 13_1, 1 extending across the corresponding bit cells of the M word memories.
3_1N; ...; 13_N-1, 13_N-1N are provided. Each bit line pair 13_0, 13_0N; 13_
1, 13_1N; ...; 13_N-1, 13_N-1N
Are bit line pair signals BL <0>, BLN <0>; BL
<1>, BLN <1>;...; BL <N-1>, BLN <
N-1> is transmitted.

Further, the associative memory 100 has match line signals ML <0> and ML <1 corresponding to each word memory.
>, ..., Matching lines 14_0,1 for transmitting ML <M-1>
4_1, ..., 14_M-1 are provided.

In the associative memory 100, bit line pairs 13_0, 13_0N; 13_1, 13_1N; ...; 1
Matching lines 14_0, 14_1, ..., 14_M- in a state in which search data is applied to 3_N-1, 13_N-1N.
Based on the potential of 1, the bit line pair 13_0, 13
_0N; 13_1,13_1N; ...; 13_N-1,1
A match detection circuit 15 is provided for detecting whether or not the search data on 3_N-1N and the stored data in the word memory match.

Further, the associative memory 100 has a decoder 17 for inputting and decoding the address data ADR,
Word line signals WL <0>, WL <1>, ..., WL <M-
1> transmitting word lines 18_0, 18_1, ..., 18
_M-1 is provided.

FIG. 5 is a diagram showing a circuit of one CAM cell forming the CAM cell array shown in FIG.

The CAM cell 110 shown in FIG. 5 has a storage section 120 in which the stored data is written and the stored data is read, as in a normal semiconductor memory, and the storage section 120.
Data stored in and the data you want to search (search data)
It is comprised from the comparison part 130 which compares with.

The storage section 120 is a normal SRAM cell in which 1-bit data is stored, and a latch circuit 123 composed of inverters 121 and 122 whose inputs and outputs are cross-coupled to each other, and one end of the latch circuit 123. The transfer gate 124 arranged between the inverted bit line 13_nN and the other end of the latch circuit 123 and the bit line 1
3_n and a transfer gate 125 disposed between the transfer gate 125 and 3_n. Transfer gates 124, 12
Each gate of 5 is commonly connected to the word line 18_m.

In the comparison unit 130, each gate has a latch circuit 1.
23. NMOS transistors 131 and 133 connected to both ends of 23 and drains of which are connected to the match line 14_m, and NMOS transistors 131 and 13
3 and the ground GND, and NMOS transistors 132 and 134 arranged between them. NMO
The gates of the S transistors 132 and 134 are connected to the inverted bit line 13_nN and the bit line 13_n.

The standby state of the associative memory 100 including the CAM cells 110, the normal data read operation, the normal data write operation, and the search operation when the search data is input are performed as follows. Be done.

In the standby state, the word line signal WL <m> of the word line 18_m and the match line signal ML <m> of the match line 14_m are both at the'L 'level. The bit line pair 13_n, 13_nN is the bit line control circuit 12
The bit line pair signals BL <n> and BLN <n> have been precharged in advance (see FIG. 4), and therefore are at the power supply potential. The match line 14_m is also precharged by a circuit (not shown) in advance, so that the match line signal ML <m> is also at the power supply potential.

In a normal data read operation, the address ADR of the desired word memory is input to the decoder 17 and decoded, and the word line signal WL <m> of the word line 18_m shown in FIG. It becomes H'level. Then, the transfer gates 124 and 125 in the word memory are both turned on, and the data stored in the word memory, that is, the latch circuit 12 is turned on.
Complementary data on both ends of the three transfer gates 124, 12
5 is transmitted to the bit line pair 13_n, 13_nN. At this time, a minute difference voltage signal according to the logic of complementary data at both ends of the latch circuit 123 is output to the bit line pair 13_n, 13_nN that has been precharged in advance, and is amplified by a sense amplifier (not shown) to obtain a desired word. The data in the memory is read.

In a normal data write operation, the address ADR is input to the decoder 17 and the write data DATA is input to the bit line control circuit 12.
This causes the word line signal WL <m of the word line 18_m.
>Becomes'H'level and bit line control circuit 1
2 bit line pair 13_ according to write data DATA
One of the signals BL <n> and BLN <n> of n, 13_nN is set to the “H” level, and the other is set to the “L” level. Here, since the transfer gates 124 and 125 are both turned on, the transfer gate 1
A signal B of which either one is at the “H” level and the other is at the “L” level at both ends of the latch circuit 123 via 24 and 125.
L <n> and BLN <n> are applied. In this way, the write data is latched by the latch circuit 123 and stored in the desired word memory. The search operation will be described with reference to FIG.

FIG. 6 is a diagram showing timings in the search operation of the associative memory shown in FIG.

Here, the storage unit 1 shown in FIG. 5 in advance.
It is assumed that data is written (stored) in 20. The procedure of the search operation will be described below.

First, in the first precharge period, the word line signal WL <m> of the word line 18_m, the bit line pair 1
The signals BL <n> and BLN <n> of the 3_n and 13_nN are set to the “L” level state. Also, the match line 14_
m is precharged, so that the match line signal ML <m
>Becomes'H'level.

Next. During the comparison operation period, the search data DATA is input to the bit line control circuit 12. As a result, the signals BL <n> and BLN <n of the bit line pairs 13_n and 13_nN are input according to the input search data DATA.
> Becomes one of the “H” levels and the other becomes the “L” level. Here, it is assumed that the inverted bit line signal BLN <n> is at the “H” level and the bit line BL <n> is at the “L” level.

Here, for example, the node A in FIG.
When it is at the level, the inversion bit line BLN <n> is also at the “H” level.
1, 132 are both turned on, and the match line signal ML <m
> Is withdrawn from the “H” level to the “L” level.
In this case, it is determined that the search data DATA and the stored data do not match. The above is the search operation of one cycle.

Conversely, the node A is at the "H" level, the bit line signal BL <n> is at the "H" level, and the inverted bit line signal B is
When LN <n> is at the “L” level, N in FIG.
The MOS transistors 132 and 133 are turned off,
The match line signal ML <m> remains at the “H” level without being pulled down to the “L” level. In this case, it is determined that the search data DATA and the stored data match. This'H 'level match line signal ML <m> is
It is input to the coincidence detection circuit 15 and is output to the outside as a coincidence detection signal MT <m>of'H'level after a lapse of a predetermined time.

The above search operation is applied to the CAM cell array 11 having a plurality (M) of word memories each having N bits as one word, so that the stored data and the search data in the word memory of N bits × 1 word are obtained. It is compared, and if there is a mismatch in even one bit, the match line signal ML <m> is dropped. On the contrary, the match line signal ML <m> is not dropped only when the stored data and the search data match in all the bits.

[0024]

The above-mentioned associative memory 1
In the CAM cell array 11 (N bits × M words) that configures 00, there are 2N bit lines and inverted bit lines that configure a bit line pair, and M match lines. Therefore, N bit lines are used during a search operation. (Or an inverted bit line) and M match lines have full amplitude. Associative memory 100
In the search operation of, the power consumption of these wirings occupies most of the total power consumption. In recent years, as the capacity of the associative memory has increased, the number of these wirings has also increased. Therefore, the power consumption of the associative memory tends to increase more and more, and the reduction of the power consumption in the search operation is a big issue.

Here, assuming that the capacity of one bit line (or inverted bit line) is Cbl and the capacity of one match line is Cml, the maximum charge amount that can be charged or discharged in one search operation. Qbl = Cbl × Vdd Qml = Cml × Vdd. In addition, Vdd is a power supply voltage, and corresponds to an'H 'level voltage for driving the capacitance of each wiring.

From the above equation, in order to reduce the power consumption, it is preferable to keep the wiring capacitance and the signal level amplitude small.

Therefore, first, the capacitance of the bit line will be considered. The bit line capacity is Cbl = Cmetal + Cdr
ain + Cgate. Here, Cmetal is the parasitic capacitance of the metal wiring, Cdrain is the total drain capacitance of the NMOS transistors (corresponding to the NMOS transistors 124 and 125 in FIG. 5) of the storage portion of the CAM cell, and Cgate is the NMOS of the comparison portion of the CAM cell. Transistor (NMOS transistors 132 and 13 in FIG. 5)
4) (corresponding to 4).

Here, by setting the potential at the time of the search operation of the bit line pair to be an intermediate potential between the power supply potential and the ground potential,
The applicant of the present application has filed a technique for reducing the power consumption by suppressing the amplitude of the voltage applied to the bit line pair (Japanese Patent Application No. 2001-11005). However, in this technique, the NMOS transistor (the NMOS in FIG.
It is difficult to completely turn on the transistors (132, 134), and therefore it takes time to drain the charges on the coincidence line, and there is a lack of speeding up. In addition, there is a technique of reducing the potential of the bit line pair by setting the bit line pair to the intermediate potential between the power supply potential and the intermediate potential in the search standby mode.
Since the MOS transistors 132 and 134 are in a semi-conductive state, it is difficult to precharge the match line sufficiently. Therefore, for example, in Japanese Unexamined Patent Publication No. 2-192098 or Japanese Unexamined Patent Publication No. 8-212791, the sources of the NMOS transistors 132 and 134 are connected to the control signal line instead of being connected to the ground GND, and this control is performed during the search operation. A technique for setting the signal line to the'L 'level has been proposed. With this technique, it is possible to precharge the match line while keeping the bit line pair at the intermediate potential during search standby. However, an NMOS transistor is required to bring the control signal line to the'L 'level, and this NMOS transistor is turned on during the search operation (comparison operation period), so that the control signal line and the match line are in a short circuit state. Becomes For this reason, it is necessary to perform the bridging in consideration of the parasitic capacitance of the control signal line in addition to the parasitic capacitance of the match line. Therefore, the parasitic capacitance to be charged increases, which causes a problem of increasing power consumption. Further, in the search operation, the charge on the match line is drawn through the NMOS transistor, so that the parasitic capacitance of the NMOS transistor is also added, which is compared with the case where the sources of the NMOS transistors 132 and 134 are directly connected to the ground GND. And it takes time to withdraw,
Therefore, there is also a problem that speeding up is lacking.

As another technique for solving the problem of match line bridging, there is known a technique of driving a match line after driving a bit line pair. However, with this technique, it is difficult to quickly raise the match line that is pulled down to the'L 'level when the stored data and the search data do not match to the'H' level. Therefore, it is necessary to consider that the match detection circuit detects the potential of the match line at a predetermined timing from the start of the search. However, for example, in the precharge circuit disclosed in Japanese Patent Laid-Open No. 2-192098,
The potential of the match line is different due to the balance between the gate width of the PMOS transistor forming the precharge circuit and the total gate width of the NMOS transistors forming the match detection circuit in the ON state. In other words, since the potential of the match line after the drop is different each time depending on how many bits do not match, it is difficult to detect whether the stored data and the search data match. Further, in the case of a configuration in which the PMOS transistor forming the bridging circuit and the NMOS transistor forming the coincidence detection circuit are turned on at the same time, a through current flows from the power supply to the ground, which causes a problem of increasing power consumption.

In view of the above situation, it is an object of the present invention to provide an associative memory device which has a high speed operation and a low power consumption.

[0031]

An associative memory of the present invention which achieves the above object is provided with a plurality of word memories for storing storage data for one word and spans corresponding bit cells of the plurality of word memories. Corresponding to the search data on the bit line pair based on the potential of the match line in the state where the search data is applied to the bit line pair, the bit line pair extending and the match line corresponding to each word memory. In a content addressable memory that detects a word memory in which stored data is stored, a bit line pair control unit that applies search data to the bit line pair during a search operation, and a search to the bit line pair by the bit line pair control unit At the timing of starting the application of data, the match line is placed in a discharged state, and then a match line control unit for injecting a predetermined amount of charge into the match line, A coincidence detection unit that detects a word memory in which stored data corresponding to search data on the bit line pair is stored, based on the potential of the coincidence line after the predetermined amount of charge is injected by the bias line control unit. It is characterized by having and.

According to the present invention, the match line is placed in a discharged state at the timing of starting the application of the search data, and then the search data on the bit line pair is selected based on the potential of the match line into which a predetermined amount of charge has been injected. Since it detects the word memory in which the corresponding stored data is stored, it is sufficient to inject into the match line a charge amount of a potential large enough to detect a match / mismatch in the match detection unit, reducing power consumption. be able to. Further, since such an amount of electric charge is injected into the coincidence line, the electric charge can be quickly removed in the non-coincidence state, and the speed can be increased.

Here, it is preferable that the match line control section charges a predetermined capacity prior to the search operation, and causes the charge charged in the capacity during the search operation to flow out to the match line.

By doing so, the circuit configuration of the match line control unit for injecting a predetermined amount of charges into the match line can be easily realized.

Further, the bit line pair control unit short-circuits the two bit lines forming the bit line pair with each other and holds them at an intermediate potential prior to the search operation, and at the time of the search operation, two bit lines are controlled. It is also a preferable aspect to set the bit line from the intermediate potential to a potential according to the search data.

The present invention also relates to a read bit line pair for writing the stored data in the word memory and for reading the stored data stored in the word memory, and a search bit for applying the search data. The line pairs may be arranged independently of each other.

Further, the bit line pair control section short-circuits the two search bit lines forming the search bit line pair to each other to hold them at an intermediate potential prior to the search operation, and at the time of the search operation. , These two search bit lines,
It is also a preferred embodiment that the intermediate potential is set to a potential according to the search data.

As described above, when the reading bit line pair and the search bit line pair are independently arranged, and the search bit line pair is held at the intermediate potential and set to the potential according to the search data, The capacity of the bit line pair can be small, and the charge amount in the search bit line pair can be small. Therefore, the power consumption in the search operation can be further reduced.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a circuit block diagram of an associative memory according to an embodiment of the present invention.

The same components as those of the associative memory 100 described above are designated by the same reference numerals.

In the associative memory 1 shown in FIG. 1, the storage unit 120 in which the stored data is written and the stored data is read out as in a normal semiconductor memory, and the stored data in the storage unit 120 is compared with the search data. A large number of CAM cells 110 each including a comparison unit 130 are provided. The configuration of the CAM cell 110 is the same as the configuration of the CAM cell 110 shown in FIG. 5 described above except that the reading bit line pair and the search bit line pair are arranged independently of each other. The description is omitted.

In the present embodiment, the reading bit line pair and the search bit line pair are provided independently of each other, but the present invention is applied even when they are not independent but shared by a pair of bit lines. It goes without saying that you can do it.

The associative memory 1 has a plurality of CAM cells 11
Reading bit line pair 13_n, 13_nN for writing stored data to the word memory consisting of 0 and reading stored data stored in the word memory, search data ID <n>, search inverted data IDN <n> The search bit line pair 33_n and 33_nN for applying the voltage are provided independently of each other. Reading bit line pair 13_n,
13_nN is a bit line pair signal B having different levels.
L, BLN are transmitted. Also, the search bit line pair 33_
n and 33_nN are search data I whose levels are different from each other.
The search bit line pair signals KD <n> and KDN <n> represented by D <n> and search inversion data IDN <n> are transmitted.

Further, the associative memory 1 is provided with a bit line pair control section 20. This bit line pair control unit 20
Is a PMOS transistor 21_ arranged in series between the NAND gate 21_1, the NOR gate 21_2, the OR gate 21_3, and the power supply Vdd and the ground GND.
4, a set of NMOS transistors 21_5, a NAND gate 22_1, a NOR gate 22_2, and an OR gate 22_3.
And a transfer gate 23 and a set of a PMOS transistor 22_4 and an NMOS transistor 22_5 arranged in series between the power supply Vdd and the ground GND.

NAND gate 21_1, NOR gate 21_
2 and NAND gates 22_1 and NOR gates 22_2 have search data I at different levels during the search operation.
D (n) and search inversion data IDN (n) are applied. Further, the comparison signal KDDR and the comparison inverted signal KDDRN having different levels are input to the NAND gates 21_1 and 22_1 and the NOR gates 21_2 and 22_2. Further, the search control signal KDDC is input to the OR gates 21_3 and 22_3, and the search equalize signal KDEQ is input to the transfer gate 23. The role of these signals will be described later,
Prior to the search operation, the bit line pair control unit 20 short-circuits the two search bit lines forming the search bit line pair 33_n, 33_nN by the transfer gate 23 upon receiving the search equalize signal KDEQ. Are held at the intermediate potential, and at the time of the search operation, those two search bit lines are searched for from the intermediate potential to the search data ID <n.
>, Search inversion data IDN <n>. .

In the associative memory 1, the search bit line signal KD <n> and the search inverted bit line signal KDN <n> to the search bit line pair 33_n, 33_nN by the bit line pair control unit 20. Represented search data ID <n
>, The matching lines 14_0, ..., 14_m, 14_m + 1 are placed in a discharged state at the timing of starting the application of the search inversion data IDN <n>, and then the matching lines 14_0 ,.
A match line control unit 30 for injecting a predetermined amount of charges into 4_m and 14_m + 1 is provided. Although the configuration of the match line control unit 30 will be described later, the match line control unit 30 charges a predetermined capacity prior to the search operation, and charges the charges charged in the capacity during the search operation to the match lines 14_0, ..., 14_
m, 14_m + 1.

Further, in the associative memory 1, the match line 14_ after the match line controller 30 injects a predetermined amount of charges.
A match detection unit 40 is provided for detecting a word memory in which stored data corresponding to search data on the search bit line pair 33_n, 33_nN is stored based on the potentials of 0, ..., 14_m, 14_m + 1.

FIG. 2 is a diagram showing a circuit configuration of the coincidence line control unit shown in FIG.

The match line control unit 30 has a PMOS transistor 31 whose source is connected to the power supply Vdd and whose gate receives the match line precharge signal MPCN.
A capacitor 32 arranged between the drain of the PMOS transistor 31 and the ground GND; a transfer gate 333 having one end connected to the drain of the PMOS transistor 31 and a match line equalize signal MEQ input to the gate; An NMOS transistor 34 arranged between the other end of the transfer gate 333 and the ground GND is provided. Less than,
A search operation in the associative memory 1 of this embodiment will be described with reference to FIGS. 1, 2, and 3.

FIG. 3 is a timing chart in the search operation of the associative memory shown in FIG.

In the associative memory 1, first, a search standby operation is performed. Here, before the search standby operation, a comparison operation to be described later is performed in advance, and one of the search bit line 33_n and the search inverted bit line 33_nN is at the power supply potential and the other is at the ground potential. And In the search standby operation, search data DATA is input to a circuit portion (not shown) of the bit line pair control unit 20. Bit line pair control unit 2
In 0, the search data ID <n> of the “H” level having different levels from each other is received in response to the data DATA.
And the inverted search data IDN <n> of the “L” level are generated and input to the NAND gates 21_1 and NOR gates 21_2 and the NAND gates 22_1 and 22_2. Further, the NAND gates 21_1 and 22_1 and the NOR gates 21_2 and 22_2 are input with the comparison signal KDDR of the “L” level and the inverted comparison signal KDDRN of the “H” level which are different from each other. Further, the OR gates 21_3 and 22_3 are supplied with the search control signal KDDC of the “L” level indicating that the search operation is being performed. Further, the search gate equalize signal KDEQ at the “H” level is input to the transfer gate 23.

Since the NAND gate 21_1 receives the'L 'level comparison signal KDDR, the gate of the PMOS transistor 21_4 becomes'H' level, and the P
The MOS transistor 21_4 is turned off. Also,
The'L 'level search control signal KDDC is input to one of the OR gates 21_3. Also, Nand Gate 21
Since the search data ID <n> of the “H” level and the inversion signal for comparison KDDRN are both input to _2, the signal of the “L” level is also input to the other of the OR gates 21_3. Therefore, the “L” level signal is output from the OR gate 21_3, and the NMOS transistor 21_5 is turned off. On the other hand, PMOS transistors 22_4 and NM
Similarly, the OS transistors 22_5 are both turned off. The transfer gate 23 is supplied with the search equalize signal KDEQ at the “H” level. Therefore, the transfer gate 23 is turned on, which causes the search bit line 33_n and the search inverted bit line 33_nN.
Are short-circuited to each other and are equalized to an intermediate potential between the power supply potential and the ground potential.

Furthermore, the transfer gate 3 shown in FIG.
Matching line equalize signal M of'L 'level to the gate of 33
Since the EQ is input, the transfer gate 333 is turned off. In addition, the PMOS transistor 31, NM
The “L” level match line precharge signal MPCN and the “H” level match line discharge signal MDC are input to the respective gates of the OS transistor 34.
Both the S transistor 31 and the NMOS transistor 34 are turned on. Since the PMOS transistor 31 is turned on, the capacitor 32 is charged with the electric charge from the power supply Vdd via the PMOS transistor 31.
Further, since the NMOS transistor 34 is turned on, the charge on the match line 14_m is discharged to the ground GND, and the match line signal ML <m> becomes the “L” level. Furthermore, in the standby operation, the data DATA
In response to the change of "H" level search data ID <n>
And the'L 'level search inverted data IDN <n> are inverted from each other to generate'L' level search data ID <n>and'H'level search inverted data IDN <n>. In such a state, the comparison operation is performed.

First, the comparison operation when the search data and the stored data do not match will be described. In this comparison operation, the search data ID <n> of the “L” level and the search inverted data IDN <n> of the “H” level are input to the NAND gate 21_1, the NOR gate 21_2 and the NAND gates 22_1 and 22_2, and the NAND gate 21_1 is input. , 22_1 and NOR gate 21_
2, 22_2 is supplied with the comparison signal KDDR of the “H” level and the inverted signal KDDRN of the comparison of the “L” level. Further, the search gate equalize signal KDEQ of'L 'level is input to the transfer gate 23. The NAND gate 21_1 has an “L” level search data ID <
Since n> is input, the PMOS transistor 21_4
, The gate of the PMOS transistor 21_4 remains at the “H” level, and the PMOS transistor 21_4 is maintained in the off state. Further, both of the NOR gates 21_2 have'L 'level search data I.
Since D <n> and the inverted signal for comparison KDDRN are input, the gate of the NMOS transistor 21_5 becomes the “H” level, and the NMOS transistor 21_5 is turned on. On the other hand, since the NAND gate 22_1 receives the search inverted data IDN <n> of the “H” level and the comparison signal KDDR, the PMOS transistor 2
The gate of 2_4 becomes “L” level, and the PMOS transistor 22_4 is turned on. In addition, the NOR gate 22_2 has the'H 'level search inverted data IDN <
Since n> is input, the NMOS transistor 22_5
Of the NMOS transistor 21_5 remains at the “L” level, and the NMOS transistor 21_5 is maintained in the off state. here,
Since the transfer gate 23 is supplied with the search equalizing signal KDEQ at the “L” level, the transfer gate 23 is in the off state. Therefore, the search bit line signal KD <n> of the search bit line 33_n.
Becomes the ground GND potential (the potential shown by the solid line in FIG. 3), and the search inverted bit line signal KDN <n> potential of the search inverted bit line 33_nN becomes the power supply Vdd potential (the potential shown by the dotted line in FIG. 3).

Furthermore, the transfer gate 3 shown in FIG.
Since the'H 'level match line equalize signal MEQ is input to the gate of 33, the transfer gate 333 is turned on. Also, the PMOS transistors 31, N
Since the'H 'level match line precharge signal MPCN and the'L' level match line discharge signal MDC are input to the respective gates of the MOS transistor 34, PM
Both the OS transistor 31 and the NMOS transistor 34 are turned off. Since the PMOS transistor 31 is turned off, the charging (supply of electric charge) from the power supply Vdd to the capacitor 32 is stopped. Further, since the NMOS transistor 34 is turned off and the transfer gate 333 is turned on, the charge charged in the capacitor 32 is discharged to the match line 14_m.
Then, as shown in FIG. 3, the level of the match line signal ML <m> of the match line 14_m starts to rise. However, since the search data and the stored data do not match, at least one CAM cell in the word memory pulls the match line to the ground, so that the potential rise is suppressed.
Here, the potential of the match line 14_m is different each time depending on how many bits do not match, and the reference potential VR described later is used.
Although the potential may be higher than that, the capacitor 32
Only the amount of the predetermined charge that has been charged to the matching line 14
Since it flows out to _m, the voltage higher than the potential VR is not maintained here for a predetermined period of time, so that the coincidence output signal MT <m> becomes the “L” level. In this way, the search operation for one cycle is completed.

Next, the one-cycle search operation including the comparison operation when the search data and the stored data match will be described. In this case, 'H' level search data ID
<N>and'L'level search inversion data IDN <n
> Is generated. Then, this time, the search bit line 33
The search bit line signal KD <n> of _n is the power supply potential (see FIG.
Potential shown by the solid line), and the inverted bit line 33_ for search
The nN search inverted bit line signal KDN <n> potential becomes the ground GND potential (the potential shown by the dotted line in FIG. 3). Here, the charge charged in the capacitor 32 is equal to the match line 1
It is poured out to 4_m. Then, since all the bits match this time, the capacitor 32
When the electric charge charged to the match line 14_m flows out to the match line 14_m, the potential of the match line 14_m rises up to the charging voltage Vml determined by the ratio of the capacitance of the capacitor to the match line capacitance, and the potential Vml continues after a predetermined time. To do. Match detection unit 4
At 0, in response to this, the coincidence output signal MT of'H 'level
<M> is output.

In the present embodiment, the search bit line pair 33_n, 33_nN becomes an intermediate potential between the power supply Vdd potential and the ground GND potential by equalization during the search standby, and the search data ID <n>,
According to the search inversion data IDN <n>, one of the search bit line pairs 33_n and 33_nN becomes the power supply Vdd potential and the other becomes the ground GND potential. By doing so, the search bit line pair 33_n in the search operation,
33_nN voltage amplitude fluctuation can be suppressed small,
As a result, power consumption is reduced. Further, at the time of comparison operation, the NMOS transistor 13 that constitutes the comparison unit 130.
Since 2,134 are completely turned on, the match line 14_m is quickly pulled down in the mismatched state, and high speed is realized.

The transfer gate 23 is turned off during the comparison operation. Therefore, the search bit line 33
_N (or inverted bit line for search 33_nN) and the power supply Vdd, and the PMOS transistor 21_.
4 (or the PMOS transistor 22_4) or the search bit line 33_n (or the search inverted bit line 33_nN) and the ground GND.
The MOS transistor 21_5 (or the NMOS transistor 22_5) is turned on according to the search data ID <n> and the search inverted data IDN <n>, and the search bit line 33_n and the search inverted bit line 33_nN are respectively at the power supply Vdd potential or It is driven to the ground GND potential. Also, during the comparison operation, the search bit line pair 33_
The charge charged in one of n and 33_nN is charged in the other of the search bit line pair 33_n and 33_nN when the transfer gate 23 is turned on during the search standby. Therefore, no charges are exchanged with the power supply Vdd or the ground GND. Therefore, compared with the conventional associative memory, the search bit line signals KD <n> and KDN <n> are compared.
Of the search bit line pair 33_n, 3 while maintaining the amplitude of
The power consumption of 3_nN is 1/2.

By the way, when the search bit line pair 33_n, 33_nN has an intermediate potential during the search standby, the NMOS transistors 132, 13 forming the comparison section 130 are formed.
Since 4 is turned on, it is difficult to precharge the match line 14_m. Therefore, in the present embodiment, after the search bit line pair 33_n, 33_nN is driven, the matching line 14_m is charged by causing a predetermined charge to flow out by the capacitor 32, as described with reference to FIG. The match line control unit 30 may be provided either in the entire associative memory, in every several words, or in each word. . In each case, the capacitor 3 of the match line control unit 30
The capacitance value of 2 may be set appropriately. In this embodiment, each word is provided. Here, if the capacity of the match line 14_m per word is Cml and the amount of charge that charges the match line 14_m is Qml, the match line 14_m after charging is shown.
The potential Vml of is Vml = Qml / Cml. However, the comparison unit 1 forming the CAM cell 110
When 30 is in the non-coincidence state, the coincidence line 14_m is not charged to the potential Vml and does not maintain a voltage higher than the reference potential VR over a predetermined time.
Therefore, the match line output signal MT <m> becomes the ground level, as described above. By doing this, the power consumption per matching line is the amount of charge Q to be charged.
Since it is proportional to ml, power consumption can be reduced by appropriately setting the charge amount Qml. Furthermore, the magnitude of the charging potential Vml of the match line 14_m is determined by the match detection unit 4
If a match / mismatch can be detected with 0, it is not necessary to use the power supply voltage Vdd. Preferably, by setting the potential Vml to the intermediate potential, the time required for the voltage change of the match line 14_m can be shortened, and further speedup can be achieved. It will be possible.

Further, in the match line control unit 30 which is a circuit for precharging the match line 14_m shown in FIG. 2, as described above, the PMOS transistor 31 arranged between the power supply Vdd and the capacitor 32 in the search standby mode. Turns on and charges the capacitor 32. Further, during the comparison operation, the PMOS transistor 31 is turned off, and the transfer gate 333 arranged between the capacitor 32 and the match line 14_m is turned on, so that the charge charged in the capacitor 32 is placed on the match line 14_m. If the parasitic drain capacitance of the comparing unit 130 of the existing CAM cell 110 and the parasitic capacitance of the metal wiring of the match line 14_m itself are charged, and if the CAM cell 110 is found unmatched as a result of the search, it is passed through the NMOS transistor of the unmatched bit. Is discharged to the ground GND. Here, in designing the associative memory 1 of the present embodiment, by adjusting the capacitance ratio between the capacitance of the capacitor 32 and the total parasitic capacitance on the match line 14_m, the charging potential Vm of the match line 14_m is adjusted.
l can be set to a predetermined intermediate potential. In this way, the associative memory 1 of the present embodiment, in the search operation,
It is possible to reduce the power consumption of the search bit line pair while increasing the speed. Further, it is possible to reduce the power consumption of the coincidence line while increasing the speed.

The circuit configuration of the coincidence detecting section 40 in this embodiment has the coincidence lines 14_0, ..., 14_m, 14_m.
Any circuit configuration may be used as long as it is a circuit configuration that can distinguish the +1 charged potential and the dropped potential. For example, the reference potential VR and the coincidence line 14_ shown in FIG. 3 set between the potential Vml and the ground GND level.
A match line 14_0, ..., 14_m, 14 is provided with a comparator for comparing the potentials of 0, ..., 14_m, 14_m + 1.
_M + 1 is the reference potential VR at a predetermined timing
The circuit configuration may be such that when the potential is higher than the reference potential, it is determined that they match, and when the potential is lower than the reference potential VR, it is determined that they do not match.

[0063]

As described above, according to the associative memory of the present invention, it is possible to speed up the operation and reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an associative memory according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a match line control unit shown in FIG.

FIG. 3 is a timing chart in a search operation of the associative memory shown in FIG.

FIG. 4 is a circuit block diagram showing an example of a conventional associative memory.

5 is a diagram showing a circuit of one CAM cell forming the CAM cell array shown in FIG.

6 is a diagram showing timings in a search operation of the associative memory shown in FIG.

[Explanation of symbols]

1 associative memory 13_n, 13_nN reading bit line pair 14_0, ..., 14_m, 14_m + 1 match line 17_0, ..., 17_m, 17_m + 1 word line 20 bit line pair control unit 21_1, 22_1 NAND gate 21_2, 22_2 NOR gate 21_3, 22_3 OR gate 21_5, 22_5 , 34, 131, 132, 133
134 NMOS transistors 23, 333, 124, 125 Transfer gate 30 Match line control units 21_4, 22_4, 31 PMOS transistor 32 Capacitors 33_n, 33_nN Search bit line pair 40 Match detection unit 110 CAM cell 120 Storage unit 121, 122 Inverter 123 Latch Circuit 130 comparator

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Naoki Kanazawa             1-3 Nakase River, Mihama-ku, Chiba City, Chiba Prefecture             Inside Saki Microelectronics Co., Ltd.

Claims (5)

[Claims] 1. A plurality of word memories for storing one word of stored data, and a bit line pair extending across corresponding bit cells of the plurality of word memories,
A match line corresponding to each word memory is provided, and stored data corresponding to the search data on the bit line pair is stored based on the potential of the match line in a state where the search data is applied to the bit line pair. In an associative memory that detects a word memory, a bit line pair control unit that applies search data to the bit line pair during a search operation, and a timing of starting application of search data to the bit line pair by the bit line pair control unit Then, the match line is placed in a discharged state, and then a match line control unit that injects a predetermined amount of charge into the match line, and the match line after the predetermined amount of charge is injected by the match line control unit An associative memory that detects a word memory storing stored data corresponding to the search data on the bit line pair based on the potential of 2. The match line control unit charges a predetermined capacity prior to a search operation, and causes the charge charged in the capacitor during the search operation to flow out to the match line. An associative memory according to item 1. 3. The bit line pair control unit short-circuits two bit lines forming the bit line pair to hold an intermediate potential before the search operation and holds the two bit lines during the search operation. 3. The associative memory according to claim 1 or 2, wherein the bit line of is set to a potential corresponding to the search data from the intermediate potential. 4. A read bit line pair for writing stored data to the word memory and reading stored data stored in the word memory, and a search bit line pair for applying search data. 3. The associative memory according to claim 1, wherein the associative memories are arranged independently of each other. 5. The bit line pair control unit short-circuits the two search bit lines forming the search bit line pair to each other and holds them at an intermediate potential prior to the search operation.
The associative memory according to claim 4, wherein during the search operation, the two search bit lines are set to a potential corresponding to the search data from the intermediate potential.