JP2007288419A - Oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillator which is capable of obtaining an oscillation output of high precision having less variance in oscillation period in spite of the variance in threshold voltage among MOS transistors during manufacturing. <P>SOLUTION: Each circuit comprises MOS transistors and includes a current source circuit 1, a capacitor 2, a first charging/discharging circuit 3, a second charging/discharging circuit 4, a first charge determination amplifier 5, a second charge determination amplifier 6, a delay inverter stage 7, a delay inverter stage 8, and a latch circuit 9. A current mirror relation is given between the current source circuit 1 and the charge determination amplifiers 5 and 6, and optimum values of both of them are obtained by using a preliminarily defined expression wherein m is the mirror ratio and K is conductivity factors of input MOS transistors constituting the charge determination amplifiers 5 and 6. When the oscillator is designed under these optimum values, the variance in threshold voltage among MOS transistors is compensated to reduce the fluctuation of the oscillation period during use though the variance in threshold voltage among the MOS transistors occurs during manufacturing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an oscillator used for clock generation and the like, and more particularly to an oscillator that can be stably manufactured when an integrated circuit is formed using a MOS transistor.

Conventionally, for example, an oscillator described in Patent Document 1 is known as an oscillator using an RS latch circuit.
The oscillator includes a capacitor, a current source circuit that generates a current for charging the capacitor, two charge / discharge circuits each configured to independently charge and discharge the capacitor, and a charge voltage of the capacitor. Two charge determination amplifiers that perform an output operation according to the determination, and a latch circuit that stores the outputs of the two charge determination amplifiers and controls the operation of the two charge / discharge circuits.

By the way, in such a conventional oscillator, when a CMOS inverter is used as a charge determination amplifier, the determination level depends on the threshold voltage, so that the oscillation period depends on the threshold voltage.
For this reason, when the output of the conventional oscillator is used as a clock for a delay counter for generating a delay time, there is a problem that the delay time varies due to variations in threshold voltage of the CMOS inverter.

In order to improve such a problem, it is possible to use a constant current drive type inverter instead of a CMOS inverter as a charge determination amplifier. In this case as well, the dependency of the determination level on the threshold voltage Therefore, the above problem cannot be solved.
US Pat. No. 3,702,446

  Therefore, in view of the above points, an object of the present invention is to obtain a highly accurate oscillation output in which variation in oscillation cycle is reduced even if there is variation due to manufacture of the threshold voltage of a MOS transistor. It is to provide an oscillator.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
That is, the first invention is an oscillator in which each circuit is configured by a MOS transistor, and includes a current source circuit that generates a reference current, a capacitor, and a charge current generated based on the reference current. A first charging / discharging circuit that performs charging and discharging of the capacitor; a second charging / discharging circuit that performs charging of the capacitor and discharging of the capacitor by a charging current generated based on the reference current; and A first charge determination amplifier that determines whether or not a charge voltage on one end side of the capacitor by the charge / discharge circuit is completed to a logical threshold value, and outputs a signal according to the determination; and the second charge / discharge circuit A second charge determination amplifier that determines whether or not the charge voltage on the other end of the capacitor has reached a logical threshold value, and outputs a signal according to the determination; A latch circuit that generates control signals for controlling charge / discharge operations of the first and second charge / discharge circuits based on both output signals of the second charge determination amplifier, and the first and second charge determination amplifiers. Each comprising a constant current drive type inverter including a first MOS transistor for input and a second MOS transistor for generating a bias current for driving the first MOS transistor, and the both charge determination amplifiers Are generated based on the reference currents generated by the current source circuits, and the bias currents of the reference current of the current source circuit 1 and the charge determination amplifiers are designed at the time of design. Optimum values for the mirror ratio m determined between the current and the conductivity coefficient K of the first MOS transistor for input are obtained in advance. Place was to constitute so that the respective values thus determined.

  According to a second invention, in the first invention, each value of the mirror ratio m and the conductivity coefficient K is defined in advance as a predetermined definition formula, and the threshold value of the first MOS transistor for input is set. A value satisfying the above definition formula was obtained under the range of voltage variation.

  A third invention is an oscillator in which each circuit is composed of MOS transistors, a current source circuit for generating a reference current, a first capacitor and a second capacitor, and a charging current generated based on the reference current A first charging / discharging circuit that charges the first capacitor and discharges the first capacitor, and charging the second capacitor with a charging current generated based on the reference current; and discharging the second capacitor A first charge / discharge circuit that performs a determination, determines whether the charge voltage of the first capacitor has been completed to a logical threshold value, and outputs a signal according to the determination; and the second charge determination amplifier It is determined whether or not the charging voltage of the capacitor is completed up to the logic threshold value, and both the first charging determination amplifier and the second charging determination amplifier that outputs a signal corresponding to the determination are output. And a latch circuit that generates control signals for controlling the charge / discharge operations of the first and second charge / discharge circuits based on the signal, respectively, and the first and second charge determination amplifiers include the first input amplifier Each of the constant current drive type inverters includes a MOS transistor and a second MOS transistor that generates a bias current for driving the first MOS transistor, and the bias currents for driving both the charge determination amplifiers are respectively The mirror ratio is generated based on the reference current generated by the current source circuit, and is determined between the reference current of the current source circuit 1 and the bias current of the charge determination amplifiers at the time of design. m and an optimum value for the conductivity coefficient K of the first MOS transistor for input are obtained in advance, and the obtained values are obtained. It was to be configured.

In a fourth aspect based on the third aspect, the mirror ratio m and the conductivity coefficient K are defined in advance as predetermined values for the threshold value of the first MOS transistor for input. A value satisfying the above definition formula was obtained under the range of voltage variation.
According to the present invention having such a configuration, even if there is a variation due to the manufacture of the threshold voltage of the MOS transistor, a highly accurate oscillation output in which the variation in the oscillation period is reduced can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
The configuration of the first embodiment of the oscillator of the present invention will be described with reference to FIG.
As shown in FIG. 1, the oscillator according to the first embodiment includes a current source circuit 1, a capacitor 2, a first charge / discharge circuit 3, a second charge / discharge circuit 4, and a first charge determination amplifier 5. , A second charging determination amplifier 6, a delay inverter stage 7, a delay inverter stage 8, and a latch circuit 9.

Further, in the first embodiment, each circuit as described above is composed of MOS transistors, and the MOS transistors are integrated on the same substrate.
Here, prior to the description of the first embodiment of the present invention, the basic concept of the present invention will be described.
When an oscillator like the present invention is composed of MOS transistors, if there is a variation in the threshold voltage of the MOS transistor, there is a problem that the oscillation period varies when the oscillator is mass-produced. It is difficult to deal with it in terms of cost.

However, when mass-producing oscillators, MOS transistors are integrated on the same substrate. For this reason, if the threshold voltage varies among the plurality of MOS transistors integrated into the integrated circuit, it is considered that the same tendency varies, and it is preferable to solve this variation uniformly.
Therefore, in the present invention, a current mirror relationship is provided between the current source circuit 1 and the charge determination amplifiers 5 and 6, the mirror ratio is m, and the conductivity coefficient of the input MOS transistor constituting the charge / discharge determination amplifier is If the optimum value of both is obtained using K and a design is made under the obtained optimum value, even if there is a variation in the threshold voltage of the MOS transistor at the time of manufacture, the variation will be caused at the time of use. It has been found that the fluctuation of the oscillation period becomes small after compensation.

Next, a schematic configuration of the first embodiment will be described with reference to FIG.
The current source circuit 1 is a circuit that generates a reference current Iref that serves as a reference for a charging current Ic for the first charging / discharging circuit 3 and the second charging / discharging circuit 4 to charge the capacitor 2, and the reference current Iref is The bias voltage VB supplied to the bias terminal 11 can be variably or arbitrarily set from the outside.

The current source circuit 1 generates a reference current Iref that serves as a reference for the bias current Ij that drives the first charge determination amplifier 5 and the second charge determination amplifier 6.
The first charging / discharging circuit 3 charges and discharges the capacitor 2. The second charging / discharging circuit 4 performs charging / discharging of the capacitor 2, and its charging / discharging operation is exclusive with the charging / discharging operation by the first charging / discharging circuit 3 and does not overlap.

  The first charging determination amplifier 5 determines whether or not the charging voltage on one end side of the capacitor 2 by the first charging / discharging circuit 3 is completed to the logical threshold value, and outputs a signal corresponding to this determination. ing. The second charging determination amplifier 6 determines whether or not the charging voltage on the other end side of the capacitor 2 by the second charging / discharging circuit 4 is completed up to the logical threshold value, and outputs a signal according to this determination. It has become.

The first charge determination amplifier 5 and the second charge determination amplifier 6 are each composed of a constant current drive type inverter including an input MOS transistor and a MOS transistor functioning as a current source and a load.
The delay inverter stage 7 delays the output signal of the first charge determination amplifier 5 for a predetermined time, and includes, for example, three stages of inverters 71 to 73 and an AND gate 74. The delay inverter stage 8 delays the output signal of the second charge determination amplifier 6 for a predetermined time, and is composed of, for example, three stages of inverters 81 to 83. Here, the AND gate 74 is for avoiding the prohibition input of the latch circuit 9.

  The latch circuit 9 includes an RS latch circuit in which two NOR gates 91 and 92 are connected to each other. The latch circuit 9 is a signal obtained by delaying the output signal of the first charge determination amplifier 5 by the delay inverter stage 7 and a signal obtained by delaying the output signal of the second charge determination amplifier 6 by the delay inverter stage 8. Based on this, an oscillation output signal OUT is generated at the output terminal 12, and a control signal for controlling the charge / discharge operation of the first charge / discharge circuit 3 and the second charge / discharge circuit 4 is generated.

  In the first embodiment, the charging current Ic (Ic = n × Iref) for charging the capacitor 2 by each of the first and second charging / discharging circuits 3 and 4 based on the reference current Iref generated by the current source circuit 1. ) And a bias current Ij (Ij = m × Iref) for driving the first and second charge determination amplifiers 5 and 6, respectively. Here, n and m are current mirror ratios, respectively.

Therefore, the MOS transistor PE8 of the current source circuit 1 forms a current mirror circuit with the MOS transistor PE1, MOS transistor PE3, MOS transistor PE4, and MOS transistor PE6.
Furthermore, in the first embodiment, as will be described later, the optimum value is set for the mirror ratio m and the conduction coefficient K of the input MOS transistors of the charge / discharge determination amplifiers 4 and 5 by using a predefined equation. The design is made under the optimum value obtained.

Next, a specific configuration of each circuit of the first embodiment will be described with reference to FIG.
The current source circuit 1 includes P-type MOS transistors PE7 and PE8 that constitute a current mirror circuit, N-type MOS transistors NE5 and NE6, and a resistor R1.
The sources and substrate terminals of the MOS transistors PE7 and PE8 are commonly connected, and the common connection portion is connected to the power supply terminal 10 so that the power supply voltage VDD is supplied. The gate of the MOS transistor PE8 is connected to its own drain and to the gate of the MOS transistor PE7.

  The drain of the MOS transistor PE7 is grounded through the MOS transistor NE5. The drain of the MOS transistor PE8 is grounded through the MOS transistor NE6 and the resistor R1. The gate of the MOS transistor NE5 is connected to the source of the MOS transistor NE6, and the gate of the MOS transistor NE6 is connected to the drain of the MOS transistor NE5. Further, the substrate terminals of the MOS transistors NE5 and NE6 are grounded.

The first charging / discharging circuit 3 includes a P-type MOS transistor PE2 and an N-type MOS transistor NE3 that constitute a CMOS inverter, and a P-type MOS transistor PE1 that functions as a current source for the CMOS inverter.
The MOS transistor PE1 forms a current mirror circuit with the MOS transistor PE8 in order to obtain a charging current Ic that is n times the reference current Iref flowing in the MOS transistor PE8 of the current source circuit 1.

  More specifically, the gates of the MOS transistors PE2 and NE3 are commonly connected, and the common connection portion is connected to the output terminal of the NOR gate 91 and to one input terminal of the NOR gate 92. The drains of the MOS transistors PE2 and NE3 are connected in common, and the common connection is connected to one end of the capacitor 2 and to the gate of the MOS transistor NE4 of the first charge determination amplifier 5.

The source and substrate terminal of the MOS transistor NE3 are each grounded. The source of the MOS transistor PE2 is connected to the drain of the MOS transistor PE1. The substrate terminal of the MOS transistor PE2 is connected to the power supply terminal 10 so that the power supply voltage VDD is supplied.
The gate of the MOS transistor PE1 is connected to the gate and drain of the MOS transistor PE8 of the current source circuit 1. The source and substrate terminal of the MOS transistor PE1 are connected in common, and the common connection portion is connected to the power supply terminal 10 so that the power supply voltage VDD is supplied.

The second charging / discharging circuit 4 includes a P-type MOS transistor PE5 and an N-type MOS transistor NE2 that constitute a CMOS inverter, and a P-type MOS transistor PE4 that functions as a current source for the CMOS inverter.
The MOS transistor PE4 forms a current mirror circuit with the MOS transistor PE8 in order to obtain a charging current Ic that is n times the reference current Iref flowing in the MOS transistor PE8 of the current source circuit 1.

  More specifically, the gates of the MOS transistors PE5 and NE2 are connected in common, and the common connection is connected to one input terminal of the NOR gate 91 and to the output terminal of the NOR gate 92. The drains of the MOS transistors PE5 and NE2 are connected in common, and the common connection is connected to the other end of the capacitor 2 and to the gate of the MOS transistor NE1 of the second charge determination amplifier 6.

The source and substrate terminal of the MOS transistor NE2 are grounded. The source of the MOS transistor PE5 is connected to the drain of the MOS transistor PE4. The substrate terminal of the MOS transistor PE5 is connected to the power supply terminal 10 so that the power supply voltage VDD is supplied.
The gate of the MOS transistor PE4 is connected to the gate and drain of the MOS transistor PE8 of the current source circuit 1. The source and substrate terminal of the MOS transistor PE4 are connected in common, and the common connection portion is connected to the power supply terminal 10 so that the power supply voltage VDD is supplied.

The first charge determination amplifier 5 is composed of a constant current drive type inverter composed of an N-type MOS transistor NE4 for input and a P-type MOS transistor PE3 that functions as a load and a current source.
The MOS transistor PE3 forms a current mirror circuit with the MOS transistor PE8 in order to obtain a bias current Ij that is m times the reference current Iref flowing in the MOS transistor PE8 of the current source circuit 1.

  More specifically, a voltage on one end side of the capacitor 2 is applied to the gate of the MOS transistor NE4. The source and substrate terminal of the MOS transistor NE4 are each grounded. The drain of the MOS transistor NE4 is connected to the drain of the MOS transistor PE3 and to the input terminal of the inverter 71.

  The gate of the MOS transistor PE3 is connected to the gate and drain of the MOS transistor PE8 of the current source circuit 1. The source and substrate terminal of the MOS transistor PE3 are connected in common, and the common connection portion is connected to the power supply terminal 10 so that the power supply voltage VDD is supplied.

The second charge determination amplifier 6 is composed of a constant current drive type inverter composed of an N-type MOS transistor NE1 for input and a P-type MOS transistor PE6 that functions as a load and a current source.
The MOS transistor PE6 forms a current mirror circuit with the MOS transistor PE8 in order to obtain a bias current Ij that is m times the reference current Iref flowing in the MOS transistor PE8 of the current source circuit 1.

  More specifically, the voltage on the other end side of the capacitor 2 is applied to the gate of the MOS transistor NE1. The source and substrate terminal of the MOS transistor NE1 are grounded. The drain of the MOS transistor NE1 is connected to the drain of the MOS transistor PE6 and to the input terminal of the inverter 81.

  The gate of the MOS transistor PE6 is connected to the gate and drain of the MOS transistor PE8 of the current source circuit 1. The source and substrate terminal of the MOS transistor PE6 are connected in common, and the common connection portion is connected to the power supply terminal 10 so that the power supply voltage VDD is supplied.

Next, an operation example of the first embodiment having such a configuration will be described with reference to FIG. 1 and FIG.
Now, for example, when the output of the NOR gate 91 is at L level, the input signal of the CMOS inverter of the first charge / discharge circuit 3 is at L level, so that the MOS transistor PE2 is turned on and the MOS transistor NE3 is turned off. is there.

At this time, since the output of the NOR gate 92 is at the H level, the input signal of the CMOS inverter of the second charge / discharge circuit 4 is at the H level, and the MOS transistor PE5 is turned off and the MOS transistor NE2 is turned on.
For this reason, when the output of the NOR gate 91 is L level, one end side 21 of the capacitor 2 is connected to the MOS transistor PE1 which is a current source, and the other end side 22 of the capacitor 2 is connected to the ground. For this reason, the capacitor 2 is charged by the first charging / discharging circuit 3. Therefore, at this time, the terminal voltage V1 on one end side of the capacitor 2 increases linearly as shown by the solid line in FIG. On the other hand, the terminal voltage V2 on the other end side of the capacitor 2 maintains 0 [V] as shown by a broken line in FIG.

Thereafter, when the terminal voltage V1 of the capacitor 2 reaches the logic threshold value VT of the first charge determination amplifier 3, the output of the MOS transistor NE4 is inverted from the L level to the H level. As a result, the output of the NOR gate 92 changes from H level to L level, and the output of the NOR gate 91 changes from L level to H level.
For this reason, the input signal of the CMOS inverter of the first charge / discharge circuit 3 changes from the L level to the H level, so that the MOS transistor PE2 is turned off and the MOS transistor NE3 is turned on. On the other hand, since the input signal of the CMOS inverter of the second charge / discharge circuit 4 changes from the H level to the L level, the MOS transistor PE5 is turned on and the MOS transistor NE2 is turned off.

As a result, the terminal voltage V1 of the capacitor 2 suddenly changes from the threshold voltage VT to 0 [V], while the terminal voltage V2 of the capacitor 2 suddenly decreases from 0 [V] of the ground potential to -VT [V]. (FIG. 2).
Then, charging of the capacitor 2 is started by the second charge / discharge circuit 4 from -VT [V]. At this time, the terminal voltage V2 of the capacitor 2 increases linearly as shown in FIG. On the other hand, the terminal voltage V1 of the capacitor 2 is maintained at 0 [V] as shown in FIG.

Thereafter, when the voltage V2 on the other end side of the capacitor 2 reaches the logic threshold value VT of the second charge determination amplifier 4, the output of the MOS transistor NE1 is inverted from the L level to the H level. As a result, the output of the NOR gate 92 changes from the L level to the H level, and the output of the NOR gate 91 changes from the H level to the L level.
By repeating such a series of operations, a pulse having a desired cycle is output from the output terminal 12.

Next, the design method of the first embodiment will be described.
In the first embodiment, if the proportionality constant is k between the logical threshold value VT of the charge determination amplifiers 5 and 6 and the reference current Iref generated by the current source circuit 1, the following equation (1) In this way, the proportional relationship is established in a first-order approximation.

  VT = k × Iref (1)

  Here, when the oscillation period of the oscillator is T and the capacitance value of the capacitor 2 is C, the following equation (2) is established.

  n × Iref = C × (VT / T) (2)

Here, (n × Iref) on the left side is a charging current Ic flowing through the first charging / discharging circuit 3 or the second charging / discharging circuit 4, and n is a mirror ratio between the reference current Iref and the charging current Ic. It is.
When the oscillation period T of the oscillator is obtained using the equations (1) and (2), the following equation (3) is obtained.

  T = (C × k × Iref) / (n × Iref) = (k / n) × C (3)

According to the equation (3), the first order approximation is established. Further, according to the equation (3), it can be seen that in order to increase the oscillation period T, the mirror ratio n should be decreased or the capacitance value C of the capacitor 2 should be increased.
Here, the proportionality constant k in the equation (3) can be approximated by the resistance value r when the resistance value r of the resistor R1 used in the current source circuit 1 is sufficiently large, for example, when it is several hundred KΩ or more, The formula (3) becomes the following formula (4).

  T≈C × (r / n) (4)

By the way, in the first embodiment, fluctuations in the oscillation period T of the oscillator due to variations in the threshold voltage Vthn of the input MOS transistors NE4 and NE1 of the charge determination amplifiers 5 and 6 are suppressed.
Therefore, in the first embodiment, the reference current Iref generated by the current source circuit 1 and the charge determination amplifiers 5 and 6 can be obtained as will be described later in order to deal with variations in the threshold voltage Vthn. Focusing on the logic threshold value VT, the D value is defined as in the following equation (5).

  Further, in the first embodiment, the D value defined by the equation (5) is approximately D = 1 under the range of variation of the threshold voltage Vthn of the input MOS transistors NE4 and NE1. , The mirror ratio m determined between the reference current Iref of the current source circuit 1 and the bias current Ij of the charge determination amplifiers 5 and 6, and the conduction coefficient K of the input MOS transistors NE4 and NE1 or the size ratio (W / L) ) Was determined for each optimum value, and the design was made using each of the determined values. Here, W is the channel width of the MOS transistor, and L is the channel length.

Specifically, the optimum value is obtained using a simulator. Since similar results are obtained by numerical analysis, it can be seen that this optimization does not depend on the model parameters of the MOS transistor.
In addition, it is confirmed by simulation that even if the resistance value r of the resistor R1 of the current source circuit 1, the oxide film thickness tox of the MOS transistor, and the mobility μn of carrier electrons fluctuate by several tens of percent, the optimization is hardly affected. We were able to. Furthermore, the influence of temperature is sufficiently small.

Next, the derivation of the reference current Iref of the current source circuit 1 defined by the equation (5) and the logic threshold value VT of the charge determination amplifiers 5 and 6 will be described.
In the current source circuit 1 shown in FIG. 1, if the MOS transistors PE7 and PE8 constituting the current mirror have the same size, the same current flows through the MOS transistors NE5 and NE6.

  Therefore, the MOS transistor NE5 operates in the saturation region, and the reference current Iref that is the operating current can be expressed by the following equation (6).

Here, r in the equation is the resistance value of the resistor R1, Ko is the conductivity coefficient (transconductance coefficient) of the MOS transistor, and Vthn is the threshold voltage of the MOS transistor.
When the equation (6) is solved for Iref, the following equation (7) is obtained.

Further, as the bias current Ij that is the operating current of the MOS transistors NE4 and NE1 of the charge determination amplifiers 5 and 6, a mirror current obtained by multiplying the reference current Iref of the current source circuit 1 by m flows.
Therefore, since the saturation threshold voltage when the bias current Ij of the MOS transistors NE4 and NE1 becomes the mirror current is an approximation of the logical threshold value VT of the charge determination amplifiers 5 and 6, the following equation (8) is obtained. To establish.

  When the logical threshold value VT of the charge determination circuit is obtained with respect to the equation (8), the following equation (9) is obtained.

  Here, if the equations (7) and (9) are used, detailed deformation of the equation is not shown, but K / m = ρ is rewritten as a variable, and the equation (5) can be expressed as a function of ρ. it can. In this case, the optimal ρ for setting D = 1 can be confirmed by numerical analysis with the horizontal axis being ρ and the vertical axis being D.

For simplicity, when r >> 1 and ρ = K / m >> 1 are established for the resistance value r and the variable ρ, the expression (1) is approximately calculated from the expressions (7) and (9). Is guided.
Based on these results, in the first embodiment, when an integrated circuit is formed using MOS transistors, variations in the threshold voltage of the MOS transistors occur as long as the device is manufactured with a device that minimizes the mismatch of elements on the layout. An oscillation period T that is not affected can be realized.

As described above, in the first embodiment, the current source circuit 1 and the charge determination amplifiers 5 and 6 have a current mirror relationship, the mirror ratio is m, and the charge / discharge determination amplifier is configured. The conduction coefficient of the input MOS transistor is set to K, and the optimum value of both is obtained by using a predefined formula.
For this reason, when designed under the optimum value obtained, even if there is a variation in the threshold voltage of the MOS transistor at the time of manufacture, the variation is compensated at the time of use and the fluctuation of the oscillation period becomes small. For example, even if the threshold value of the MOS transistor varies, the variation is compensated by the bias current flowing through the charge determination amplifiers 5 and 6.

(Second Embodiment)
The configuration of the second embodiment of the oscillator of the present invention will be described with reference to FIG.
In the first embodiment shown in FIG. 1, one capacitor 2 is configured, and both ends of the capacitor 2 are used as charging terminals. For this reason, when the terminal charged until then is rapidly discharged at the time of switching between charge and discharge, the ground level terminal on the opposite side cannot follow this, so it instantaneously drops to a level below ground.

  Therefore, in the second embodiment, the capacitor 2 is divided into two parts and the two capacitors are alternately charged and discharged in order to eliminate errors and problems caused by the lowering. Such a configuration is effective when there is no problem in matching capacitance values of capacitors and there is a sufficient layout area.

Therefore, in the second embodiment, as shown in FIG. 3, the current source circuit 11, the capacitor 2A and the capacitor 2B, the first charging / discharging circuit 13, the second charging / discharging circuit 14, and the first charging determination An amplifier 15, a second charge determination amplifier 16, a delay inverter stage 17, a delay inverter stage 18, and a latch circuit 19 are provided.
In the second embodiment, each circuit as described above is composed of MOS transistors, and the MOS transistors are integrated on the same substrate.

Next, a schematic configuration of the second embodiment will be described with reference to FIG.
The current source circuit 11 is a circuit that generates a reference current Iref that serves as a reference for the charging current Ic for the first charging / discharging circuit 13 and the second charging / discharging circuit 14 to charge the capacitors 2A and 2B, respectively. The current Iref can be set from the outside.
The current source circuit 11 generates a reference current Iref that serves as a reference for the bias current Ij that drives the first charge determination amplifier 15 and the second charge determination amplifier 16.

The first charge / discharge circuit 13 charges and discharges the capacitor 2A. The second charge / discharge circuit 14 charges and discharges the capacitor 2B.
The first charging determination amplifier 15 determines whether or not the charging voltage of the capacitor 2A by the first charging / discharging circuit 13 has been completed to the logical threshold value, and outputs a signal according to this determination. The second charging determination amplifier 16 determines whether or not the charging voltage of the capacitor 2B by the second charging / discharging circuit 14 is completed to the logical threshold value, and outputs a signal corresponding to this determination.

The first charge determination amplifier 15 and the second charge determination amplifier 16 are each composed of a constant current source drive type inverter including an input MOS transistor and a current source and a MOS transistor functioning as a load.
The delay inverter stage 17 delays the output signal of the first charge determination amplifier 15 for a predetermined time, and includes, for example, three stages of inverters 171 to 173 and an AND gate 174. The delay inverter stage 18 delays the output signal of the second charge determination amplifier 16 for a predetermined time, and includes, for example, three stages of inverters 181 to 183.

  The latch circuit 19 includes an RS latch circuit in which two NOR gates 191 and 192 are connected to each other. The latch circuit 19 is a signal obtained by delaying the output signal of the first charge determination amplifier 15 by the delay inverter stage 17 and a signal obtained by delaying the output signal of the second charge determination amplifier 16 by the delay inverter stage 18. Based on this, an oscillation output signal is generated, and a control signal for controlling the charging / discharging operation of the first charging / discharging circuit 13 and the second charging / discharging circuit 14 is generated.

In the second embodiment, based on the reference current Iref generated by the current source circuit 11, the first and second charge / discharge circuits 13 and 14 charge the capacitors 2A and 2B, respectively. × Iref) and a bias current Ij (Ij = m × Iref) for driving the first and second charge determination amplifiers 15 and 16, respectively, are generated. Here, n and m are current mirror ratios, respectively.
Therefore, the MOS transistor PE8 of the current source circuit 11 forms a current mirror circuit with the MOS transistor PE1, the MOS transistor PE3, the MOS transistor PE4, and the MOS transistor PE6.

Further, in the second embodiment, as in the first embodiment, the above-described mirror ratio m and the conductivity coefficient K of the input MOS transistors of the charge / discharge determination amplifiers 14 and 15 are determined using a predefined formula. An optimum value is obtained, and design is performed under the obtained optimum value.
Note that the specific configuration at the transistor level in the second embodiment is basically the same as the configuration in the first embodiment. Omitted.

Next, an operation example of the second embodiment having such a configuration will be described with reference to FIGS.
Now, for example, when the output of the NOR gate 191 is L level, the input signal of the CMOS inverter of the first charge / discharge circuit 13 is L level, so that the MOS transistor PE2 is turned on and the MOS transistor NE3 is turned off. is there.

For this reason, since the capacitor 2A is connected to the MOS transistor PE1 that is a current source, the capacitor 2A is charged by the first charging / discharging circuit 13. Therefore, at this time, the voltage V1 of the capacitor 2A increases linearly as shown by the solid line in FIG.
At this time, since the output of the NOR gate 192 is at the H level, the input signal of the CMOS inverter of the second charge / discharge circuit 14 is at the H level, and the MOS transistor PE5 is turned off and the MOS transistor NE2 is turned on.

For this reason, since both ends of the capacitor 2B are short-circuited by the MOS transistor NE2, the voltage V2 of the capacitor 2B maintains 0 [V] as shown by the broken line in FIG.
Thereafter, when the voltage V1 of the capacitor 2A reaches the logic threshold value VT of the first charge determination amplifier 13, the output of the MOS transistor NE4 is inverted from the L level to the H level. As a result, the output of the NOR gate 192 changes from the H level to the L level, and the output of the NOR gate 191 changes from the L level to the H level.

  For this reason, the input signal of the CMOS inverter of the first charge / discharge circuit 13 changes from the L level to the H level, so that the MOS transistor PE2 is turned off and the MOS transistor NE3 is turned on. For this reason, since both ends of the capacitor 2A are short-circuited by the MOS transistor NE3, the voltage V2 of the capacitor 2A rapidly decreases to 0 [V] as shown in FIG. 4, and thereafter maintains that state.

  In parallel with these operations, the input signal of the CMOS inverter of the second charge / discharge circuit 14 changes from the H level to the L level, so that the MOS transistor PE5 is turned on and the MOS transistor NE2 is turned off. For this reason, since the capacitor 2B is connected to the MOS transistor PE4 which is a current source, the capacitor 2B is charged by the first charging / discharging circuit 14. Accordingly, at this time, the voltage V2 of the capacitor 2B increases linearly as shown in FIG.

Thereafter, when the voltage V2 of the capacitor 2B reaches the logic threshold value VT of the second charge determination amplifier 14, the output of the MOS transistor NE1 is inverted from the L level to the H level. As a result, the output of the NOR gate 192 changes from the L level to the H level, and the output of the NOR gate 191 changes from the H level to the L level.
By repeating such a series of operations, a pulse having a desired cycle is output from the output terminal 12.
Note that the design method in the second embodiment is basically the same as the design method in the first embodiment, and a description thereof will be omitted.

(Third embodiment)
The configuration of the third embodiment of the oscillator of the present invention will be described with reference to FIG.
When the first or second embodiment shown in FIG. 1 or FIG. 3 is used under a low current operating condition, the gain of the charge determination amplifier is insufficient. For example, when the inverter 171 shown in FIG. May be an abnormal operation (such as chattering).

Therefore, in this third embodiment, in order to avoid this, the inverter 171181 shown in FIG. 3 is replaced with buffer amplifiers 21 and 22 that can obtain a sufficient gain as shown in FIG. .
Further, in the third embodiment, the inverters 173 and 183 that drive the latch circuit 19 shown in FIG. 3 are replaced with Schmitt circuits 23 and 24, thereby forming a pulse in the latch circuit 19 and making the blunt waveform a rectangular wave. I tried to do it.

  As shown in FIG. 5, the buffer amplifier 21 includes a P-type MOS transistor PE11 in the input stage and an N-type MOS transistor NE11 that functions as a current source and a load. Further, as shown in the figure, the buffer amplifier 22 includes a P-type MOS transistor PE12 in the input stage, and an N-type MOS transistor NE12 that functions as a current source and a load.

A desired bias voltage is supplied to the gates of the MOS transistors NE11 and NE12 of the buffer amplifiers 21 and 22, respectively. For this purpose, a P-type MOS transistor PE13 and an N-type MOS transistor NE13 are added to the current source circuit 11, thereby generating the bias voltage Vb. The generated bias voltage Vb is used as the MOS transistor NE11, Each is supplied to the gate of the NE 12.
The portions of the third embodiment other than the above-described configuration are the same as those of the second embodiment shown in FIG. 3, and therefore the same components are denoted by the same reference numerals and detailed description thereof is omitted. To do.

Next, a specific configuration of the Schmitt circuits 23 and 24 in FIG. 5 will be described with reference to FIG.
In this Schmitt circuit, P-type MOS transistors PE21 and PE22 and N-type MOS transistors NE21 and NE22 are connected in series between a power supply terminal 31 and a ground terminal 32, as shown in FIG. Yes. The gates of the four MOS transistors are connected to each other, the common connection portion is connected to the input terminal 33, and the input voltage VIN is supplied. Further, the drain of the MOS transistor PE22 and the drain of the MOS transistor NE21 are connected, and this common connection is connected to the output terminal 34, and the output voltage OUT is taken out from the output terminal 34.

  Further, the gates of the P-type MOS transistor PE23 and the N-type MOS transistor NE23 are connected, and the common connection portion is connected to the output terminal 34. The source of the MOS transistor PE23 is connected to the drain of the MOS transistor PE21, and the drain thereof is connected to the ground terminal 32. Further, the source of the MOS transistor NE23 is connected to the source of the MOS transistor NE21, and the drain thereof is connected to the power supply terminal 31.

(Other)
As the capacitor of each embodiment, a MOS capacitor whose thickness is well controlled, and in particular, a capacitor whose width of the depletion layer is shortened may be used.
The resistor R1 used in the current source circuit of each embodiment may be an N + poly resistor with little manufacturing variation, and the resistance value may be trimmed to the center value at the time of prototype evaluation.
In the third embodiment, the buffer amplifier and the Schmitt circuit are included. However, in the second embodiment, the buffer amplifier and the Schmitt circuit may be included.

1 is a circuit diagram showing a configuration of a first embodiment of an oscillator of the present invention. It is a wave form diagram which shows the waveform of each part at the time of operation | movement of 1st Embodiment. It is a circuit diagram which shows the structure of 2nd Embodiment of the oscillator of this invention. It is a wave form diagram which shows the waveform of each part at the time of operation | movement of 2nd Embodiment. It is a circuit diagram which shows the structure of 3rd Embodiment of the oscillator of this invention. It is a circuit diagram which shows the structural example of a Schmitt circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,11 ... Current source circuit 2, 2, 2A, 2B ... Capacitor 3, 13 ... 1st charging / discharging circuit 4, 14 ... 2nd charging / discharging circuit 5, 15 ... 1st charge determination amplifier, 6, 16 ... 2nd charge determination amplifier, 7, 17 ... Delay inverter stage, 8, 18 ... Delay inverter stage, 9, 19 ... Latch circuit

Claims (4)

Each circuit is an oscillator composed of MOS transistors,
A current source circuit for generating a reference current;
A capacitor;
A first charging / discharging circuit for charging the capacitor and discharging the capacitor with a charging current generated based on the reference current;
A second charging / discharging circuit for charging the capacitor and discharging the capacitor with a charging current generated based on the reference current;
A first charge determination amplifier that determines whether or not a charge voltage on one end side of the capacitor by the first charge / discharge circuit is completed to a logical threshold value, and outputs a signal according to the determination;
A second charging determination amplifier that determines whether or not a charging voltage on the other end side of the capacitor by the second charging / discharging circuit is completed up to a logical threshold, and outputs a signal according to the determination;
A latch circuit that generates control signals for controlling charge / discharge operations of the first and second charge / discharge circuits based on both output signals of the first and second charge determination amplifiers,
The first and second charge determination amplifiers are constant current drive type inverters including an input first MOS transistor and a second MOS transistor that generates a bias current for driving the first MOS transistor. Configure each
The bias currents for driving both the charge determination amplifiers are generated based on reference currents generated by the current source circuits, respectively.
In designing, the mirror ratio m determined between the reference current of the current source circuit 1 and the bias current of the both charge determination amplifiers, and the conductivity coefficient K of the first MOS transistor for input are optimal. An oscillator characterized in that each value is obtained in advance and configured so as to have each obtained value.   Each value of the mirror ratio m and the conductivity coefficient K is defined in advance as a predetermined definition formula, and the definition formula is determined within a range of variation in threshold voltage of the first MOS transistor for input. 2. The oscillator according to claim 1, wherein a value satisfying the above is obtained. Each circuit is an oscillator composed of MOS transistors,
A current source circuit for generating a reference current;
A first capacitor and a second capacitor;
A first charging / discharging circuit for charging the first capacitor and discharging the first capacitor with a charging current generated based on the reference current;
A second charging / discharging circuit for charging the second capacitor and discharging the second capacitor with a charging current generated based on the reference current;
A first charge determination amplifier that determines whether or not the charging voltage of the first capacitor is completed to a logical threshold value, and outputs a signal according to the determination;
A second charging determination amplifier that determines whether or not the charging voltage of the second capacitor is completed up to a logical threshold, and outputs a signal according to the determination;
A latch circuit that generates control signals for controlling charge / discharge operations of the first and second charge / discharge circuits based on both output signals of the first and second charge determination amplifiers,
The first and second charge determination amplifiers are constant current drive type inverters including a first MOS transistor for input and a second MOS transistor for generating a bias current for driving the first MOS transistor. Configure each
The bias currents for driving both the charge determination amplifiers are generated based on reference currents generated by the current source circuits, respectively.
In designing, the mirror ratio m determined between the reference current of the current source circuit 1 and the bias current of both the charge determination amplifiers and the conductivity coefficient K of the first MOS transistor for input are optimal. An oscillator characterized in that each value is obtained in advance and configured to have the obtained values.   Each value of the mirror ratio m and the conductivity coefficient K is defined in advance as a predetermined definition formula, and the definition formula is determined within a range of variation in threshold voltage of the first MOS transistor for input. 4. The oscillator according to claim 3, wherein a value satisfying the above is obtained.

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