JP2007288178A5

JP2007288178A5 -

Info

Publication number: JP2007288178A5
Application number: JP2007073794A
Authority: JP
Filing date: 2007-03-21
Publication date: 2010-04-15
Anticipated expiration: 2027-03-21

Claims

A semiconductor substrate having an impurity region of a pair, and between the channel formation region,
A first insulating layer prior SL channel forming region,
A floating gate on the first insulating layer,
A second insulating layer on said floating gate,
And a control gate on the second insulating layer,
The first insulating layer has a lamination of a silicon nitride layer on the silicon oxide layer and a silicon oxide layer,
The floating gate comprises a semiconductor material,
The band gap of the semiconductor material, a non-volatile semiconductor memory device, characterized in that less than the bandgap of the channel formation region of the semiconductor substrate.

A semiconductor substrate having an impurity region of a pair, and between the channel formation region,
A first insulating layer prior SL channel forming region,
A floating gate on the first insulating layer,
A second insulating layer on said floating gate,
And a control gate on the second insulating layer,
The first insulating layer has a lamination of a silicon nitride layer on the silicon oxide layer and a silicon oxide layer,
The non-volatile semiconductor memory device, wherein the floating gate has a material having an electron affinity higher than that of silicon.

A semiconductor substrate having an impurity region of a pair, and between the channel formation region,
A first insulating layer prior SL channel forming region,
A floating gate on the first insulating layer,
A second insulating layer on said floating gate,
And a control gate on the second insulating layer,
The first insulating layer has a lamination of a silicon nitride layer on the silicon oxide layer and a silicon oxide layer,
A non-volatile semiconductor memory characterized in that a barrier energy against electrons in the floating gate formed by the silicon oxide layer is higher than a barrier energy against electrons in a channel formation region of the semiconductor substrate formed by the silicon oxide layer. apparatus.

A semiconductor substrate having an impurity region of a pair, and between the channel formation region,
A first insulating layer prior SL channel forming region,
A floating gate on the first insulating layer,
A second insulating layer on said floating gate,
And a control gate on the second insulating layer,
The first insulating layer has a lamination of a silicon nitride layer on the silicon oxide layer and a silicon oxide layer,
The non-volatile semiconductor memory device, wherein the floating gate is formed of germanium or a germanium compound.

A semiconductor substrate having an impurity region of a pair, and between the channel formation region,
A first insulating layer prior SL channel forming region,
A floating gate on the first insulating layer,
A second insulating layer on said floating gate,
And a control gate on the second insulating layer,
The first insulating layer has a lamination of a silicon nitride layer on the silicon oxide layer and a silicon oxide layer,
The floating gate is germanium or a germanium compound, a nonvolatile semiconductor memory device according to claim Oh Rukoto in the 1nm or 20nm or less thick.

Oite to claim 1, wherein the band gap of the material forming the channel formation region in the semiconductor substrate, nonvolatile difference in band gap of the semiconductor material forming the floating gate, characterized in that at least 0.1eV Semiconductor memory device.

6. The nonvolatile semiconductor memory device according to claim 4 , wherein the germanium compound is germanium oxide or germanium nitride.

In any one of claims 1 to 7, wherein the floating gate, the nonvolatile semiconductor memory device, characterized in that in contact with the silicon nitride layer.

Those in any one of claims 1 to 8, wherein the silicon oxide layer, which said semiconductor substrate is oxidized by plasma treatment, the silicon nitride layer, said silicon oxide layer is nitrided by plasma treatment A non-volatile semiconductor memory device characterized by the above.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer has a thickness of 1 nm to 20 nm.

11. The nonvolatile semiconductor memory device according to claim 1, wherein the second insulating layer includes a silicon nitride layer in which the floating gate is nitrided by plasma treatment.

11. The first insulating layer according to claim 1, wherein the second insulating layer includes a silicon nitride layer, and the floating gate is in contact with the silicon nitride layer included in the second insulating layer. A non-volatile semiconductor memory device.

13. The nonvolatile semiconductor memory device according to claim 1, further comprising sidewalls on side surfaces of the control gate, the second insulating film, and the floating gate.

14. The nonvolatile semiconductor memory device according to claim 13, wherein the semiconductor substrate has a low concentration impurity region below the sidewall and between the pair of impurity regions and the channel formation region.