JP2008010842A5

JP2008010842A5 -

Info

Publication number: JP2008010842A5
Application number: JP2007136314A
Authority: JP
Filing date: 2007-05-23
Publication date: 2010-05-27
Anticipated expiration: 2027-05-23

Claims

A semiconductor region having a channel forming region between the impurity regions of a pair,
A first insulating layer prior SL channel forming region,
A plurality of layers on the first insulating layer,
A second insulating layer on the plurality of layers;
Possess a control gate, the said second insulating layer,
Wherein the plurality of layers, a non-volatile semiconductor memory device characterized by have a different nitride compound.

A semiconductor region having a channel formation region between a pair of impurity regions;
A first insulating layer on the channel formation region;
A plurality of layers on the first insulating layer;
A second insulating layer on the plurality of layers;
A control gate on the second insulating layer;
Each of the plurality of layers has a different nitride compound;
An area of an upper surface of the plurality of layers is smaller than an area of an upper surface of the control gate;
The second insulating layer extends beyond an end of the control gate;
Said to overlap with the channel formation region, the first insulating layer, said multiple layers, said second insulating layer, and a non-volatile semiconductor memory device, characterized in that said control gate are stacked.

A semiconductor region having a channel formation region, a pair of LDD regions, a source region, and a drain region;
A first insulating layer on the channel formation region;
A plurality of layers on the first insulating layer;
A second insulating layer on the plurality of layers;
A control gate on the second insulating layer;
Each of the plurality of layers has a different nitride compound;
An area of an upper surface of the plurality of layers is smaller than an area of an upper surface of the control gate;
The second insulating layer extends beyond an end of the control gate;
The nonvolatile semiconductor memory device, wherein the control gate overlaps with the channel formation region and the pair of LDD regions.

In any one of Claims 1 thru | or 3 ,
At least one non-volatile semiconductor memory device characterized by functioning as a charge storage layer of the multiple layers.

In claim 4 ,
The first insulating layer has a oxidation silicon layer,
Interface before Symbol silicon oxide layer and the charge storage layer or in the silicon oxide layer, the nonvolatile semiconductor memory device which comprises nitrogen.

A semiconductor region having a channel formation region between a pair of impurity regions;
A first insulating layer having an oxide layer and a nitride layer on the channel formation region;
A plurality of layers on the first insulating layer;
A second insulating layer on the plurality of layers;
A control gate on the second insulating layer;
Each of the plurality of layers has a different nitride compound;
An area of an upper surface of the plurality of layers is smaller than an area of an upper surface of the control gate;
The nonvolatile semiconductor memory device, wherein the second insulating layer extends beyond an end portion of the control gate.

In any one of Claims 1 thru | or 6 ,
The non-volatile semiconductor memory device, wherein the plurality of layers include a layer containing a germanium nitride compound.

In claim 7 ,
The nonvolatile semiconductor memory device, wherein the germanium nitride compound is germanium nitride, germanium nitride to which oxygen is added, or germanium to which oxygen and hydrogen are added.

In any one of Claims 1 thru | or 8 ,
The non-volatile semiconductor memory device, wherein the plurality of layers include a layer containing a silicon nitride compound.

In claim 9 ,
The nonvolatile semiconductor memory device, wherein the silicon nitride compound is silicon nitride, silicon nitride to which oxygen is added, or silicon nitride to which oxygen and hydrogen are added.

In any one of Claims 1 to 10 ,
Each of said multiple layers, the non-volatile semiconductor memory device, wherein the thickness is 1nm or more 20nm or less.

In any one of Claims 1 to 11,
The nonvolatile semiconductor memory device, wherein the semiconductor region is provided in a semiconductor layer on an insulating surface.

In any one of Claims 1 to 12,
The non-volatile semiconductor memory device, wherein the semiconductor region is provided on a semiconductor substrate.