JP2007281470A - Gate structure of integrated circuit memory device having charge storing nano crystals in metal oxide dielectric film and method of forming the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate structure of an integrated circuit memory device having charge storing nano crystals in a metal oxide dielectric film and a method of forming the gate structure. <P>SOLUTION: The method of forming a gate structure of an integrated circuit memory device includes forming a metal oxide dielectric film 150 on an integrated circuit substrate 100. Ions of an element selected from group IV of the periodic table and having a thermal diffusivity no larger than 0.5 cm<SP>2</SP>/s, such as Ge, are injected into the dielectric film to form a charge storing region in the dielectric film with a tunnel dielectric film 135 formed under the charge storing region and a capping dielectric film 140 formed on the charge storing region. The substrate 100 including the dielectric film 150 is thermally treated to form a plurality of discrete charge storing nano crystals 130_NC in the charge storing region. A gate electrode layer 160 is formed on the dielectric film 150. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an integrated circuit device, and more particularly to a gate structure of an integrated circuit device and a method for forming the same.

  Increasing use of portable electronic products and embedded systems requires low power, high density, ultrafast programmable non-volatile memory. One form of the memory thus developed is a flash EEPROM (Electronically Erasable and Programmable Read Only Memory). Flash EEPROMs are used not only for huge electronic systems such as automobiles, airplanes, and industrial control systems, but also for many portable electronic products such as personal computers, mobile phones, portable computers, recorders and the like.

  Flash EEPROM devices are typically formed on an integrated circuit substrate such as a semiconductor substrate. Doped source and drain regions are generally formed in the surface portion of the substrate with a channel region therebetween. The tunnel silicon oxide insulating film can be formed on the semiconductor substrate on the channel region between the source and drain regions. A laminated gate structure including a floating gate layer, a control gate layer, and an electrode dielectric layer interposed therebetween is generally formed on the tunnel silicon oxide insulating film on the channel region. The source region is generally located on one side of the stacked gate structure, with one end of the source region overlapping the gate structure. The drain region is generally located on the opposite side of the stacked gate structure, with one end overlapping the gate structure. Such an apparatus can be programmed, for example, by hot electron injection as shown in FIG. 1 and erased by FN (Fowler-Nordheim) tunneling.

  It has been proposed that silicon (Si) nanocrystal flash EEPROM devices can be programmed at high speeds (hundreds of nanoseconds) by storing electrons in silicon nanocrystals using a low voltage for direct tunneling. By using electrically isolated nanocrystal charge storage regions, charge leakage due to local defects in the gate dielectric can be reduced, for example, as shown in FIG. This can be contrasted with the continuous floating gate leakage path shown in FIG.

  It has also been proposed that Ge nanocrystal flash EEPROM devices can be programmed with low power and high speed. Such an apparatus can be manufactured by implanting Ge ions into a silicon substrate. However, the ion implantation process places Ge in the boundary region of the silicon-tunnel insulating film and forms a trap region that can degrade the performance of the device. The presence of such a trap region does not significantly limit the thickness of the tunnel dielectric, but it provides insufficient data retention due to defect-induced leakage currents in very thin tunnel dielectrics. Because there are things.

  In addition, a nanocrystal charge trap triple film structure having a tunneling film, a Ge-doped insulating film, and a capping film structure has been proposed. Such a structure may reduce memory hysteresis characteristics of the capacitance-voltage curve, and may have problems such as manufacturing process complexity, leakage current, and diffusion of ions to the outside. However, the process complexity of the nanocrystal charge trap triple film structure can include difficulties in forming charge traps and consequently in forming an excessively thin tunnel insulator.

  A technical problem to be solved by the present invention is to provide a method of manufacturing a nanocrystal nonvolatile semiconductor integrated circuit device exhibiting memory hysteresis characteristics.

  Another technical problem to be solved by the present invention is to provide a nanocrystal nonvolatile semiconductor integrated circuit device that exhibits memory hysteresis characteristics and has a simplified structure.

  The objects of the present invention are not limited to the objects mentioned above, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

The present invention includes a step of forming an insulating layer on a substrate, and ion implantation of an element selected from group IV of the periodic table and having a thermal diffusivity of 0.5 cm ² / s or less into the insulating layer. Stages,
Partitioning the insulating layer into a tunnel insulating layer below the charge storage region and a capping insulating layer above the charge storage region by forming a charge storage region in the insulating layer by implanting the ions; And heat-treating the substrate including the insulating layer in which the tunnel insulating layer, the charge storage region, and the capping insulating layer are partitioned to form a plurality of separated charge storage nanocrystals in the charge storage region; And a step of forming a gate electrode layer on the insulating layer to solve the above-mentioned problem by a method of forming a gate structure of an integrated circuit memory device.

  According to the manufacturing method of the present invention, a tunnel insulating film having an energy band gap exceeding 5 eV and a relative dielectric constant exceeding 7 and implanting ions into a dense film having a quality higher than that of a silicon oxide film by an annealing process, Since the nanocrystal and the coupling and blocking insulating film can be formed at the same time, not only the process is simple but also the formation of a single-layer nanocrystal is easy.

  Meanwhile, according to the integrated circuit memory device of the present invention, since the nanocrystal is used as the charge trap site, the trapped charge leakage due to the defect is less than that of the integrated circuit memory device using the conventional floating gate. Can be significantly reduced. Furthermore, when the nanocrystal is embodied as a Ge nanocrystal, low power and high speed operation are possible. Also, the integrated circuit memory device of the present invention has significantly improved memory hysteresis characteristics as compared with the conventional nanocrystal integrated circuit memory device. Further, since the tunnel insulating film is made of a high dielectric constant material, leakage current characteristics are improved, and the coupling and blocking insulating film is also made of a high dielectric constant material, so that high speed operation is possible.

  Advantages and features of the present invention and methods of achieving the same will be apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiment disclosed below, and can be embodied in various forms that deviate from this embodiment. The embodiment described in this specification completes the disclosure of the present invention, and The present invention is provided in order to fully inform those skilled in the art in the technical field to which the present invention pertains, and the present invention is only defined by the claims and the detailed description of the invention. On the other hand, the same reference numerals denote the same components throughout the specification.

  The present invention will be described in further detail below with reference to the accompanying drawings disclosed in the embodiments of the invention. In the drawings shown in the present invention, each component may be illustrated in a slightly enlarged or reduced manner for convenience of explanation.

  What elements or layers are referred to as "on", "connected to" or "coupled to" other elements or layers This includes not only an element or a layer directly above but also a case where another layer or another element is interposed in the middle. On the other hand, the elements are referred to as “directly on”, “directly connected to” or “directly coupled to”, etc. This means that no element or layer is interposed. The same reference numerals indicate the same components. As used herein, “and / or” includes each and every combination of one or more of the items mentioned.

  Even if terms such as “first”, “second” are used herein to describe various components, components, regions, membranes and / or areas, such components, Components, regions, membranes and / or areas should not be limited by such terms. Such terms are only used to distinguish one component, component, region, film or section from another region, film or section. Accordingly, the first component, component, region, membrane or area discussed below may be referred to as the second component, component, region, membrane or area without departing from the guidelines of the present invention.

  The spatially relative terms "beneath", "below", "lower", "above", "upper", etc. are shown in the drawings. As can be used to easily describe the correlation with one device or component. Spatial relative terms should be understood as terms that include different directions of the device in use or operation in addition to the directions shown in the drawings. For example, if the apparatus of the drawing is flipped over, the component described as “below” or “beneath” relative to the other component or drawing is “above” the other component or drawing. above) ”. Thus, the exemplary term “below” may include both above and below directions. The device can be oriented in other directions (rotated to 90 ° or have other directions), and spatially relative terms can be interpreted and used thereby.

  The terminology used herein is for describing the embodiments and is not intended to limit the present invention. In this specification, the singular forms also include plural forms unless the context clearly indicates otherwise. As used herein, “comprises” and / or “comprising” refers to one or more other components, steps, operations and / or other than the mentioned components, steps, operations and / or apparatus. Used to mean that the presence or addition of equipment is not excluded.

  Also, the embodiments described herein will be described with reference to cross-sectional and / or schematic illustrations that are ideal illustrations of the invention. Therefore, the form of the example diagram may change depending on the manufacturing technique and / or tolerance. Accordingly, embodiments of the present invention are not limited to the specific forms shown, but are to include variations in form produced by the manufacturing process. For example, the etched area shown in the rectangle may be round or curved. Accordingly, the areas shown in the drawings are schematic and the form of the drawings is not intended to accurately illustrate the area of the device and is not intended to limit the scope of the invention.

  Unless otherwise defined, all terms used herein (including technical and scientific terms) have the meanings commonly understood by one of ordinary skill in the art. Also, commonly used normative terms shall be construed to have a meaning consistent with their meaning in the relevant field and context of this specification, and unless otherwise defined herein, ideal or excessive It is not interpreted as a stylized meaning.

  An example of an embodiment of a gate structure of an integrated circuit memory device of the present invention will be described with reference to FIGS. 3A to 3D.

The gate structure of the integrated circuit memory device according to the present invention includes a substrate, a tunnel insulating layer on the substrate that is a part of the insulating layer on the substrate, and an IV of a periodic table on the tunnel insulating layer. A charge storage region comprising a plurality of isolated nanocrystals of an element selected from the group and having a thermal diffusivity of 0.5 cm ² / s or less, and a portion of an insulating layer on the substrate on the charge storage region A gate structure of an integrated circuit device comprising a capping insulating layer and a gate electrode layer on the capping insulating layer, which can be used in, for example, a flash memory device and is defined by source and drain regions in a substrate A gate structure having a channel region can be provided. The first insulating layer is formed on the channel region, and the second insulating layer has an energy band gap exceeding about 5 eV and is formed on the first insulating film with a structure thinner than that of the first insulating layer. A plurality of charge storage nanocrystals are embedded in the first insulating layer, and a control gate is provided on the second insulating layer to provide a floating gate structure. Since the first insulating layer has a shape in which a charge storage nanocrystal is embedded, the lower portion of the nanocrystal is a tunnel insulating layer, the first insulating layer portion above the nanocrystal and the second insulating layer are Coupling / capping and blocking having a charge storage layer comprising a plurality of isolated charge storage nanocrystals between the tunnel insulating film and the coupling / capping and blocking insulating layer, which becomes a coupling / capping and blocking insulating layer It can correspond to an insulating layer.

A method for forming a gate structure according to the present invention includes a step I of forming an insulating layer on a substrate, and
Performing an ion implantation of an element selected from group IV of the periodic table and having a thermal diffusivity of 0.5 cm ² / s or less into the insulating layer;
By performing the ion implantation to form a charge storage region in the insulating layer, the insulating layer is partitioned into a tunnel insulating layer below the charge storage region and a capping insulating layer above the charge storage region. Stage III to
Heat treating the substrate including the insulating layer in which the tunnel insulating layer, the charge storage region, and the capping insulating layer are partitioned to form a plurality of separated charge storage nanocrystals in the charge storage region; and
Forming a gate electrode layer on the insulating layer;
An example of an embodiment according to the present invention will be described below with reference to the drawings.

  The insulating layer according to the present invention is preferably composed of a first insulating layer, and the insulating layer is a metal oxide or Al, Hf, Ti, Zr, Sc, Y having a relative dielectric constant of more than 7. And at least one selected from the group consisting of oxides and oxynitrides of La. In addition, as will be described in detail below, the insulating layer is made of a first insulating layer, and it is more preferable to form a second insulating layer containing a metal oxide on the first insulating layer between the ion implantation and the heat treatment of the substrate. .

  Referring to the flowchart of FIG. 16 and the cross-sectional view of FIG. 3A, the low dielectric constant insulating layer forming process of step 1600 is shown in FIG. 3A showing that the first insulating layer 110 is formed on the substrate 100. You can see that The first insulating layer 110 is preferably a metal oxide, more preferably a silicon oxide film, and may have an energy band gap exceeding about 5 eV. The thickness of the first insulating layer 110 is preferably about 30 nm or less, more preferably 20 nm or less, and particularly preferably 17 nm or less. In some embodiments, a single nanocrystal film can be easily formed in the first insulating layer 110 to about 15 nm.

The step of implanting ions into the first insulating layer in step 1610 to form the charge storage region is shown in FIG. 3B illustrating some embodiments of the present invention. Referring to FIG. 3B, ions of an element selected from group IV of the periodic table and having a thermal diffusivity of 0.5 cm ² / s or less are implanted into the first insulating layer 110 into the first insulating layer 110. A charge storage region is formed, and a lower portion of the charge storage region is formed to have a tunnel insulating layer. For example, as shown in FIG. 3B, the ion of an element selected from Group IV of the periodic table is not particularly limited, but Ge is particularly preferable.

  Table 1 below shows various characteristic differences between Ge, which is an ion implanted in the insulating layer, and silicon to illustrate various embodiments of the present invention. As can be seen from Table 1, Ge has a larger relative dielectric constant and smaller energy band gap than silicon, which is advantageous from the viewpoint of low voltage driving. Further, as can be seen from Table 1, Ge has a low nanocrystal formation temperature and a low thermal diffusivity, so that it is more easily formed at a desired depth, and has a lower diffusion variability. In addition, Ge can perform a rapid thermal annealing process at a lower temperature, and when performing a low temperature annealing process after ion implantation, the nanocrystal structure embedded in the insulating layer is vertical and cannot be spread in multiple layers. Is easily formed in a single layer. During the thermal process, Ge can be easily prevented from diffusing out of the silicon. As a result, nanocrystal particles can be formed to a uniform size in order to minimize interference between adjacent nanocrystal points. Further, since Ge has a higher mobility than silicon, it can be further adapted to the implementation of a high-speed nonvolatile integrated circuit device.

  In step 1610, ion implantation conditions may be selected to provide the desired average implantation depth and the delta projection range of the implanted layer. More specifically, the ion implantation energy and dose can be determined using a TRIM (Transport of Ionsin Matter) simulation code.

  In some embodiments, a delta projection range of about 7 nm is provided for the selected average implant depth. In the delta projection range of 7 nm or less, the thickness of the lower insulating film 135 of the separated nanocrystal particle layer 130_NC as shown in FIG. 5 can be about 6 nm or less. In some embodiments of the present invention, ions are implanted at an average implantation depth selected as in step 1610 with a delta projection range of about 80 to about 120 inches.

In one of several embodiments of the present invention, the first insulating layer 110 has a thickness of about 17 nm or less. In some embodiments, the ion implantation process of step 1610 preferably implants at least one ion selected from group IV of the periodic table with an implant energy of about 30 KeV or less, and a period with an implant energy of 10 eV or less. More preferably, at least one ion selected from group IV of the table is implanted, more preferably an implantation energy of 5 eV to 10 eV, particularly preferably 7 KeV to 10 eV, and an ion implantation energy of about 30 KeV or less. Implanting ions at a dose of about 1 × 10 ¹⁴ / cm ^{2 to} about 2 × 10 ¹⁶ / cm ² .

  The relationship between the “insulating layer” and “ion implantation energy” in this specification will be described below. Although the ion implantation energy is specifically described above, the ion implantation energy is originally appropriately selected depending on the thickness of the insulating layer. For example, when only one insulating layer is formed, the ion implantation energy is high, for example. Ions are preferably implanted into the insulating layer with ion implantation energy (7 KeV or more and 10 eV or less). On the other hand, when two insulating layers are formed (the first insulating layer and the second insulating layer), for example, It is preferable that ions are implanted into the first insulating layer with low ion implantation energy (5 KeV or more and 10 eV or less).

  This is because when two insulating layers are provided, the thickness of each insulating layer is thinner than when only one layer is provided.

  Referring to FIGS. 16 and 3C, the second insulating layer 120 is preferably formed on the first insulating layer 110 (step 1620). More specifically, in some embodiments of the present invention, the second insulating layer 120 is preferably a metal oxide. In a specific embodiment, the second insulating layer 120 is more preferably at least one selected from the group consisting of oxides or oxynitrides of Al, Hf, Ti, Zr, Sc, Y, and La. . The first insulating film 110 may be formed on the substrate 100 by a thermal oxidation process, and the second insulating film 120 may be formed by atomic layer deposition and / or PECVD (Plasma Enhanced Chemical Vapor Deposition).

The metal oxide as the second insulating film 120 may be a dense film having an energy band gap exceeding 5 eV and being thinner than the first insulating film 110. The second insulating film 120 acts to limit or prevent electrons from passing through the first insulating film 110 and tunneling to the control gate formed on the second insulating film 120 during the programming operation. The thickness of the second insulating film 120 is preferably about 10 nm or less from some embodiments of the present invention, and the capacitance of the gate including the second insulating film 120 can be increased to facilitate high-speed operation. To. For the second insulating film 120, for example, Al ₂ O ₃ , HfO _2, ZrO ₂ or the like can be used. Al ₂ O ₃ has a dielectric constant of 9 and an energy band gap of 8.7 eV, HfO ₂ has a dielectric constant of 25 and an energy band gap of 5.7 eV, and ZrO ₂ has a dielectric constant of 25 and an energy band gap of 7.8 eV. Have.

  A step of forming a plurality of separated charge storage nanocrystals in the charge storage region of the first insulating film 110 by heat-treating the substrate including the first insulating film 110 and the second insulating film 120 is shown in Step 1630 of FIG. This will be described with reference to FIGS. 3D and 4A and 4B. As shown in FIG. 3D, in some embodiments of the present invention, rapid thermal annealing 122 is used to heat-treat the first insulating film 110. The rapid thermal annealing can be performed, for example, in a nitrogen gas atmosphere.

  As shown in FIGS. 4A and 4B, a first stage (FIG. 4A) or second stage (FIG. 4B) annealing process may be used for the process of step 1630 of FIG. The first stage annealing may be performed at about 700 ° C. to 950 ° C. for about 5 minutes to about 30 minutes, more preferably about 700 ° C. to about 900 ° C. for about 5 minutes to about 30 minutes. More specifically, the first stage annealing may be performed for 10 minutes. Referring to FIG. 4B, the first thermal annealing may be performed at a temperature lower than the temperature condition described with reference to FIG. 4A to form nanocrystals separated in the charge storage region of the first insulating layer 110. The nanocrystals of the present invention preferably have a diameter of about 1 nm to about 7 nm, and the spacing between nanocrystals is preferably between about 1 nm and about 7 nm. In some embodiments, a single layer of nanocrystals is formed in the first insulating layer 110. In another embodiment, the diameter range of the nanocrystal is more preferably about 3 nm to about 7 nm.

  As shown in FIG. 4B, after the nanocrystal is formed, a second step annealing is performed to densify the first insulating layer 110 and further repair the damage generated in the first insulating layer 110 during ion implantation. Yes. In some embodiments, the second rapid thermal annealing can be performed at a temperature of about 900 ° C. to about 1050 ° C. for about 5 minutes to about 30 minutes. The second rapid thermal annealing is more preferably performed at a temperature of about 900 ° C. to about 950 ° C. The second annealing at a relatively high temperature can effectively repair defects generated in the first insulating film 110.

  The gate structure of the integrated circuit device according to some embodiments of the present invention will be described with reference to the cross-sectional view of FIG. FIG. 5 illustrates a charge trap bilayer 150 including a first insulating layer 110 that is annealed and a second insulating layer 120 that is annealed. A plurality of charge storage nanocrystals 130_NC are embedded in the annealed first insulating layer 110. The first insulating film region 110a below the nanocrystal 130_NC forms a tunnel insulating layer 135. The first insulating layer region 110b and the second insulating layer 120 on the nanocrystal 130_NC form a coupling and blocking insulating layer 140. Here, the upper region 110b of the first insulating layer 110 may be a coupling insulating layer, and the second insulating layer 120 may be a blocking insulating layer.

  The tunnel insulating layer 135 according to the present invention preferably has a thickness of about 9 nm or less, and more preferably has a thickness of about 6 nm or less. The first insulating layer 110 may be a silicon oxide layer, and the second insulating layer 120 may be a high relative dielectric constant insulating layer.

When the first insulating layer 110 is a silicon oxide layer and the second insulating layer 120 is a metal oxide such as Al ₂ O ₃ , HfO ₂ or ZrO ₂ , the annealed second insulating layer 120 is Silicon that has spread from the first insulating layer 110 during annealing may be included. At this time, the density of silicon spread in the second insulating layer 120 may decrease along the surface of the second insulating layer 120 from the boundary surface between the first insulating layer 110 and the second insulating layer 120.

  Similarly, the second insulating layer 120 includes those in which Ge ions implanted into the first insulating layer 110 spread, and the density of the ions spread into the second insulating layer 120 is also different from that of the first insulating layer 110. The distance from the interface with the layer 120 may decrease along the surface of the second insulating layer 120. Such diffusion can proceed in both directions, and the first insulating layer 110 made of silicon oxide may include Al, Hf, Zr, or other metal material that has spread from the second insulating layer 120 during annealing. As described above, the density of the metal material spreading in the first insulating layer 120 may be sequentially decreased from the boundary surface between the first insulating layer 110 and the second insulating layer 120 toward the substrate 100.

  Referring to FIG. 5, the second insulating layer 120 is thinner than the first insulating film 110 in some embodiments. For example, the second insulating film 120 may have a thickness of about 10 nm or less, and the first insulating film 110 may have a thickness of about 17 nm or less.

  Meanwhile, although FIG. 5 illustrates a single layer of nanocrystals 130_NC separated to a single average implantation depth, in some embodiments of the present invention, multiple layers of separated nanocrystals 130_NC are represented by the first insulating layer 110. It must be understood that it is provided to the charge storage region within. In such an embodiment, ions of an element selected by the first ion implantation energy are implanted to form the first charge storage region on the tunnel insulating layer 135, and the second ion implantation energy lower than the first ion implantation energy. A second charge storage layer having a depth different from that of the first charge storage layer, substantially implanted between the first charge storage layer and the second charge storage layer. Preferably, a multi-layer structure is provided by forming a region that is free of ionized ions. Here, it should be understood that a multi-layer structure having regions substantially free of implanted ions implants ions based on the selected average implantation depth and delta projection range characteristics of the ion implantation process. In the above description, the double film structure has been described. However, ions are implanted into the first insulating layer 110 at a plurality of different heights as compared with the substrate 100, and the substrate 100 and the first insulating layer. It should be understood that the heat treatment process of 110 and the second insulating layer 120 can provide a multilayer structure in which the separated charge storage nanocrystals are overlapped.

  A flash memory device including a gate structure according to some embodiments of the present invention will be described with reference to the cross-sectional view of FIG. As shown in FIG. 6, the flash memory device includes a substrate 100 having source / drain regions 170S and 170D and a channel region 180 extending between the source / drain regions 170S and 170D.

  The charge trap bilayer 150 is formed on the channel region 180. The illustrated charge trap bilayer 150 includes a tunnel insulating layer 135 defined in the lower region 110 a of the first insulating layer 110. The thickness of the tunnel insulating layer 135 is preferably 9 nm or less, more preferably 6 nm or less, and in some embodiments, may be about 4.5 nm to 5.5 nm. The thickness of the tunnel insulating layer 135 may be selected to be thin enough to provide electron tunneling when a program voltage is applied to the flash memory device.

  The isolated nanocrystal 130_NC has a diameter of about 1 nm to about 15 nm in various embodiments, and in some embodiments has a diameter of about 3 nm to about 7 nm. The nanocrystals 130_NC are dot-shaped, and the distance between the nanocrystals 130_NC may be about 3 nm to 7 nm. The distance between the nanocrystals 130-NC can be selected to limit or prevent side diffusion of charge. The illustrated charge trap bilayer 150 further includes a coupling and blocking insulating layer 140 including the upper region 110 b of the first insulating layer 110 and the second insulating layer 120.

  The gate electrode layer is formed on the substrate and defines the control gate 160 on the second insulating layer 120. The control gate 160 may be a metal material or doped poly silicon. The control gate 160 has a single layer structure as in the embodiment of FIG. 6, and may have a multilayer structure.

  Further, the flash memory device shown in FIG. 6 further includes a sidewall spacer 165 and a capping layer 162. Sidewall spacers 165 are on each side of control gate 160 and may be formed from silicon oxide layer lines.

  Although a flash memory device will be described with reference to FIG. 6, it should be understood that various embodiments of the present invention can provide a gate structure that can be used in a non-volatile memory device and / or a DRAM. The embodiment described here is based on a flash memory device, but will be described with reference to a floating gate structure.

  6 will be further described with reference to the energy band diagrams of FIGS. 7A-7C. FIG. 7A is a diagram illustrating an energy band diagram in an initial state. Specifically, in FIG. 7A, the energy band gap of the first insulating layer 110 is 9 eV, the first insulating layer is a silicon oxide film, the energy band gap of the second insulating layer 120 is 8.7 eV, In this example, the insulating film is an aluminum oxide film, the separated nanocrystal 130_NC is a Ge nanocrystal having an energy band gap of about 0.66 eV, and the control gate 160 is aluminum.

  In FIG. 7A, the tunnel insulating layer 135 may be a silicon oxide film having a thickness of about 6 nm. The average diameter of the Ge nanocrystals 130_NC is 4 nm, and a single film of the nanocrystals 130_NC can be provided. The coupling and blocking insulating layer 140 shown in FIG. 7A includes a silicon oxide film region 110b of the insulating layer 110 having a thickness of about 7 nm and an aluminum oxide first insulating film 120 having a thickness of about 10 nm.

  The erase and program operations for the example energy band diagram shown in FIG. 7A will be described with reference to the energy band diagrams of FIGS. 7B and 7C.

  Referring to FIG. 7C, the erase operation state of the apparatus shown in FIG. 6 is shown. Specifically, the ground voltage (GND) is applied to the control gate 160, and the negative erase voltage (Verase) is applied to the substrate 100. Then, the charges stored in the separated charge storage nanocrystals 130_NC are released to the substrate 100 side by FN tunneling and / or hot carrier injection as indicated by arrows in FIG. 7C.

  With reference to FIG. 7B, the program operation state of the apparatus of FIG. 6 will be described. As shown in FIG. 7B, the positive program voltage Vpgm is applied to the control gate 160 and the ground voltage GND is applied to the substrate 100. Thereby, electrons moving from the channel region 180 are trapped in the charge storage region including the charge storage Ge nanocrystals 130_NC separated by passing through the tunnel insulating layer 135 by FN tunneling. However, when the positive program voltage Vpgm is applied to the control gate 160, a high voltage similar to the program voltage Vpgm is applied to the source region 170S, and the ground voltage GND is applied to the drain region 170D, it is adjacent to the source region 170s. The hot carrier electrons generated in this way can be injected into the Ge nanocrystal 130_NC or trapped through the tunnel insulating layer 135, as indicated by arrows in FIG. 7B. That is, FN tunneling and / or hot carrier electronic programming can be used in some embodiments of the present invention.

  If the coupling ratio of the voltage applied to the control gate 160 during the program operation is high, the FN tunneling and / or hot carrier electron injection may be more effectively performed because the high voltage is transmitted through the nanocrystal 130_NC. That is, if the second insulating film 120 is formed of a high dielectric constant material such as a metal oxide, the nonvolatile memory device can operate at high speed.

  In some embodiments, when the energy band gap of the first insulating layer region 110b is about 8 eV to about 9 eV, if the energy band gap of the second insulating layer 120 is 5 eV or less, the dotted line shown in FIG. As shown, the trap electrons of the nanocrystal 130_NC can be further tunneled in the direction of the control gate 160. As a result, in some embodiments of the present invention, the second insulating layer 120 has an energy band gap of more than 5 eV to provide the ability to prevent electron tunneling from the nanocrystal 130_NC toward the control gate 160.

  Another embodiment of the integrated circuit memory device will be described with reference to the cross-sectional views of FIGS. First, referring to the embodiment shown in FIG. 8, the charge trap double film 150 is formed in a part of the channel region 180. The second insulating layer 120 is formed as a gate insulating layer on the remaining portion of the channel region 180. The control gate 160 is formed on the second insulating layer 120. That is, the charge trapping bilayer 150 in the embodiment shown in FIG. 8 does not extend completely along the channel region 180 as compared with the embodiment of FIG. The configuration of the embodiment shown in FIG. 8 can reduce power consumption during operation of the memory device, and thus increase the program and erase efficiency of the memory device.

  The gate structure shown in FIG. 8 may be formed substantially as described above. Specifically, after the first insulating layer 110 is formed on the substrate 100 to a selected size, the separated charge storage nanocrystal forming ions are implanted into the first insulating layer 110. The second insulating layer 120 is formed to cover the first insulating layer and the substrate 100. Thereafter, the nanocrystals 130_NC may be formed in the first insulating layer 110 by a heat treatment such as the rapid thermal annealing process described above.

  The flash memory device according to another embodiment of the present invention has a charge trap double layer 150 between the gate sidewall 167 and the channel region 180 as shown in the cross-sectional view of FIG. 9 described with reference to FIG. Formed. The charge trap double layer 150 extends between the sidewall gate 167 and the common control gate 160. The gate insulating layer 105 is formed between the control gate 160 and the substrate 100 in the channel region 180. After forming the gate insulating layer 105 and the control gate 160, a charge trap bilayer 150 is formed on the resultant substrate 100. Next, a conductive film for forming a sidewall gate is deposited. The sidewall gate 167 can be formed of, for example, a conductive film deposited by an etch back process. Accordingly, a floating gate structure for a multi-bit memory cell as shown in FIG. 9 is provided.

  The embodiment shown in FIG. 9 differs from the embodiment of FIGS. 6 and 8 in that the common gate electrode 160 is formed on the gate insulating film 105 and the substrate 100 before the first insulating layer 110 is formed. There is a difference. The ion implantation and heat treatment processes of the first insulating layer 110 and the second insulating layer 120 are performed on the side wall of the common gate electrode layer 160 and on the channel portion 180 of the substrate 100 adjacent to each side surface of the common gate electrode layer 160. The sidewall gate 167 is formed to extend on the second insulating layer 120 adjacent to each side surface of the common gate 160 and on the channel portion 180 including the charge trap double film 150.

  That is, in the method of forming a gate structure of an integrated circuit memory device according to the present invention, a common gate electrode layer is formed on a gate insulating layer on a substrate before forming an insulating layer, and the insulating layer is formed and ion-implanted. Is performed on a side wall of the common gate electrode layer and on a channel portion of the substrate adjacent to each side surface of the common gate electrode layer, and the gate electrode layer is formed on each side surface of the common gate electrode layer. Forming a sidewall gate extending on the second insulating layer adjacent to the channel portion and on the channel portion.

  A memory cell structure according to still another embodiment of the present invention will be described with reference to FIG. As shown in FIG. 10, the channel region 180 includes a recess region 180_RC and a step region 180_SC adjacent to the recess region 180_RC in the region extending between the source region 170S and the drain region 170D in the substrate 100. The charge trap double film 150 is formed on the channel region 180 including the recess region 180_RC and the step region 180_SC. Further, the embodiment of FIG. 10 further includes a sidewall spacer 165 and a capping film 162. The recess region is based on a strain technique. For example, the recesses are stretched (tensile) or crushed (compressive stress) into the crystal lattice of Si, and the reaction of charge carriers (electrons and holes) in Si to applied voltage is accelerated. It can be made.

  That is, in the method for forming a gate structure of an integrated circuit memory device according to the present invention, a step region adjacent to the recess region and the recess region extending between the source region and the drain region in the substrate is formed before the insulating layer is formed. A channel region including the insulating layer, the ion implantation, the gate electrode, and the second insulating layer as necessary on the channel region including the recess region and the step region. Is preferably carried out.

  The memory cell structure shown in the embodiment of FIG. 11 is similar to that described with reference to FIG. The embodiment shown in FIG. 11 differs from the embodiment of FIG. 10 in that the recess region 180-RC includes a round portion. 10 and 11 may easily implement multi-bit storage of a memory device as in the embodiment of FIG.

Operation according to some embodiments of the invention is further described with reference to the capacitance (C) -voltage (V) hysteresis curves of FIGS. 12A-12C. FIG. 12A illustrates operating characteristics for an embodiment of the present invention when the ion selected from group IV of the periodic table and implanted into the first insulating layer 110 is Ge. More specifically, FIG. 12A shows a simulation result in which Ge ions are implanted into the silicon oxide first insulating layer 110 having a thickness of about 17 nm with a dose of about 2 × 10 ¹⁶ / cm ² and an ion implantation energy of about 30 KeV. Show. The first insulating layer 110 is grown on the p-type semiconductor substrate 100 by a thermal oxidation process. The aluminum oxide film second insulating layer 120 is formed to a thickness of about 10 nm. The separated charge storage nanocrystals 130_NC are formed by rapid thermal annealing at about 800 ° C. for about 10 minutes in a nitrogen (N ₂ ) atmosphere. The aluminum control gate 120 is formed on the second insulating layer 120.

  Using the example embodiment of the present invention having a charge trapping bilayer 120 as shown in FIG. 12, the capacitance is “81” due to the deflection voltage from a negative applied voltage to a positive applied voltage. Change in direction, ie in the opposite direction. The capacitance changes in the “82” direction due to a deflection voltage from a positive applied voltage to a negative applied voltage. That is, the embodiment shown in FIG. 12A exhibits favorable counterclockwise hysteresis characteristics. The capacitance change in the “81” direction indicates that the boundary surface between the silicon oxide film 110 and the p-type substrate 100 can be changed to an inverted state by the accumulation of electrons. When the surface of the p-type substrate 100 reaches an inverted state, electrons can be trapped in the Ge nanocrystals 130_NC in the charge storage region of the first insulating film 110. On the other hand, the capacitance curve in the “82” direction has a positive flat band voltage shift due to electrons trapped in the isolated charge storage nanocrystal 130_NC.

  From the CV curve of FIG. 12, it can be seen that as the applied voltage range increases, the positive flat band voltage shift increases and the hysteresis width increases greatly. This indicates that the greater the applied voltage, the greater the number of electrons trapped in the Ge nanocrystal 130_NC, thereby accumulating a large amount of charge. In other words, if the accumulated charge increases, the operation and performance of the device can be improved during programming. Accordingly, the embodiment of the present invention shown in FIG. 12A provides a counterclockwise hysteresis characteristic and a hysteresis width applicable to a memory device.

  In the CV hysteresis curve shown in FIG. 12B, the second insulating layer 120 is a silicon nitride oxide film having a thickness of about 30 nm, and the 10 nm thickness used in the embodiment shown in FIG. 12A. This contrasts with the aluminum oxide film. The hysteresis range shown in FIG. 12B indicates that a clockwise hysteresis characteristic appears when silicon nitride having an energy band gap of 5 eV is used as the second insulating film 120.

  In the CV hysteresis curve shown in FIG. 12C, a silicon oxide film having a thickness of about 100 nm is used as the second insulating film 120 instead of the aluminum oxide film in FIG. 12A. It can be seen that the hysteresis curve shown in FIG. 12C does not show normal characteristics when the silicon oxide film is used as the second insulating film 120.

13A to 13E illustrate CV hysteresis curves using various annealing temperatures in forming the isolated charge storage nanocrystals 130_NC in the charge storage region of the first insulating layer 110. FIG. The curves shown in FIGS. 13A to 13E show a dose of about 2 × 10 ¹⁶ / cm ^{2 in} the silicon oxide first insulating film 110 grown on the p-type substrate to a thickness of about 17 nm by a thermal oxidation process. And a structure containing Ge ions implanted with an ion implantation energy of about 7 KeV. Next, an aluminum oxide second insulating layer 120 having a thickness of about 10 nm is formed on the first insulating layer 110.

  The heat treatment for forming the separated charge storage nanocrystal 130_NC is performed by rapid thermal annealing at different temperatures for about 10 minutes in a nitrogen atmosphere. More specifically, FIG. 13A shows a temperature of about 600 ° C., FIG. 13B shows a temperature of about 700 ° C., FIG. 13C shows a temperature of about 800 ° C., FIG. 13D shows a temperature of about 900 ° C., and FIG. Corresponds to a temperature of ℃. An aluminum control gate is formed on the resulting charge trap bilayer 150.

  The CV hysteresis curve at a temperature of 600 ° C. shown in FIG. 13A does not provide normal hysteresis characteristics. When annealing is performed at a temperature of about 950 ° C. shown in FIG. 13E, a clockwise hysteresis characteristic that cannot be applied appears.

  In contrast, when annealed at temperatures of 700 ° C., 800 ° C., and 900 ° C. as shown in FIGS. 13B through 13D, a preferred counterclockwise hysteresis characteristic is provided to the memory device. More specifically, the CV hysteresis curve for the 800 ° C. annealing temperature of FIG. 13C may provide favorable memory hysteresis characteristics for some memory devices formed in embodiments of the present invention.

  Other examples of hysteresis characteristics according to embodiments of the present invention are illustrated in Table 2 below. More specifically, Table 2 provides examples of hysteresis characteristics at various Ge ion implantation energies and various annealing temperatures for devices including 10 nm and 20 nm thick aluminum oxide second insulation layers 120, respectively. . In Table 2, the clockwise hysteresis characteristic is represented as CW, and the counterclockwise hysteresis characteristic is represented as CCW. As shown in the example of Table 2, when the thickness of the aluminum oxide film is about 10 nm or less and the ion implantation energy is 7 KeV or more and 30 KeV or less and the annealing temperature is 700 ° C. to 900 ° C., it is suitable for about 10 minutes. The characteristics of the device appear.

  Such a result may be understood that some embodiments of the present invention provide isolated charge storage nanocrystals 130_NC. Thus, as shown in FIG. 14, a single leakage path for trapped charges is provided, in contrast to the leakage path of the continuous floating gate structure described with reference to FIG. That is, the leakage path generated due to the defect of the first insulating layer 110 may generate a limited amount of charge leakage applying a continuous operation of the floating gate formed by the isolated charge storage nanocrystal 130_NC.

  With additional description of various embodiments of the present invention, process simplification can be provided by the methods described herein. Furthermore, ion diffusion can be limited or prevented by the capping film structure of the second insulating film 120. By performing annealing, damage generated in the insulating layer during ion implantation can be repaired, and a stable nanocrystal can be formed. For example, by performing the two-step annealing process described with reference to FIG. 4B, damage generated in the insulating layer 110 during ion implantation can be effectively repaired. In addition, the memory device including the charge trapping bilayer 150 in some embodiments may enable low voltage and high speed operation of the memory device due to the blocking and coupling insulating layer 140 having a high dielectric constant. FIG. 15 shows a Ge ion implantation simulation result. More specifically, FIG. 15 shows simulation results in which Ge ions are implanted into a silicon oxide film target layer having a thickness of 500 mm at an angle of 7 ° with ion implantation energies of 20 KeV, 30 KeV, 35 KeV, and 40 KeV. The simulation results shown in FIG. 15 show an average implantation depth (Rp) of about 350 mm to about 400 mm in a delta projection range of about 80 mm to about 120 mm. Table 3 below shows the average implantation depth and delta projection range for each ion implantation energy.

Referring to the flowchart of FIG. 16, a method for forming a gate structure of an integrated circuit memory device is summarized. Step 1600 is a process of forming a low dielectric constant insulating film such as a silicon oxide film as a first insulating layer on the integrated circuit substrate. In step 1610, the ion of the element selected from group IV of the periodic table such as Ge in the first insulating layer 110 is taken as an example and ion implantation energy of 7 KeV or more and about 1 × 10 ¹⁴ / cm ^{2 to} about 2 ×. A charge storage region is formed in the first insulating layer by implantation at a dose of 10 ¹⁶ / cm ^2. A tunnel insulating layer of about 6 nm or less is formed below the charge storage region, and a capping insulating film is formed above the charge storage region. Form to have. In step 1620, a second insulating layer is formed on the first insulating layer to a thickness of, for example, 10 nm or less. In step 1630, the substrate including the first and second insulating layers is heat-treated, for example, by rapid thermal annealing at about 700 ° C. to about 900 ° C. for about 5 minutes to about 30 minutes, to form a plurality of separated charges in the charge storage region. Conserved nanocrystals are formed. In step 1640, a gate electrode layer is formed on the second insulating layer.

  Another embodiment of the present invention will be described with reference to FIGS. 17 and 18. Reference numerals in FIGS. 17 and 18 are the same as those described with reference to FIGS. 3A to 3D and FIG. 5, and redundant descriptions are omitted. The embodiments of FIGS. 17 and 18 each have a charge trap double film structure and a charge trap single film structure, and can be suitably used in a nonvolatile memory device or DRAM as well as a flash memory device in the gate structure portion. . The memory device may further include a structure as described with reference to FIG.

  Referring to the embodiment shown in FIGS. 17 and 18, a metal oxide film (so-called insulating layer) or a high dielectric constant insulating film having a denser structure than the silicon oxide film as described above is formed on the channel region. Thus, there is a difference from the other embodiments in that ions are implanted. More specifically, the first insulating layer 110 has an energy band gap of more than 5 eV on the substrate 100, a relative dielectric constant of more than 7, and a thinner and denser structure than the silicon oxide film. Vertical and / or horizontal diffusion of nanocrystal-forming ions formed by implantation can be minimized.

The embodiment shown in FIG. 17 includes a high dielectric constant charge trapping bilayer structure 150a. The gate structure shown in FIG. 17 may be formed by forming the first insulating layer 110 as a metal oxide insulating film on the integrated circuit substrate 100 in some embodiments. As in the above-described embodiment, ions of an element selected from group IV of the periodic table and having a thermal diffusivity of 0.5 cm ² / s or less are implanted into the insulating layer film 110 to store charges in the insulating layer. A region is formed, and a tunnel insulating layer is formed below the charge storage region and a capping insulating layer is formed above the charge storage region. More specifically, in FIG. 17, the lower region 110a of the first insulating layer 110 corresponds to the tunnel insulating layer 135a, and the upper region 110b of the first insulating layer 110 corresponds to the capping insulating layer. In the embodiment of FIG. 17, the second insulating layer 120 is formed on the first insulating film 110 as a blocking insulating film. In FIG. 17, the upper region 110 b of the first insulating layer 110 corresponds to the coupling and blocking insulating layer 140 a together with the second insulating layer 120.

  The substrate 100 including the insulating layer 110 into which ions are implanted is heat-treated to form a plurality of separated charge storage nanocrystals 130_NC in the charge storage region of the insulating layer 110. A gate electrode 160 as shown in FIG. 6 is formed on the second insulating layer 120 to form a gate structure as shown in the embodiment of FIG.

The insulating layer 110 of the present invention preferably includes at least one selected from the group consisting of oxides or oxynitrides of Al, Hf, Ti, Zr, Sc, Y, and La having a dielectric constant exceeding 7. In some embodiments, the insulating layer film 110 more preferably includes Al ₂ O ₃ having a relative dielectric constant of 9 and an energy band gap of 8.7 eV. In another embodiment, the oxide insulating layer film 110 preferably includes HfO ₂ having a relative dielectric constant of 25 and an energy band gap of 5.7 eV. In yet another embodiment, the first insulating layer 110 preferably includes ZrO ₂ having a relative dielectric constant of 25 and an energy band gap of 7.8 eV. The thickness of the oxide insulating layer 110 is preferably about 30 nm or less, and in some embodiments may be about 20 nm or less.

The ions implanted into the insulating layer 110 to form the isolated charge storage nanocrystals 130_NC are Ge and the ion dose is 1 × 10 ¹⁶ / cm ² or less, and some implementations of the invention In form, it may be from about 1 × 10 ¹⁴ / cm ^{2 to} about 2 × 10 ¹⁶ / cm ² . The ions are implanted with an ion implantation energy of about 10 KeV or less, so that the thickness of the tunnel insulating layer 135a can be about 9 nm or less. In some embodiments, an implantation energy of 5 KeV or higher can be used to implant Ge ions into the insulating layer 110.

  Prior to ion implantation in the insulating layer 110, the ion implantation energy and dose may be adjusted by the thickness of the insulating layer 110 and / or the desired thickness of the tunnel insulating layer 135a below the embedded nanocrystal 130_NC. . The ion implantation energy and dose can be determined using, for example, TRIM (Transport of Ions in Matter) simulation code.

The second insulating layer 120 is preferably a metal oxide or a material having a high relative dielectric constant of 4 or more, and can increase capacitance characteristics. Thereby, the high speed operation and large capacity of the final memory device including the gate structure shown in FIG. 17 can be realized. The second insulating layer 120 can have a thickness of about 10 nm or less, which can maximize the capacitance for high speed operation of the memory device including the illustrated structure. In some embodiments, the second insulating layer 120 is preferably at least one selected from the group consisting of oxides or oxynitrides of Al, Hf, Ti, Zr, Sc, Y, and La. For example, the second insulating layer 120 may be formed of Al ₂ O ₃ , HfO ₂ , ZrO ₂ and the same material as the first insulating layer 110. In another embodiment, the second insulating layer film 120 is preferably a silicon nitride film.

  In the second insulating layer 120, ions implanted during the heat treatment process for forming the nanocrystals 130_NC separated at desired positions in the first insulating layer film 110 are diffused from the first insulating layer 110 to the outside. Can be limited or prevented. Accordingly, the second insulating layer 120 operates as a blocking layer and provides the capping and blocking insulating layer 140a together with the upper capping portion 110a of the first insulating layer 110.

  Meanwhile, the first and second insulating layers 110 and 120 may be the same type of high dielectric constant material. In such an embodiment, the same kind of material selection may enable high speed operation or large capacity of the final memory device using the gate structure of FIG. 17, and may simplify the manufacturing process in forming the structure shown in FIG. . The second insulating layer 120 may be formed using, for example, atomic layer deposition (ALD) and / or PECVD (Plasma Enhanced Chemical Vapor Deposition).

  A charge trapping single membrane structure 150b according to some embodiments of the present invention will be described with reference to the cross-sectional view of FIG. In the embodiment of FIG. 18, a first insulating layer 110 is formed on the substrate 100, and in some embodiments, an energy band gap greater than 5 eV and a dielectric constant greater than 7, and see FIGS. 3A-3D and FIG. It has a denser structure than the generally provided silicon oxide film structure mentioned above. In the charge trap single membrane structure 150b of FIG. 18, the first insulating layer 110 includes a lower portion 110a adjacent to the substrate 100 defining the tunnel insulating layer 135b and an upper portion 110b defining the coupling and blocking insulating layer 140b. The nanocrystal 130_NC is embedded in the first insulating layer 110 at a distance of about 9 nm from the surface of the substrate 100 to provide a tunnel insulating layer 135b of about 9 nm or less. Therefore, the structure of FIG. 18 differs from the structure of FIG. 17 in that the second insulating layer 120 is not provided and the upper portion 110b of the first insulating layer 110 forms the coupling and blocking insulating layer 140b. In the embodiment of FIG. 18, the first insulating layer film 110 is thicker than the embodiment of FIG. In the single film structure of FIG. 18, the ion implantation energy is about 10 KeV or less, and in some embodiments, about 7 KeV or more, and can be about 10 KeV or less. For the structure of FIG. 17, in some embodiments, the ion implantation energy is about 5 KeV or more and can be about 10 KeV or less.

  Meanwhile, the charge storage nanocrystals 130_NC separated in the embodiments of FIGS. 17 and 18 may be formed by heat-treating the substrate 100 including the first insulating layer 110 after ion implantation. As described in the embodiment of FIGS. 4A and 4B, the heat treatment process may be a rapid thermal annealing process performed at about 700 ° C. to about 900 ° C. for about 5 minutes to about 30 minutes. In the embodiment of FIG. 17, the rapid thermal annealing may be performed after the second insulating layer 120 is formed.

  In the one-step annealing embodiment shown in FIG. 4A, rapid thermal annealing can be performed at about 700 ° C. to about 950 ° C. for about 10 minutes to about 30 minutes. In the two-step annealing as shown in FIG. 4B, the first annealing may be performed at about 700 ° C. to about 900 ° C. for about 5 minutes to about 30 minutes, and then at about 900 ° C. to about 1050 ° C. for about 5 minutes to about 30 minutes. Second annealing can be performed. The one-step annealing of FIG. 4A or the first annealing of FIG. 4B is performed at a selected temperature and is separated by crystallizing the ions by minimizing the outward diffusion of ions implanted in the first insulating layer 110. The charge storage nanocrystal 130_NC may be formed.

  The higher-temperature second annealing shown in FIG. 4B may further densify the first insulating film 110 and repair, for example, damage generated in the first insulating layer 110 during ion implantation. In addition, the second annealing not only suppresses the generation of leakage current in the operation of the memory device including the gate structure of FIG. 17 or FIG. 18, but can repair defects generated in the first insulating film 110.

  The nanocrystal 130_NC may be formed before performing the higher temperature second heat treatment as shown in FIG. 4B. The first annealing step provides an array of single layer nanocrystals and can form nanocrystals having a diameter of about 3 nm to about 7 nm. In some embodiments, nanocrystals 130_NC have a diameter of about 1 nm to about 7 nm, and the spacing between nanocrystals can be about 1 nm to about 7 nm.

  Meanwhile, although the process of ion-implanting a selected element with reference to a single layer structure has been described, the multilayer structure of the charge storage nanocrystal 130_NC has a first insulating layer film 110 as in various embodiments described above. The annealing of the substrate 100 and the first insulating layer 110 is performed by implanting ions at a plurality of positions at different heights compared to the substrate 100 in the separated charge storage nanocrystal 130_NC. It should be understood as providing a multilayer structure to be wrapped. As described above, ions are implanted with the first ion implantation energy to form the first charge storage layer on the tunnel insulating layers 135a and 135b, and then selected with the second ion implantation energy lower than the first ion implantation energy. An element is ion-implanted to form a second charge storage film on the first charge storage film, and a region substantially free of implanted ions is formed between the first charge storage film and the second charge storage film. Preferably, such an intermediate region substantially free of implanted ions is due to the delta projection range of the ion implantation process.

  The charge trap layer structure shown in FIG. 5 as described above may be included in various integrated circuit memory devices like the structures shown in FIGS. 6 and 8 to 11. The charge trap structure shown in FIG. 17 and / or FIG. 18 is also used in the structure of the memory device shown in FIG. 6 and FIGS. This structure can also be used in the structure of 150a and 150b. For example, referring to FIGS. 17 and 6, the structure of FIG. 6 includes a tunnel insulating layer 135a having a dense structure having a thickness of about 9 nm or less, a dielectric constant of more than about 7, and an energy band gap of more than about 5 eV. (110a) is provided, and electron tunneling may occur at the floating gate defined by the charge storage nanocrystals 130_NC separated through the tunnel insulating layer 135a. The spacing between the charge storage nanocrystals 130_NC is about 3 nm to about 7 nm, which may limit or prevent horizontal diffusion of charges between the separated charge storage nanocrystals 130_NC. The coupling and blocking insulating layer 140a restricts movement of charges stored in the separated charge storage nanocrystals 130_NC toward the control gate 160 when a voltage is applied to the control gate 160 during device operation. Can be prevented.

The operation of the gate structure including the charge trap layer structure 150a of FIG. 17 will be described in more detail with reference to the energy band diagrams of FIGS. 19A to 19C. First, referring to FIG. 19A, an energy band diagram in an initial state is illustrated. FIG. 19A shows that the first insulating layer 110 and the second insulating layer 120 are both Al ₂ O ₃ having an energy band gap of about 8.7 eV and a relative dielectric constant of 9, and the nanocrystal 130_NC has an energy band gap. This is embodied as a Ge nanocrystal having a voltage of about 0.66 eV. In the embodiment shown in FIGS. 19A to 19C, the control gate 160 is aluminum, and the thickness of the tunnel insulating layer 135a is about 9 nm. The average diameter of the Ge nanocrystals 130_NC is substantially 4 nm with a single layer structure. The thickness of the coupling and blocking insulating layer 140a is exemplified by the case where the Al ₂ O ₃ films 110b and 120 are about 17 nm thick.

  FIG. 19B is an energy band diagram for explaining the program operation. When the positive program voltage Vpgm is applied to the control gate 160 and the ground voltage GND is applied to the substrate 100, the electrons in the channel region 180 are formed by FN tunneling. Can be trapped in the Ge nanocrystal 130_NC through the tunnel insulating layer 135a.

  In some embodiments, a positive program voltage Vpgm is applied to the control gate 160, a high voltage substantially similar to the voltage applied to the control gate 160 is applied to the source region 170S, and the ground voltage GND is applied to the drain region. If applied to 170D, hot carrier electrons generated concentrated in the direction of the source region 170S may be injected into the Ge nanocrystal 130_NC through the tunnel insulating layer 135a as shown in FIG. 19B.

  If the coupling ratio of the voltage applied to the control gate 160 during the program operation is high, a higher voltage is transmitted to the nanocrystal 130_NC, so that FN tunneling or hot carrier electron injection can occur more effectively. That is, in some embodiments of the present invention, the non-volatile memory device is provided with high speed operation by using a coupling and blocking layer 140a formed of a high dielectric material having a relative dielectric constant of about 4 or more. sell.

  FIG. 19C is an energy band diagram for explaining the erase operation. As shown in FIG. 19C, when the ground voltage GND is applied to the control gate 160 and the negative erase voltage Verase is applied to the substrate 100, the charge trapped in the nanocrystal 130_NC is indicated by an arrow in FIG. 19C. As described above, it can be emitted toward the substrate 100 by FN tunneling or hot hole injection.

FIG. 20 is a TEM (Transmissive Electron Microscopy) photograph of a high dielectric constant charge trapping bilayer 150a according to some embodiments of the present invention. Referring to the photograph of FIG. 20, the first insulating layer 110 is an aluminum oxide film having a thickness of about 20 nm grown on the p-type semiconductor substrate 100 by atomic layer deposition. Ge ions are implanted into the aluminum oxide film 110 at an ion implantation energy of about 10 KeV and a dose of about 1 × 10 ¹⁶ / cm ² . The second insulating layer 120 is also an aluminum oxide film and has a thickness of about 10 nm. Thermal annealing for the formation of the nanocrystal 130_NC is performed at about 800 ° C. for about 30 minutes in a nitrogen (N ₂ ) atmosphere.

In the embodiment illustrated in FIG. 20, in addition to the thermal annealing for forming the nanocrystal 130_NC, referring to the flowchart of FIG. 24, rapid thermal annealing is further performed before ion implantation. In the embodiment illustrated in FIG. 20, annealing prior to ion implantation is rapid thermal annealing at about 950 ° C. for about 30 minutes in a nitrogen (N ₂ ) atmosphere. As shown in FIG. 20, it can be seen that the nanocrystal 130_NC is formed almost like a single film structure rather than a multilayer film structure.

Accordingly, the substrate including the insulating layer according to the present invention is preferably heat-treated before ion implantation, and the substrate including the insulating layer before the ion implantation is a temperature equal to or higher than the crystallization temperature of the insulating layer. It is more preferable that the heat treatment be performed at a temperature of 950 ° C. or higher in a nitrogen (N ₂ ) atmosphere.

  Some embodiments of the present invention will be described with reference to the CV hysteresis curve shown in FIG. FIG. 21 shows a CV hysteresis curve of a nonvolatile memory integrated circuit device having an aluminum control gate on the charge trapping double film structure of FIG. As shown in FIG. 21, some embodiments of the present invention exhibit counterclockwise hysteresis characteristics. It can also be seen that as the range of applied voltages increases, the positive flat band voltage shift increases and the hysteresis width D increases. This indicates that as the applied voltage increases, the number of electrons trapped in the Ge nanocrystal increases and thus a larger amount of charge is stored in the floating gate structure provided by the nanocrystal 130_NC. . That is, some embodiments of the present invention may provide a counterclockwise hysteresis characteristic applicable to a variety of integrated circuit device memory devices.

  On the other hand, when the thickness of the first insulating layer 110 is excessively thin in the embodiment, it may exhibit a clockwise hysteresis characteristic that cannot be applied to the integrated circuit memory device. For example, when an aluminum oxide film having a thickness of about 20 nm or less is formed as the first insulating layer 110, clockwise hysteresis characteristics can be exhibited. Further, in the embodiment using the charge trap double film 150a structure shown in FIG. 17, when the thickness of the second insulating layer is about 10 nm or less, improved hysteresis characteristics can be exhibited.

  On the other hand, some embodiments of the present invention provide a heat treatment prior to implanting ions into the first insulating layer 110. FIG. 22 is a graph that measures the effect of other annealing temperatures on leakage current characteristics for heat treatment prior to ion implantation in some embodiments of the present invention. The graph of FIG. 22 shows the case where annealing is not performed before ion implantation, when the process is advanced at about 900 ° C. for about 30 minutes, and when the process is advanced at about 950 ° C. for about 30 minutes. Referring to FIG. 22, it can be seen that the leakage current is remarkably reduced when annealing is performed compared to the case where annealing before ion implantation is not performed, and leakage occurs when annealing is performed at about 950 ° C. It can be seen that it is more effective in reducing the current.

23A and 24B are CV hysteresis curves of a high dielectric constant charge trap single layer 150b fabricated according to yet another embodiment of the present invention. More specifically, FIG. 23A shows a case where the thickness of the aluminum oxide film is formed as the first insulating layer 110 to about 20 nm, and FIG. 23B shows a case where the thickness of the aluminum oxide film is formed to about 60 nm. . In each case, the first insulating film 110 can be grown on the p-type substrate 100 by an atomic layer deposition process. In both embodiments, rapid thermal annealing before ion implantation can be performed in a nitrogen atmosphere at about 950 ° C. for about 30 minutes. Ge ions are implanted at an ion implantation energy of about 10 KeV and a dose of about 1 × 10 ¹⁶ / cm ² , and then subjected to rapid thermal annealing at about 950 ° C. for about 30 minutes in a nitrogen (N ₂ ) atmosphere to form nanocrystals 130_NC. Form. As shown in FIGS. 23A and 23B, it can be seen that even in the case of a high dielectric constant charge trapping single film, it exhibits a counterclockwise hysteresis characteristic applicable to a memory. It can be seen that the hysteresis width increases as the value increases.

An example of an embodiment of the present invention will be described with reference to a schematic process cross-sectional view of FIG. Referring to FIG. 24, each row represents various processes constituting the embodiment of the present invention, and the first column and the second column represent the embodiment of the high dielectric constant charge trap dual film manufacturing method, and the first column. The third and fourth columns each represent an embodiment of a method for manufacturing a high dielectric constant charge trapping single film. In all embodiments, forming the gate structure of the integrated circuit memory device includes forming a first insulating layer 110 on the substrate 100. The first and third row embodiments are provided with heat treatment prior to ion implantation, as described with reference to FIG. As shown in the second row of FIG. 24, a heat treatment step 111 is performed on the substrate 100 including the first insulating film 110 before ion implantation. More specifically, the first and third row embodiments perform the rapid thermal annealing process in a nitrogen (N ₂ ) atmosphere. A temperature above the crystallization temperature of the insulating layer 110 may be used in the rapid thermal annealing step 111 shown in the second row of FIG. In some embodiments, the rapid thermal annealing step is performed at about 950 ° C. in a nitrogen (N ₂ ) atmosphere.

  Every embodiment shown in the third row of FIG. 24 is a step of ion-implanting 112 ions of an element selected from group IV of the periodic table into the first insulating layer 110. More specifically, in all the embodiments in the third row, Ge ions are implanted into the first insulating layer film 110.

  On the other hand, the thickness of the first insulating layer 110 in the third and fourth row embodiments is formed to be thicker than that in the first and second row embodiments. For example, the thickness of the first insulating layer 110 may be about 30 nm in the third and fourth row embodiments, and may be about 20 nm in the first and second row embodiments.

  Referring to the fourth row, the embodiments of the first column and the second column do not form the second insulating layer in that the second insulating layer film 120 is formed on the first insulating layer 110. There are differences from the column and fourth column embodiments. The second insulating layer 120 is preferably a metal oxide, and may have a thickness of about 10 nm or less. In the first and / or second row embodiments, the second insulating layer 120 may be the same material as the first insulating layer 110. Finally, in the first to fourth column embodiments, the fifth row performs a rapid thermal annealing step 122 to form the nanocrystals 130_NC in the first insulating layer 110, referring to FIGS. The structure described above is provided.

  In some embodiments, the conditions for the fifth row rapid thermal annealing step are determined by the performance of the second row pre-implant annealing step. That is, the first column embodiment may use the fifth row heat treatment under different conditions than the second column embodiment. Similarly, the third column embodiment may use the fifth row heat treatment under different conditions than the fourth column embodiment. For example, when annealing is performed before ion implantation as shown in the second row of the first and third columns in FIG. 24, the annealing in the fifth row is as shown in FIG. 4A. In addition, the single step annealing may be performed at about 700 ° C. to about 950 ° C. for about 5 minutes to about 30 minutes. On the other hand, when the annealing is omitted before ion implantation as in the second row of the second and fourth columns in FIG. 24, the annealing in the fifth row is performed at a higher temperature of about 900 ° C. to about 950 ° C. for about 5 ° C. Can be done for about 30 minutes.

In some embodiments of the invention, Ge ions are implanted into an aluminum oxide (Al ₂ O ₃ ) target layer having a thickness of 200 mm at an angle of 7 ° and an ion implantation energy of 7 KeV and 10 KeV, respectively. . The simulation results of such an example have a delta projection range of about 20 to about 60 mm and an average implantation depth (Rp) of about 100 to about 170 mm. Some simulation results at 10 KeV have a delta projection range of about 30 mm and an average implantation depth (Rp) of about 131 mm. In some embodiments, the ion implantation preferably has a delta projection range of about 20 to about 160 inches, more preferably a delta projection range of about 20 to about 60 inches, with a selected average implantation depth. Including implanting ions.

  The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art to which the present invention pertains may have other specific forms without changing the technical idea and essential features thereof. It will be understood that this can be implemented. Accordingly, it should be understood that the above-described embodiments are illustrative in all aspects and not limiting.

  The present invention can be applied to a flash EEPROM device, a nonvolatile memory device, or a DRAM.

FIG. 10 is a schematic cross-sectional view showing erase and program operations in a conventional floating gate memory cell. It is a schematic sectional view showing a leakage path of a conventional continuous floating gate cell. 6 is a cross-sectional view illustrating a method of forming a gate structure of an integrated circuit device according to some embodiments of the present invention. FIG. 6 is a cross-sectional view illustrating a method of forming a gate structure of an integrated circuit device according to some embodiments of the present invention. FIG. 6 is a cross-sectional view illustrating a method of forming a gate structure of an integrated circuit device according to some embodiments of the present invention. FIG. 6 is a cross-sectional view illustrating a method of forming a gate structure of an integrated circuit device according to some embodiments of the present invention. FIG. 2 is a diagram illustrating a heat treatment for the formation of a charge storage region comprising isolated charge storage nanocrystals according to some embodiments of the present invention. 2 is a diagram illustrating a heat treatment for the formation of a charge storage region comprising isolated charge storage nanocrystals according to some embodiments of the present invention. FIG. 3 is a cross-sectional view illustrating a charge trap bilayer structure according to some embodiments of the present invention. 1 is a cross-sectional view illustrating a flash memory device including a gate structure according to some embodiments of the present invention. 2 is an energy band diagram of a flash memory device according to some embodiments of the present invention. 2 is an energy band diagram of a flash memory device according to some embodiments of the present invention. 2 is an energy band diagram of a flash memory device according to some embodiments of the present invention. FIG. 6 is a cross-sectional view illustrating a flash memory device including a gate structure according to still another embodiment of the present invention. 6 is a cross-sectional view illustrating a flash memory device including a gate structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a flash memory device including a gate structure according to still another embodiment of the present invention. 6 is a cross-sectional view illustrating a flash memory device including a gate structure according to still another embodiment of the present invention. 3 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device according to some embodiments of the present invention. 3 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device without a metal oxide capping insulating layer. 3 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device without a metal oxide capping insulating layer. 3 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device thermally treated at another temperature according to some embodiments of the present invention. 3 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device thermally treated at another temperature according to some embodiments of the present invention. 3 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device thermally treated at another temperature according to some embodiments of the present invention. 3 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device thermally treated at another temperature according to some embodiments of the present invention. 3 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device thermally treated at another temperature according to some embodiments of the present invention. FIG. 6 is a schematic cross-sectional view showing a leakage path in a separated charge storage nanocrystal floating gate. 6 is a diagram illustrating ion implantation simulation results according to some embodiments of the present invention. 6 is a flowchart illustrating operations for forming a gate structure of an integrated circuit device according to some embodiments of the present invention. FIG. 6 is a cross-sectional view illustrating a charge trap double membrane structure according to another embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a charge trapping single film structure according to still another embodiment of the present invention. 4 is an energy band diagram of a flash memory device according to another embodiment of the present invention. 4 is an energy band diagram of a flash memory device according to another embodiment of the present invention. 4 is an energy band diagram of a flash memory device according to another embodiment of the present invention. 4 is a TEM photograph showing a cross section of a charge trapping bilayer structure according to some embodiments of the present invention. 6 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device according to another embodiment of the present invention. 6 is a graph illustrating leakage current characteristics according to some embodiments of the present invention. 4 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device according to another embodiment of the present invention. 4 is a capacitance (C) -voltage (V) hysteresis curve of a flash memory device according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional process diagram illustrating a charge trap structure and a method of forming the same according to some embodiments of the present invention.

Explanation of symbols

100 substrates,
110 first insulating layer,
111 annealing,
112 Ion implantation for nanocrystal formation,
120 second insulating layer;
122 annealing,
130_NC charge trap nanocrystal,
135a, 135b tunneling layer,
140a, 140b coupling and blocking insulation layers,
150a nanocrystal embedded high dielectric constant charge trap double layer,
150b nanocrystal embedded high dielectric constant charge trap single layer,
160 control gate,
170S, 170D source, drain,
180 channels.

Claims (48)

Forming an insulating layer on the substrate;
Implanting an ion of an element selected from group IV of the periodic table into the insulating layer and having a thermal diffusivity of 0.5 cm ² / s or less;
Partitioning the insulating layer into a tunnel insulating layer below the charge storage region and a capping insulating layer above the charge storage region by forming a charge storage region in the insulating layer by implanting the ions; When,
Heat treating the substrate including the insulating layer in which the tunnel insulating layer, the charge storage region, and the capping insulating layer are partitioned to form a plurality of separated charge storage nanocrystals in the charge storage region;
Forming a gate electrode layer on the insulating layer;
A method for forming a gate structure of an integrated circuit memory device.   The insulating layer includes a first insulating layer, and further includes forming a second insulating layer including a metal oxide on the first insulating layer between the ion implantation and the heat treatment of the substrate. A method for forming a gate structure of an integrated circuit memory device according to claim 1.   The insulating layer includes at least one selected from the group consisting of oxides or oxynitrides of Al, Hf, Ti, Zr, Sc, Y, and La having a relative dielectric constant of greater than 7, The method for forming a gate structure of an integrated circuit memory device according to claim 1, wherein the selected element includes Ge.   The method for forming a gate structure of an integrated circuit memory device according to claim 1, wherein the ions are implanted with an implantation energy of 10 KeV or less.   5. The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the ions are implanted with an implantation energy of 5 KeV or more.   The method for forming a gate structure of an integrated circuit memory device according to claim 1, wherein the ions are implanted with an implantation energy of 7 KeV or more.   The method for forming a gate structure of an integrated circuit memory device according to claim 1, wherein a thickness of the insulating layer formed on the substrate is 30 nm or less.   The method for forming a gate structure of an integrated circuit memory device according to claim 1, wherein a thickness of the insulating layer formed on the substrate is 20 nm or less.   9. The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the substrate including the edge layer is heat-treated before the ion implantation.   The gate structure of the integrated circuit memory device according to claim 1, wherein the substrate including the insulating layer is heat-treated at a temperature equal to or higher than a crystallization temperature of the insulating layer before the ion implantation. Forming method.   11. The integrated circuit memory device gate structure according to claim 1, wherein the substrate including the insulating layer is heat-treated at a temperature of 950 ° C. or more in a nitrogen atmosphere before the ion implantation. Method.   After the ion implantation, the substrate including the tunnel insulating layer, the charge storage region, and the insulating layer in which the capping insulating layer is partitioned includes rapid thermal annealing at 700 ° C. to 900 ° C. for 5 to 30 minutes. A method for forming a gate structure of an integrated circuit memory device according to claim 1.   13. The method of forming a gate structure of an integrated circuit memory device according to claim 12, wherein the second rapid thermal annealing is performed at 900 to 1050 [deg.] C. for 5 to 30 minutes after the rapid thermal annealing.   The heat treatment of the substrate after the ion implantation may be performed by heating the substrate including the tunnel insulating layer, the charge storage region, and the insulating layer in which the capping insulating layer is partitioned at 900 ° C. to 950 ° C. for 5 minutes to 30 minutes. The method for forming a gate structure of an integrated circuit memory device according to claim 1, comprising performing rapid thermal annealing.   The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the insulating layer has a thickness of 30 nm or less.   The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the tunnel insulating layer has a thickness of 9 nm or less.   The gate of an integrated circuit memory device according to claim 1, wherein the ions are implanted with an average implantation depth selected based on a thickness of the insulating layer and a delta projection range of 7 nm or less. A method of forming a structure.   18. The method of forming a gate structure of an integrated circuit memory device according to claim 17, wherein the ions include implanting the ions in a delta projection range of 20 to 60 inches.   The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the insulating layer has an energy band gap exceeding 5 eV. 20. The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the ions are implanted at a dose of 1 × 10 ¹⁴ / cm ² to 2 × 10 ¹⁶ / cm ² .   21. The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the nanocrystal has a diameter of 1 nm to 7 nm, and a distance between the nanocrystals is 1 nm to 7 nm. The ion implantation includes implanting ions of the selected element with a first ion implantation energy to form a first charge storage film.
Implanting ions of the selected element with a second ion implantation energy lower than the first ion implantation energy to form a second charge storage film on the first charge storage film,
The integrated circuit according to claim 1, further comprising a region substantially free of implanted ions between the first charge storage film and the second charge storage film. A method of forming a gate structure of a memory device. The step of implanting ions includes implanting ions into the insulating layer at a plurality of different height positions compared to the substrate;
23. The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the heat treatment of the substrate has a multilayer structure in which the separated charge storage nanocrystals are overlapped.   A common gate electrode layer is formed on the gate insulating layer on the substrate before the insulating layer is formed, and the formation of the insulating layer and the ion implantation are performed on the side wall of the common gate electrode layer and the common gate electrode layer. Forming the gate electrode layer on the second insulating layer adjacent to each side surface of the common gate electrode layer and on the channel portion. The method for forming a gate structure of an integrated circuit memory device according to claim 1, comprising forming a sidewall gate.   Forming a channel region including a recess region and a step region adjacent to the recess region extending between a source region and a drain region in the substrate before forming the insulating layer; forming the insulating layer; 25. The method for forming a gate structure of an integrated circuit memory device according to claim 1, wherein the gate electrode is formed on the channel region including the recess region and the step region.   26. The method of forming a gate structure of an integrated circuit memory device according to claim 2, wherein the second insulating layer has a thickness of 10 nm or less.   27. The method of forming a gate structure of an integrated circuit memory device according to claim 2, wherein the first and second insulating layers include the same kind of material.   The first and second insulating layers include at least one selected from the group consisting of oxides or oxynitrides of Al, Hf, Ti, Zr, Sc, Y, and La, and the selected element is 28. The method of forming a gate structure of an integrated circuit memory device according to claim 2, comprising Ge.   29. The method of forming a gate structure of an integrated circuit memory device according to claim 2, wherein the second insulating layer includes atomic layer deposition and / or PECVD.   Before forming the first insulating layer, a common gate electrode layer is formed on the gate insulating layer on the substrate, and the formation of the first insulating layer, the ion implantation, and the formation of the second insulating layer are the common. Forming the common gate electrode layer on the side wall of the gate electrode layer and on the channel portion of the substrate adjacent to each side surface of the common gate electrode layer is adjacent to each side surface of the common gate electrode layer 30. The method of forming a gate structure of an integrated circuit memory device according to claim 2, further comprising forming a sidewall gate extending on the second insulating layer and on the channel portion.   Forming a channel region including a recess region and a step region adjacent to the recess region extending between the source and drain regions in the substrate before forming the first insulating layer; and forming the first insulating layer; 31. The gate structure of an integrated circuit memory device according to claim 2, wherein the ion implantation and the formation of the second insulating film and the gate electrode are performed on the channel region including the recess region and the step region. Forming method.   32. The method of forming a gate structure of an integrated circuit memory device according to claim 25, wherein the recess region includes a round portion.   33. A method of forming a gate structure of an integrated circuit memory device, comprising a non-volatile memory device or a DRAM.   34. The method of forming a gate structure of an integrated circuit memory device according to claim 1, wherein the integrated circuit memory device includes a flash memory, and the charge storage region includes a floating gate of a cell of the flash memory. Forming an insulating layer on the substrate;
The substrate including the insulating layer is heat-treated at a temperature equal to or higher than a crystallization temperature of the metal oxide insulating film;
Ge ions are implanted into the heat-treated first insulating film at an ion implantation energy of 10 KeV or less and a dose of 1 × 10 ¹⁴ / cm ² to 2 × 10 ¹⁶ / cm ² to preserve electric charge in the first insulating layer. Forming a tunnel insulating layer below the charge storage region and a capping insulating layer above the charge storage region by forming a region; and
Rapid thermal annealing of the substrate including the insulating layer at 700 ° C. to 900 ° C. for 5 to 30 minutes to form a plurality of separated charge storage nanocrystals in the charge storage region;
Forming a gate electrode layer on the insulating layer; and forming a gate structure of an integrated circuit memory device.   The insulating layer includes a first insulating layer, and further includes forming a second insulating layer including a metal oxide on the insulating layer between the ion implantation and the rapid thermal annealing, and the second insulating layer. 36. The method of forming a gate structure of an integrated circuit memory device according to claim 35, wherein the layer has a thickness of 10 nm or less. A substrate,
A tunnel insulating layer on the substrate that is part of the insulating layer on the substrate;
A charge storage region comprising a plurality of isolated nanocrystals of an element selected from group IV of the periodic table on the tunnel insulating layer and having a thermal diffusivity of 0.5 cm ² / s or less;
A capping insulating layer that is part of an insulating layer on the substrate on the charge storage region;
And a gate electrode layer on the capping insulating layer.   The insulating layer comprises a first insulating layer, and the gate structure according to claim 36 or 37, further comprising a second insulating layer interposed between the capping insulating layer and the gate electrode layer, 38. The gate structure of an integrated circuit device according to claim 37, wherein the second insulating layer includes a metal oxide and has a thickness of 10 nm or less.   39. The gate structure of an integrated circuit memory device according to claim 38, wherein the first insulating layer has a thickness of 20 nm or less.   40. The gate structure of an integrated circuit device according to claim 38 or 39, wherein the first and second insulating layers include an oxide and / or oxynitride of Al, Hf, Ti, Zr, Sc, Y, and / or La. object.   41. The gate structure of an integrated circuit memory device according to claim 37, wherein the tunnel insulating layer has a thickness of 9 nm or less.   The gate structure of the integrated circuit memory device according to any one of claims 37 to 41, wherein the nanocrystals have a diameter of 1 nm to 7 nm, and an interval between the nanocrystals is 1 nm to 7 nm.   43. The gate structure of an integrated circuit device according to claim 37, wherein the charge storage region includes a multilayer structure in which the separated charge storage nanocrystals are overlapped.   44. The integrated circuit memory device according to claim 37, wherein the integrated circuit memory device includes a nonvolatile memory device or a DRAM.   45. The integrated circuit memory device according to claim 37, wherein the integrated circuit memory device includes a flash memory device, and the charge storage region includes a floating gate of a cell of the flash memory device. A memory cell comprising the gate structure of claim 37,
The memory cell further includes a common gate electrode layer on a gate insulating layer on the substrate, and the insulating layer is adjacent to each side surface of the common gate electrode layer along a side wall of the common gate electrode layer. The memory cell includes a gate structure that extends over a channel portion of the substrate, and the memory cell further includes a sidewall gate that extends over the insulating layer adjacent to each side surface of the common gate electrode layer and over the channel portion. A memory cell comprising the gate structure of claim 37,
The memory cell further includes a channel region including a recess region and a step region adjacent to the recess region extending between the source and drain regions in the substrate, and the insulating layer includes the recess region and the step region. A memory cell comprising a gate structure extending along said channel region comprising:   48. The memory cell of claim 47, wherein the recess region includes a gate structure having a round portion.