TWI469337B - Non-volatile memory and manufacturing method thereof - Google Patents

Description

Non-volatile memory and method of manufacturing same

The present invention relates to a memory and a method of fabricating the same, and more particularly to a non-volatile memory and a method of fabricating the same.

Non-volatile memory has the advantage that it does not disappear after power-off, so many electrical products must have such memory to maintain the normal operation of the electrical products when they are turned on. In particular, flash memory has become a memory component widely used in personal computers and electronic devices because it has operations such as storing, reading, and erasing data.

For flash memory, it is generally desirable to have a higher gate coupling ratio (GCR) and transconductance (Gm) to make the memory more efficient. The gate coupling ratio and transduction value are usually related to the inter-gate dielectric layer. The thinner the thickness of the dielectric layer between the gates and the higher the dielectric constant, the higher the capacitance of the dielectric layer between the gates, and thus the gate coupling ratio and the transconductance value can be improved. In addition, increasing the area of the dielectric layer of the gate can also increase the gate coupling ratio.

However, thinner inter-gate dielectric layers tend to cause problems with reduced data retention. In addition, high dielectric constant materials are often not easily compatible with existing memory systems. In addition, increasing the area of the dielectric layer of the gate also leads to an increase in process difficulty. So how is it in the existing Effectively increasing the gate coupling ratio and transduction value in the process has become an important issue at present.

The present invention provides a non-volatile memory having a charged nitride layer.

The present invention further provides a method of fabricating a non-volatile memory that can produce a non-volatile memory having a charged nitride layer.

The invention provides a non-volatile memory comprising a gate dielectric layer, a floating gate, a control gate, a gate dielectric structure and two doped regions. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The dielectric structure of the gate is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer, and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The two doped regions are respectively disposed in the substrate on the two sides of the floating gate.

According to the non-volatile memory of the embodiment of the invention, the above-mentioned charged nitride layer contains, for example, an N-type dopant.

According to the non-volatile memory of the embodiment of the invention, the charged nitride layer contains, for example, electrons.

The invention further provides a method for fabricating a non-volatile memory, the method comprising: forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first oxide layer on the floating gate On the first oxide layer Forming a nitride layer thereon; forming a second oxide layer on the nitride layer; forming a control gate on the second oxide layer; forming a doped region in the substrate on the two sides of the floating gate; A charge treatment is performed to form a charged nitride layer.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the charge treatment described above is, for example, performing N-type dopant implantation on the nitride layer.

According to the method of fabricating a non-volatile memory according to an embodiment of the invention, the charge treatment described above is performed, for example, after forming a nitride layer and before forming a second oxide layer.

In accordance with a method of fabricating a non-volatile memory according to an embodiment of the invention, the charge treatment described above is performed, for example, after forming a control gate and before forming a doped region.

According to the method of fabricating a non-volatile memory according to an embodiment of the invention, the charge treatment described above is performed simultaneously with the step of forming a doped region, for example.

According to the method of fabricating a non-volatile memory according to an embodiment of the invention, the charge treatment described above is, for example, injecting electrons into the nitride layer.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the charge treatment is performed, for example, after forming a doped region, and the charge treatment is, for example, applying a voltage greater than 7 MV per centimeter to the control gate. The electrons are injected into the nitride layer.

Based on the above, after forming the nitride layer in the inter-gate dielectric structure, the nitride layer is subjected to a charge treatment to form a charged nitride layer, thereby increasing the conductivity of the nitride layer, thereby improving non-volatileness. The gate coupling ratio and transduction value of the memory.

The above described features and advantages of the present invention will be more apparent from the following description.

Hereinafter, a method of producing the non-volatile memory of the present invention will be described by way of examples. In the method of fabricating the non-volatile memory of the present invention, by forming the inter-gate dielectric structure having the charged nitride layer, the gate coupling ratio and the transduction value of the non-volatile memory can be effectively improved. In particular, the step of forming a charged nitride layer is not limited to use in the process of the non-volatile memory structure described below. In other words, the step of forming a charged nitride layer in the present invention can be used in the process of any form of non-volatile memory structure as long as the non-volatile memory structure has an oxide/nitride/oxide ( O/N/O) The dielectric structure of the gate can be used.

1A-1D are cross-sectional views showing a process of fabricating a non-volatile memory according to an embodiment of the invention. First, referring to FIG. 1A, a dielectric layer 102 is formed on the substrate 100. The material of the dielectric layer 102 is, for example, an oxide. The formation method of the dielectric layer 102 is, for example, a thermal oxidation method or a chemical vapor deposition method. Then, a conductor layer 104 is formed on the dielectric layer 102. The material of the conductor layer 104 is, for example, polycrystalline germanium. The method of forming the conductor layer 104 is, for example, a chemical vapor deposition method.

Then, referring to FIG. 1B, the conductor layer 104 and the dielectric layer 102 are patterned to form a floating gate 104a and a gate dielectric layer 102a. Next, the oxide layer 106, the nitride layer 108 and the oxygen are conformally formed on the substrate 100. Compound layer 110. The method of forming the oxide layer 106 is, for example, a chemical vapor deposition method. The thickness of the oxide layer 106 is, for example, between 15 Å and 60 Å, preferably between 30 Å and 50 Å, and more preferably 40 Å. The method of forming the nitride layer 108 is, for example, a chemical vapor deposition method. The thickness of the nitride layer 108 is, for example, between 15 Å and 100 Å, preferably between 30 Å and 50 Å, and more preferably 40 Å. The thickness of the oxide layer 110 is, for example, between 15 Å and 60 Å, preferably between 30 Å and 50 Å, and more preferably 50 Å.

Next, referring to FIG. 1C, the nitride layer 108 is subjected to a charge treatment 112 to form a charged nitride layer 114. In the present embodiment, the charge treatment 112 is, for example, N-type dopant implantation of the nitride layer 108. The above N-type dopant may be phosphorus or boron.

Thereafter, referring to FIG. 1D, a conductor layer (not shown) covering the oxide layer 110 is formed on the substrate 100. The material of the above conductor layer is, for example, polycrystalline germanium, and the formation method thereof is, for example, a chemical vapor deposition method. Then, a patterning process is performed to remove a portion of the conductor layer to form the control gate 116. In addition, during the patterning process, part of the oxide layer 110, the charged nitride layer 114 and the oxide layer 106 are simultaneously removed to form the oxide layer 110a, the charged nitride layer 114a and the oxide layer 106a. . The oxide layer 110a, the charged nitride layer 114a and the oxide layer 106a form an inter-gate dielectric structure 118 between the floating gate 104a and the control gate 116. Thereafter, doped regions 120 are respectively formed in the substrates 100 on both sides of the floating gate 104a to complete the fabrication of the non-volatile memory 10 of the present embodiment. The method of forming the doping region 120 is, for example, performing an ion implantation process.

In the non-volatile memory 10, due to the inter-gate dielectric structure 118 The nitride layer is charged, so the nitride layer has an internal electric field (internal E-field). As a result, the trapping barrier of the electrons becomes lower, so that the electrons have a greater probability of being randomly moved, thereby increasing the conductivity of the nitride layer. Since the conductivity of the nitride layer is increased, it can be considered that the electrical thickness of the nitride layer is reduced, and thus has a higher capacitance value. Since the nitride layer in the gate dielectric structure 118 has a higher capacitance value, the gate coupling ratio and the transconductance value of the non-volatile memory 10 are improved.

2 is a comparison diagram of the electrical thickness of the inter-gate dielectric structure (having a charged nitride layer) and the general inter-gate dielectric structure (the nitride layer is not charged) in the present embodiment. The gate dielectric structure of the present embodiment has the same actual thickness as the general gate dielectric structure, but it can be seen from FIG. 2 that the gate dielectric structure of the present embodiment has a thin electrical thickness, which is represented by The inter-gate dielectric structure of the present embodiment can have a large capacitance value, so the non-volatile memory of the present embodiment can have a higher gate coupling ratio.

3 is a graph showing the relationship between the transduction value of the non-volatile memory and the threshold voltage (Vt) of the present embodiment. As can be seen from Figure 3, as the threshold voltage increases, the transduction value also increases. In other words, the non-volatile memory of the present embodiment can easily have a higher transduction value.

In particular, in the present embodiment, the charged nitride layer 114 is formed by subjecting the nitride layer 108 to a charge treatment 112 after forming the oxide layer 110. However, the invention is not limited thereto. In other embodiments, the nitride layer 108 may also be subjected to a charge treatment 112 at other timings after the formation of the nitride layer 108. For example, you can The nitride layer 108 is subjected to a charge treatment in the following case: in an embodiment, the nitride layer 108 may be subjected to a charge treatment 112 to form a charged nitride layer 114 immediately after the formation of the nitride layer 108, as shown in the figure. 4; in an embodiment, the patterned nitride layer 108 may be subjected to a charge treatment 112 to form a charged nitride layer 114a immediately after forming the control gate 116, as shown in FIG. 5; In one embodiment, the patterned nitride layer 108 may be subjected to a charge treatment 112 to form a charged nitride layer 114a during formation of the doped region 120, as shown in FIG.

In addition, in each of the above embodiments, the charged nitride layer is formed by N-type dopant implantation of the nitride layer in the gate dielectric structure. However, the invention is not limited thereto. In another embodiment, after the general non-volatile memory is formed in the existing process, a voltage is applied to the control gate, and the electron is injected into the gate by means of Fowler-Nordheim tunneling. A charged nitride layer is formed in the nitride layer of the dielectric structure.

7A-7B are cross-sectional views showing a process of fabricating a non-volatile memory according to another embodiment of the invention. First, referring to FIG. 7A, the non-volatile memory 70 is formed in a manner similar to that described in FIGS. 1A through 1D except that the nitride layer 108 is not N-type dopant implanted after formation of the nitride layer 108. The nitride layer 108a is not charged.

Thereafter, referring to FIG. 7B, a charge treatment 122 is performed, a voltage V is applied to the control gate 116, and electrons are implanted into the nitride layer 108a by FN tunneling to form a charged nitride layer 124 to complete the embodiment. The production of non-volatile memory 70a. In the present embodiment, the voltage V is, for example, greater than 7 MV per centimeter.

Figure 8 is a graph showing the relationship between the charged nitride layer and the improved memory efficiency using a Nb cell. As shown in FIG. 8, after the voltage is applied by the FN tunneling method, as the amount of change in the threshold voltage (ΔVt) increases, the transduction value tends to gradually increase.

In summary, after forming the nitride layer in the inter-gate dielectric structure, the nitride layer is subjected to charge treatment to form a charged nitride layer, thereby increasing the conductivity of the nitride layer and thereby improving The capacitance value of the dielectric structure of the gate. Since the dielectric structure of the gate has a high capacitance value, the non-volatile memory of the present invention can have a high gate coupling ratio and a transconductance value.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 70, 70a‧‧‧ non-volatile memory

100‧‧‧Base

102‧‧‧ dielectric layer

102a‧‧‧gate dielectric layer

104‧‧‧Conductor layer

104a‧‧‧Floating gate

106, 106a, 110, 110a‧‧‧ oxide layer

108, 108a‧‧‧ nitride layer

112, 122‧‧‧ with charge treatment

114, 114a, 124‧‧‧Charged nitride layer

116‧‧‧Control gate

118‧‧‧Intermittent dielectric structure

120‧‧‧Doped area

1A-1D are cross-sectional views showing a process of fabricating a non-volatile memory according to an embodiment of the invention.

2 is a comparison diagram of the electrical thickness of the inter-gate dielectric structure (having a charged nitride layer) and the general inter-gate dielectric structure (the nitride layer is not charged) in the present embodiment.

FIG. 3 is a transduction value and a critical power of the non-volatile memory of the embodiment. Diagram of the threshold voltage (Vt).

4 to 6 are schematic cross-sectional views showing a charge treatment of a nitride layer in various embodiments of the present invention.

7A-7B are cross-sectional views showing a process of fabricating a non-volatile memory according to another embodiment of the invention.

Figure 8 is a graph showing the relationship between the charged nitride layer and the improved memory efficiency using Nbit cells.

100‧‧‧Base

102a‧‧‧gate dielectric layer

104a‧‧‧Floating gate

106, 110‧‧‧ oxide layer

112‧‧‧with charge treatment

114‧‧‧Charged nitride layer

Claims (3)

A non-volatile memory comprising: a gate dielectric layer disposed on a substrate; a floating gate disposed on the gate dielectric layer; and a control gate disposed on the floating gate; The gate dielectric structure is disposed between the control gate and the floating gate, wherein the gate dielectric structure comprises: a first oxide layer disposed on the floating gate; a second oxide a layer disposed on the first oxide layer; and a charged nitride layer disposed between the first oxide layer and the second oxide layer, wherein the entire charged nitride layer contains electrons; The two doped regions are respectively disposed in the substrate on the two sides of the floating gate. A method for fabricating a non-volatile memory, comprising: forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first oxide layer on the floating gate Forming a nitride layer on the first oxide layer; forming a second oxide layer on the nitride layer; forming a control gate on the second oxide layer; and the floating gate 2 Forming a doped region in the substrate on the side; and performing a charge treatment on the nitride layer to form a charged nitrogen a layer of material, wherein the charge treatment comprises implanting electrons throughout the nitride layer. The method of fabricating the non-volatile memory of claim 2, wherein the charging treatment is performed after forming the doping region, and the charging treatment comprises applying a voltage greater than 7 MV per centimeter to the control gate. To inject electrons into the nitride layer.