JP2007281270A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device having a low on-resistance and being capable of improving reverse characteristics and the semiconductor device. <P>SOLUTION: The semiconductor device has an n<SP>+</SP>-type hetero semiconductor region 3 arranged adjacently to a gate electrode 16, while being brought into contact with a gate insulating film 5 as a hetero semiconductor region hetero-joined with an n-type SiC drain region 2 formed on an SiC-board region 1, and connected to a source electrode 14 and a p<SP>+</SP>-type hetero semiconductor region 9 arranged on the SiC drain region 2. The n<SP>+</SP>-type hetero semiconductor region 3 is formed by patterning, using a cap insulating film 6 formed on the upper section of the gate electrode 16 and the upper section of the gate insulating film 5 in the vicinity of the gate electrode 16 as a mask. Then, the p<SP>+</SP>-type hetero semiconductor region 9 is formed by introducing p-type impurities to the hetero semiconductor region formed on the SiC drain region 2 exposed by an etching. The forming process of the p<SP>+</SP>-type hetero semiconductor region 9 is formed after forming at least the gate insulating film 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

As a conventional technique related to a field effect transistor using a hetero interface, there is a technique described in Japanese Patent Laid-Open No. 2003-318398 “Silicon Carbide Semiconductor Device” disclosed in Patent Document 1. The technique described in Patent Document 1 is such that post-annealing is performed on a polycrystalline silicon (poly-Si) layer formed on a semiconductor substrate to form a low-resistance hetero semiconductor region close to the gate electrode. A control voltage is applied to the gate electrode to control the thickness of the energy barrier at the heterojunction interface, and when the element is on, carriers are passed by a tunnel current. A field effect transistor using such a heterointerface has a feature that a device structure which is not easily affected by channel resistance can be formed because there is no large channel region like a MOSFET. A power semiconductor switch having a high breakdown voltage and a low on-resistance can be provided.
JP 2003-318398 A

  However, in the prior art of Patent Document 1, it is possible to improve the driving force by reducing the on-resistance by performing post annealing on the polycrystalline silicon layer, but on the other hand, the reverse breakdown voltage is deteriorated, There is a problem that it is difficult to achieve both reduction in on-resistance and improvement in reverse breakdown voltage.

  That is, a semiconductor device manufactured by a conventional manufacturing method forms a semiconductor substrate in which silicon carbide (SiC) and polycrystalline silicon (poly-Si) that are ohmic-connected to a drain electrode are heterojunction as a semiconductor substrate, In a part of the heterojunction surface, the gate electrode is arranged close to the gate insulating film.

Here, the forward current when the element is on flows along the interface between the gate insulating film and polycrystalline silicon and the interface between the gate insulating film and silicon carbide (SiC). It should be noted that since the structure has no large channel region extending to several μm, it is not as affected by the electron mobility at the interface as the MOSFET, but the higher the electron mobility at the interface is advantageous. Therefore, when forming the gate insulating film, high-temperature heat treatment (annealing) is performed in an N ₂ O atmosphere or the like to reduce the interface state. In some cases, the polycrystalline silicon layer is subjected to high-temperature heat treatment in order to control the crystal grain size of the polycrystalline silicon serving as a current path and further reduce the on-resistance.

  However, there is a concern that such high-temperature heat treatment adversely affects the heterojunction interface that determines the off characteristics of the device. Specifically, there is a concern about a decrease in reverse breakdown voltage.

  In addition, in order to produce a device structure that overcomes such problems with a fine pattern, a self-alignment process that eliminates margins such as mask alignment as much as possible is indispensable. No device structure or manufacturing process was found.

  The present invention has been made in view of such a problem, and the problem to be solved by the present invention is to manufacture a semiconductor device that manufactures a semiconductor device having low on-resistance and capable of greatly improving reverse characteristics. A method and a semiconductor device thereof are provided.

  In order to solve the above-described problems, the present invention provides a hetero semiconductor region that is heterojunction with a semiconductor substrate and is connected to a source electrode, and is disposed in contact with the gate insulating film and in proximity to the gate electrode. A semiconductor device for manufacturing a semiconductor device having a structure having a first hetero semiconductor region having the same conductivity type and a second hetero semiconductor region having a conductivity type different from that of the semiconductor substrate, the second hetero semiconductor region being disposed on the semiconductor substrate. In the manufacturing method, the first hetero semiconductor region is formed using the cap insulating film formed above the gate electrode and a part of the gate insulating film adjacent to the gate electrode as a mask. Forming by patterning a layer of a first hetero semiconductor region formed proximate to a gate electrode, while said second hetero semiconductor region is formed by said semiconductor substrate Is formed by introducing impurities of different conductivity types into the hetero semiconductor region formed on the semiconductor substrate, and the step of forming the second hetero semiconductor region is at least from the step of forming the gate insulating film Is also featured later.

  According to the present invention, after the high-temperature heat treatment is performed on the gate insulating film, the second hetero semiconductor region having a conductivity type different from that of the semiconductor substrate and dominantly determining the element off characteristics can be formed. Since the first hetero semiconductor region having the same conductivity type as that of the semiconductor substrate can be reliably formed in a narrow region by a self-alignment process, the device has low on-resistance and off characteristics (reverse direction) while achieving downsizing. Thus, a semiconductor device capable of significantly improving the characteristics can be provided.

  Hereinafter, an example of a semiconductor device manufacturing method and a semiconductor device according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
First, a first embodiment of a device structure of a semiconductor device manufactured by the manufacturing method of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a first embodiment of a device cross-sectional structure of a field effect transistor which is a semiconductor device according to the present invention. The semiconductor device 100 of FIG. 1 corresponds to a cross section in which two unit cells are arranged to face each other. Actually, a plurality of these cells are connected in parallel to form an element. This cross-sectional structure will be described as a representative.

(Configuration example)
First, the structure of the semiconductor device 100 in FIG. 1 showing an example of a semiconductor device according to the present invention will be described. On the first main surface of SiC (silicon carbide, hereinafter abbreviated as SiC) substrate region 1 of high-density N-type (N + type: hereinafter, high-density is indicated by “+”), low-density N-type (N -Type: SiC drain region 2 of low density is shown below ("-"). N− type SiC drain region 2 is formed of an epitaxial layer grown on N + type SiC substrate region 1. Here, the N + type SiC substrate region 1 and the N− type SiC drain region 2 constitute a semiconductor substrate of the first conductivity type (here, N type).

  There are several polytypes (polycrystalline forms) of SiC. Here, a description will be given using typical 4H—SiC (four-layer hexagonal SiC). However, other 6H—SiC (6-layer hexagonal SiC) and 3C—SiC (3-layer cubic SiC) may be used. In the present embodiment and the following embodiments, the N type is described as the first conductivity type and the P type is described as the second conductivity type. The first conductivity type is the same conductivity type as the semiconductor substrate. The second conductivity type means a conductivity type different from that of the semiconductor substrate.

  In FIG. 1, the concept of the thicknesses of the N + type SiC substrate region 1 and the N− type SiC drain region 2 is omitted. Actually, the N + type SiC substrate region 1 has a thickness of several hundreds μm, and the N− type SiC drain region 2 is about several μm to several tens of μm.

  A groove portion 7 having a predetermined shape is formed on a predetermined region (peripheral portion) on the surface on the first main surface side (the side opposite to the N + type SiC substrate region 1) of the N− type SiC drain region 2. Then, a P + type hetero semiconductor region 9 made of polycrystalline silicon (poly Si) is formed as a second conductivity type (P type) second hetero semiconductor region 9 in contact with the drilled groove 7. Has been. SiC and polycrystalline silicon have different band gaps and different electron affinities. Accordingly, a heterojunction plane is formed at the junction interface between the N− type SiC drain region 2 and the P + type hetero semiconductor region 9 of polycrystalline silicon (because the polycrystalline silicon region is referred to as a hetero semiconductor region). Is).

  Further, on the first main surface side of the N− type SiC drain region 2 (on the side opposite to the N + type SiC substrate region 1), on a part of the first main surface where no groove 7 is formed. The N + type hetero semiconductor region 3 is formed as the first conductivity type (N type) first hetero semiconductor region 3 in contact with the N − type SiC drain region 2. The N + type hetero semiconductor region 3 also has a region that partially overlaps the P + type hetero semiconductor region 9. That is, the N + -type hetero semiconductor region 3 and the P + -type hetero semiconductor region 9 have overlapping portions in the direction from the source electrode 14 to the drain electrode 13.

  Here, an example is shown in which the layers of the N + -type hetero semiconductor region 3 and the P + -type hetero semiconductor region 9 are in contact with each other with overlapping portions, but the P + -type hetero semiconductor region 9 is in contact with the N + -type. As long as it is formed at a deeper position in the N− type SiC drain region 2 than the hetero semiconductor region 3 and is in contact with the N + type hetero semiconductor region 3, it may be formed in any shape or state.

  Here, what is characteristic is that the N + -type hetero semiconductor region 3 having the same conductivity type as that of the semiconductor substrate is connected to the source electrode 14 on the side surface of the end portion.

  In addition, a gate electrode 16 is formed which is located close to a part of the junction between the N− type SiC drain region 2 and the N + type hetero semiconductor region 3 via the gate insulating film 5. A cap insulating film 6 is formed on the gate electrode 16. P + type hetero semiconductor region 9 is directly connected to source electrode 14.

  Further, the N + type hetero semiconductor region 3 is characterized in that a contact portion in contact with the source electrode 14 is formed on the side surface of the end portion, and the contact portion is disposed near the gate insulating film 5. It is a point. As a result, when the N + type hetero semiconductor region 3 is used as a current path when the element is turned on, the lead region extending in the lateral direction (that is, the surface of the N + type hetero semiconductor region 3 is in contact with the lower surface of the source electrode 14). As in the case of providing a laterally extending region below the source electrode 14, there is no useless region, and the structure is advantageous for miniaturization.

  A drain electrode 13 is electrically ohmically connected to the back surface of the N + type SiC substrate region 1 with low resistance. The gate electrode 16 is insulated and separated from the source electrode 14 by the cap insulating film 6. The P + type hetero semiconductor region 10 is present on the cap insulating film 6, and the hetero semiconductor region 8 into which no impurity is introduced is present on the side wall of the cap insulating film 6, but the P + type hetero semiconductor region is present. Neither 10 nor the hetero semiconductor region 8 is a region that does not function as a current path functioning as a field effect transistor, and may be essentially absent. These are regions that are produced in a secondary manner in the manufacturing process described below.

(Example of manufacturing process)
Next, a process for manufacturing the field effect transistor according to the present embodiment will be described with reference to each process chart of FIGS.

  First, in the first step of FIG. 2 (semiconductor substrate forming step, first hetero semiconductor region layer forming step), an N− type SiC drain region 2 is epitaxially grown on the first main surface of the N + type SiC substrate region 1. Thus, a semiconductor substrate is formed. Further, after the surface of the N− type SiC drain region 2 is cleaned by pretreatment or the like, the first conductivity type first hetero semiconductor region 3 which is the same conductivity type as the semiconductor substrate is formed. As an N + type hetero semiconductor region layer, a polycrystalline silicon (poly Si) layer 3 (denoted by the same reference numeral 3 as the first hetero semiconductor region 3) is deposited. A typical thickness of the polycrystalline silicon layer 3 is in the range of several hundreds of μm to several μm.

  After the polycrystalline silicon layer 3 is deposited, heat treatment at a high temperature not exceeding 1300 ° C. is performed so as to control the size of the grain boundary of the polycrystalline silicon and to make the current path when the device is on low resistance. There is a case. Thereafter, an impurity for making the N + type is introduced into the polycrystalline silicon layer 3. As a method for introducing the N + type impurity, an ion implantation method may be used, or a deposition diffusion method (solid phase diffusion from an impurity-containing deposition layer), a vapor phase diffusion method, or the like may be used.

  In the next second step (gate insulating film layer forming step) of FIG. 3, in order to form the gate electrode 16 at a predetermined desired position on the first main surface side of the N− type SiC drain region 2, An exposed region 4 that exposes the N− type SiC drain region 2 (in FIG. 3, a region at the center of the first main surface of the N− type SiC drain region 2) is provided, and N + located in the exposed region 4 The type hetero semiconductor region layer, that is, the polycrystalline silicon layer 3 is etched away. Here, the case where only the etching is performed so as to expose the surface of the low-density N-type (N−) SiC drain region 2 and the N− SiC drain region 2 is not etched will be described. The first main surface of the SiC drain region 2 of the mold may be etched into a groove shape.

Thereafter, a gate insulating film 5 is formed on the first main surface of N− type SiC drain region 2 (exposed region 4 where N− type SiC drain region 2 is exposed) and N + type hetero semiconductor region 3. A gate insulating film layer (denoted by the same reference numeral 5 as the gate insulating film 5) is deposited. A typical thickness of the gate insulating film layer 5 is in the range of several hundred to several thousand. Thereafter, the interface state at the junction interface between the gate insulating film layer 5 and the low-density N-type (N−) SiC drain region 2 or at the junction interface between the gate insulating film layer 5 and the N + -type hetero semiconductor region 3. In order to reduce the temperature, for example, a high-temperature heat treatment may be performed in an NO or N ₂ O atmosphere at a temperature of, for example, 900 ° C. to 1300 ° C. and for a time of about several tens of minutes.

In the next third step (gate electrode forming step) in FIG. 4, polycrystalline silicon for forming the gate electrode 16 is first thickly stacked on the gate insulating film layer 5, and then an N + type hetero semiconductor region layer is formed. That is, the deposited polycrystalline silicon is etched back to form a gate electrode 16 until the trench of the gate insulating film layer 5 after the polycrystalline silicon layer 3 is removed by etching is filled. At this time, the planarization of the gate electrode 16 may be performed by chemical etching or physical polishing. Also, CMP (Chemical Mechanical
Polish) may be used.

  In the next fourth step (cap insulating film forming step) in FIG. 5, by oxidizing the gate electrode 16, a part of the gate electrode 16 and the polycrystalline silicon layer 3 (one adjacent to the gate electrode 16). The cap insulating film 6 is locally thickly formed so as to cover the region).

  In the next fifth step of FIG. 6 (first half step of the first hetero semiconductor region forming step), using the cap insulating film 6 as a mask, the gate insulating film layer 5, the polycrystalline silicon layer 3 of the N + type hetero semiconductor region layer, The surface layer portion of the N− type SiC drain region 2 is etched. At this time, as described above, the cap insulating film 6 is formed so as to grow laterally outward with respect to the gate electrode 16 (formed so as to grow in a so-called bird's beak shape), and the cap insulating film is formed. The polycrystalline silicon layer 3 is left in a narrow region at the bottom of the ridge 6 and is formed as a first hetero semiconductor region 3 having a narrow predetermined size.

  In the next sixth step (heterosemiconductor region forming step) in FIG. 7, a polycrystalline silicon layer (heterosemiconductor) which is a heterosemiconductor region 8 into which impurities are not introduced so as to cover the entire upper surface of the structure in FIG. (Denoted by the same reference numeral 8 as region 8).

  In the next seventh step of FIG. 8 (the first half step of the second hetero semiconductor region forming step), the conductivity type is different from the first conductivity type semiconductor substrate on the polycrystalline silicon layer 8 deposited in the sixth step of FIG. Impurities are introduced so as to be P + types of different second conductivity types. An ion implantation method is most suitable as a method for introducing impurities. As a result, impurities are introduced into the surface of the polycrystalline silicon layer 8, and the second hetero semiconductor region 9, that is, the P + type hetero semiconductor region 9 is formed in a region in contact with the surface of the N − -type SiC drain region 2. A P + type hetero semiconductor region 10 is formed in a region in contact with the cap insulating film 6.

  However, the multi-layer formed in contact with the peripheral portion (that is, the side surface portion) of each of the cap insulating film 6, the gate insulating film 5, the first hetero semiconductor region 3, and the groove portion 7 of the N− type SiC drain region 2. Impurities are not introduced into the side wall portion of the crystalline silicon layer 8. That is, in this state, the narrow first hetero semiconductor region 3 formed in the lower part of the cap insulating film 6 is surrounded by the polycrystalline silicon layer 8 into which no impurity is introduced.

In the next eighth step of FIG. 9 (the second half step of the first hetero semiconductor region forming step and the second half step of the second hetero semiconductor region forming step), RTA (Rapid
Thermal heating is performed for a short time called Thermal Anneal. Then, the N + -type hetero semiconductor region 3 becomes a solid phase diffusion source, and the N-type impurity in the high-density N + -type hetero semiconductor region 3 is solidified into the polycrystalline silicon layer 8 surrounding the periphery and not doped with impurities. The phase diffused and the diffused region becomes the N + -type region 11, and the first hetero semiconductor region 3 is formed in a final shape by forming the side surface portion of the first hetero semiconductor region 3. At the same time, in the P + -type hetero semiconductor region 9, P-type impurities are solid-phase diffused into the polycrystalline silicon layer 8 which is located adjacent to the side wall portion in the lateral direction and into which impurities are not introduced. The second hetero semiconductor region 9 whose surface in contact with the SiC drain region 2 of the type is all converted to P + type to become a P + type region 12 and is in contact with the lower side of the first hetero semiconductor region 3 so as to overlap. As a final shape.

  In the last ninth step (source electrode formation step, drain electrode formation step) in FIG. 10, the entire area of the second hetero semiconductor region on the first main surface side of the P + type hetero semiconductor region 9 and the P + type hetero semiconductor region 10. A source electrode 14 made of metal or the like is formed over the surface, and is electrically connected to the surface layer portion of the P + type hetero semiconductor region 9 and the side surface portion of the N + type hetero semiconductor region 3 with low resistance. The Furthermore, a drain electrode 13 made of a metal or the like is formed on the back surface side of the N + type SiC substrate region 1 so as to form a low resistance ohmic connection over the entire surface. That is, as described above in the structure of FIG. 1, the N + type hetero semiconductor region 3 is the side wall of the N + type region 11 obtained as a result of lateral solid phase diffusion of N type impurities in the eighth step of FIG. , In contact with the source electrode 14.

  The device of the present embodiment is completed through the above steps.

  In the manufacturing process shown in FIGS. 2 to 10, the P + -type hetero semiconductor region 9 as the second hetero semiconductor region is subjected to a heat treatment process for the gate insulating film 5 (FIG. 3) as described in the seventh process of FIG. Formed after the heat treatment step described in the description of the second step. In this way, since the P + -type hetero semiconductor region 9 which is the second hetero semiconductor region that dominantly determines the off characteristics of the device is formed after the heat treatment of the gate insulating film 5, low on-resistance As a result, the off-characteristic (reverse breakdown voltage characteristic) of the element can be greatly improved.

  Further, as described in the first step of FIG. 2, the N + type hetero semiconductor region 3 that is the first hetero semiconductor region is subjected to heat treatment before the formation of the P + type hetero semiconductor region 9 that is the second hetero semiconductor region. May be given. In this way, since the P + type hetero semiconductor region 9 which is the second hetero semiconductor region can be formed after the heat treatment of the N + type hetero semiconductor region 3 which is the first hetero semiconductor region, the low on-state can be formed. The effect that the off-characteristics of the element can be greatly improved while realizing the resistance appears.

  Furthermore, in the present invention, as a self-alignment process, the N + type hetero semiconductor region 3 which is the first hetero semiconductor region is narrowly formed without unnecessarily extending in the lateral direction, and the second hetero semiconductor is formed. Since the P + type hetero semiconductor region 9 which is a region can be formed in the vicinity of the gate electrode 16, the basic cell of the element can be miniaturized, which has the effect of greatly contributing to the reduction of the on-resistance.

(Operation example)
Next, the operation of the field effect transistor manufactured by the manufacturing method of this embodiment will be described with an effect.

  The basic on / off operation is the same as in the conventional example. When the voltage applied to the gate electrode 16 is not more than a certain threshold voltage with respect to the source electrode 14, the element is in an off state. In this state, even if a voltage equal to or lower than the element breakdown voltage is applied to the drain electrode 13, a relatively large energy barrier exists at the heterojunction interface between the P + type hetero semiconductor region 9 and the N− type SiC drain region 2. , Carrier flow is blocked. Due to the voltage applied between the drain electrode 13 and the source electrode 14, the depletion layer extends to the N− type SiC drain region 2, and the off characteristics are maintained between the drain electrode 13 and the source electrode 14. The height of this energy barrier is determined by the band structure of the heterojunction between the N− type SiC drain region 2 and the P + type hetero semiconductor region 9, and is the Fermi level of the polycrystalline silicon layer, in other words, the P + type hetero semiconductor region 9. Depends on the impurity density.

  Next, when the voltage applied to the gate electrode 16 becomes a certain threshold voltage or higher with respect to the source electrode 14, the element is turned on. The electric field from the gate electrode 16 reduces the thickness of the barrier at least at the portion in contact with the gate insulating film 5 at the junction interface between the N + type hetero semiconductor region 3 and the N− type SiC drain region 2 so that carriers can pass through the tunnel current. become. As a result, a current flows between the drain electrode 13 and the source electrode 14. Also, as described in the manufacturing steps of FIGS. 2 to 10, since the interface state is reduced by the high-temperature heat treatment to the gate insulating film 5, the electron mobility is improved and a low on-resistance element is obtained. It is done.

  In the present embodiment, for example, a P + type hetero semiconductor region 9 of the second conductivity type (P type in the present embodiment) that predominates the element off characteristics is subjected to high-temperature heat treatment on the gate insulating film 5. Since it can be formed after being performed, the effect of greatly improving the off characteristics (reverse characteristics) of the element can be obtained while realizing low on-resistance.

  Further, after the high-temperature heat treatment is performed on, for example, the N + type hetero semiconductor region 3 of the first conductivity type (N type in the present embodiment), for example, the P + type of the second conductivity type (P type in the present embodiment). Since the hetero semiconductor region 9 is formed, an effect that the off characteristics of the element can be significantly improved while realizing a low on-resistance can be obtained.

  Further, structurally, the first conductivity type N + type hetero semiconductor region 3 and the N + type region 11 (both of these regions are combined to form a final N + type hetero semiconductor region) serving as current paths. Since it does not have a uselessly extending region in the lateral direction, it is advantageous for miniaturization of the device, and an effect that a device with a smaller on-resistance and a smaller size can be realized.

(Second embodiment)
FIG. 11 shows a device cross-sectional structure of a field effect transistor according to the second embodiment of the semiconductor device of the present invention. The cross-sectional structure of the semiconductor device 200 shown in FIG. 11 corresponds to a cross-sectional structure in which two unit cells are arranged to face each other, similarly to the structure shown in FIG. Since the basic configuration is the same as that described with reference to FIG. 1, only the differences from FIG. 1 will be described below.

(Configuration example)
In the semiconductor device 200 shown in FIG. 11, on the first main surface side of the N − -type SiC drain region 2, as in the case of FIG. A P + type hetero semiconductor region 9 which is a hetero semiconductor region is formed in contact with the bottom surface and the side surface of the groove portion 7. Here, unlike the case of FIG. 1, in the semiconductor device 200 of the present embodiment, further, in the vicinity of the surface layer portion of the first main surface of the N− type SiC drain region 2 of the semiconductor substrate, for example, in the groove portion 7. The electric field relaxation region 15 for relaxing the drain electric field of the drain electrode 13 applied to the junction between the N− type SiC drain region 2 and the N + type hetero semiconductor region 3 is formed in the N− type SiC drain region 2. Is formed. The electric field relaxation region 15 is, for example, a semiconductor region, a high resistance body, or an insulator having a conductivity type different from that of the semiconductor substrate, and is connected to the source electrode 14 via the second conductivity type P + type hetero semiconductor region 9. It is connected.

(Example of manufacturing process)
Next, a process for manufacturing the field effect transistor according to the present embodiment will be described with reference to each process chart of FIGS. Basically, it is the same as the manufacturing process described in the first embodiment, and only the ion implantation process (that is, the electric field relaxation region forming process) of the sixth process in FIG. 17 is added. Here, the process from the first process in FIG. 12 to the fifth process in FIG. 16 is exactly the same as the process from the first process in FIG. 2 to the fifth process in FIG. 6 described in the first embodiment. Omitted. Thereafter, in the ion implantation step of the sixth step of FIG. 17, the N − type SiC drain region 2 is exposed by etching using the cap insulating film 6 as a mask. Impurities such as P-type boron are introduced into the entire surfaces of both the SiC drain region 2 and the cap insulating film 6 by means such as ion implantation. Thus, the second conductivity type (P type) electric field relaxation region 15 is formed along the groove portion 7 of the first conductivity type (N type) N-type SiC drain region 2.

  The subsequent process from the seventh step in FIG. 18 to the ninth process in FIG. 20 is the same as the sixth process in FIG. 7 to the eighth process in FIG. 9 described in the first embodiment. The only difference is that the high-resistance layer made of impurities introduced in the sixth step is formed as the electric field relaxation region 15 in the N− type SiC drain region 2 along the groove portion 7.

  The electric field relaxation region 15 formed in the vicinity of the surface layer portion of the semiconductor substrate along the groove portion 7 of the N− type SiC drain region 2 is the conductivity type of the semiconductor substrate (for example, the N type of the SiC drain region 2). A semiconductor region into which an impurity of a different conductivity type (for example, P type) is introduced may be formed, or a high resistance body or an insulator may be formed.

  Although not shown, in the last step, as in FIG. 10 of the first embodiment, the first of the P + type hetero semiconductor region 9 and the P + type hetero semiconductor region 10 which are the first hetero semiconductor regions. A source electrode 14 made of a metal or the like is formed over the entire main surface, and is electrically connected to the P + type hetero semiconductor region 9 and the N + type hetero semiconductor region 3 with low resistance. On the other hand, a drain electrode 13 made of a metal or the like is formed on the back surface side of the N + type SiC substrate region 1 so as to form a low-resistance ohmic connection over the entire surface.

(Operation example)
Next, the operation of the field effect transistor manufactured by the manufacturing method of this embodiment will be described with an effect.

  The basic effect is the same as that described in the first embodiment. However, in the present embodiment, the electric field relaxation region 15 formed on the lower layer side of the P + type hetero semiconductor region 9 is formed in the semiconductor substrate composed of the N + type SiC substrate region 1 and the N− type SiC drain region 2. It is formed along the groove 7 at a position deeper than the heterojunction interface of the current path. As a result, when the element is off, when a voltage is applied to the drain electrode 13 with reference to the source electrode 14, the depletion layer extending to the N − -type SiC drain region 2 extends to the region immediately below the gate electrode 16. As a result, a unique effect is obtained in that the off characteristics of the device can be further improved.

  In each of the embodiments described above, the semiconductor substrate is made of silicon carbide (SiC) and the hetero semiconductor region is made of polycrystalline silicon (poly Si). However, the present invention is not limited to such a case. . The semiconductor substrate may be made of either gallium nitride (GaN) or diamond, and the hetero semiconductor region is made of single crystal silicon, amorphous silicon, germanium (Ge), or gallium arsenide (GaAs). Even in this case, the effects of the present invention can be obtained in exactly the same manner.

1 is a cross-sectional view showing a first embodiment of a device cross-sectional structure of a field effect transistor which is a semiconductor device according to the present invention. It is a device manufacturing process figure which shows the 1st process in 1st embodiment of this invention. It is a device manufacturing process figure which shows the 2nd process in 1st embodiment of this invention. It is a device manufacturing process figure which shows the 3rd process in 1st embodiment of this invention. It is a device manufacturing process figure which shows the 4th process in 1st embodiment of this invention. It is a device manufacturing process figure which shows the 5th process in 1st embodiment of this invention. It is a device manufacturing process figure which shows the 6th process in 1st embodiment of this invention. It is a device manufacturing process figure which shows the 7th process in 1st embodiment of this invention. It is a device manufacturing process figure which shows the 8th process in 1st embodiment of this invention. It is a device manufacturing process figure which shows the 9th process in 1st embodiment of this invention. It is sectional drawing which shows 2nd Embodiment of the device cross-section of the field effect transistor which is a semiconductor device which concerns on this invention. It is a device manufacturing process figure which shows the 1st process in the 2nd Example of this invention. It is a device manufacturing process figure which shows the 2nd process in the 2nd Example of this invention. It is a device manufacturing process figure which shows the 3rd process in the 2nd Example of this invention. It is a device manufacturing process figure which shows the 4th process in the 2nd Example of this invention. It is a device manufacturing process figure which shows the 5th process in the 2nd Example of this invention. It is a device manufacturing process figure which shows the 6th process in the 2nd Example of this invention. It is a device manufacturing process figure which shows the 7th process in the 2nd Example of this invention. It is a device manufacturing process figure which shows the 8th process in the 2nd Example of this invention. It is a device manufacturing process figure which shows the 9th process in the 2nd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... N + type SiC substrate region, 2 ... N- type SiC drain region, 3 ... N + type hetero semiconductor region (polycrystalline silicon layer, first hetero semiconductor region), 4 ... Exposed region (N- type SiC drain) (Region 2 is exposed), 5... Gate insulating film (gate insulator layer), 6... Cap insulating film, 7... Groove, 8. Region), 9 ... P + type hetero semiconductor region (second hetero semiconductor region), 10 ... P + type hetero semiconductor region (region above cap insulating film 6), 11 ... N + type region (solid phase diffusion) N + type hetero semiconductor region), 12 ... P + type region (P + type hetero semiconductor region by solid phase diffusion), 13 ... drain electrode, 14 ... source electrode, 15 ... electric field relaxation region, 16 ... gate electrode , 100, 200 ... Conductor device.

Claims (22)

  A semiconductor substrate having a semiconductor region formed on a substrate, a hetero semiconductor region in contact with the semiconductor substrate and made of a semiconductor material having a band gap different from that of the semiconductor substrate, and a junction between the hetero semiconductor region and the semiconductor substrate A semiconductor device for manufacturing a semiconductor device having a gate electrode formed through a gate insulating film at a position close to the source, a source electrode connected to the hetero semiconductor region, and a drain electrode connected to the semiconductor substrate In the manufacturing method, a first hetero semiconductor layer forming step of forming a layer of a first hetero semiconductor region having the same conductivity type as the semiconductor base on the first main surface of the semiconductor base, and the first hetero semiconductor Forming a gate insulating film layer on the region layer and / or the semiconductor substrate; and A gate electrode forming step for forming the gate electrode through the gate insulating film at a predetermined position close to a bonding surface between the body region layer and the semiconductor substrate; and an upper portion of the gate electrode and the gate electrode A cap insulating film forming step of forming a cap insulating film on a part of the gate insulating film adjacent to the gate insulating film; and at least the gate insulating film and the first hetero semiconductor region using the cap insulating film as a mask The first hetero semiconductor region is patterned by etching and a first hetero semiconductor region forming step of exposing a part of the semiconductor substrate, and impurities are introduced onto the exposed semiconductor substrate. A hetero semiconductor region forming step for forming a hetero semiconductor region that is not formed, and the hetero semiconductor region in which no impurity is introduced A second hetero semiconductor region forming step of introducing a second hetero semiconductor region by introducing an impurity having a conductivity type different from that of the semiconductor substrate, and the second hetero semiconductor region forming step A method for manufacturing a semiconductor device, which is performed at least after the gate insulating film layer forming step.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second hetero semiconductor region forming step is performed at least after the first hetero semiconductor layer forming step.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the first hetero semiconductor region forming step etches and removes the gate insulating film and the first hetero semiconductor region layer using the cap insulating film as a mask. In this case, a part of a surface layer portion of the semiconductor substrate is further etched to form a groove on the semiconductor substrate.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating film layer forming step forms a part of the first hetero semiconductor region before forming the gate insulating film layer. 5. A step of etching to expose the semiconductor substrate, and forming a layer of the gate insulating film on the first hetero semiconductor region and the exposed semiconductor substrate, thereby forming a groove on the gate insulating film. Forming a semiconductor device.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the gate electrode forming step, a position where the gate electrode is formed on the gate insulating film is a position of the groove formed on the gate insulating film, A method of manufacturing a semiconductor device, wherein the gate electrode is formed so as to fill the trench.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode forming step further includes a step of flattening the surface of the formed gate electrode by etching or polishing. A method of manufacturing a semiconductor device.   7. The method of manufacturing a semiconductor device according to claim 1, wherein the cap insulating film formed in the cap insulating film forming step oxidizes the gate electrode so that an upper portion of the gate electrode and A method of manufacturing a semiconductor device, comprising an oxide film formed so as to cover an upper portion of a partial region of the gate insulating film adjacent to the gate electrode.   8. The method of manufacturing a semiconductor device according to claim 1, wherein the second hetero semiconductor region forming step is adjacent to the second hetero semiconductor region in the hetero semiconductor region into which no impurity is introduced. A method of manufacturing a semiconductor device, further comprising a heat treatment step for performing a heat treatment for solid-phase diffusion of the impurity introduced into the second hetero semiconductor region at the side wall portion.   9. The method of manufacturing a semiconductor device according to claim 8, wherein a side wall adjacent to the first hetero semiconductor region in the hetero semiconductor region into which impurities are not introduced by the heat treatment step of the second hetero semiconductor region formation step. A method of manufacturing a semiconductor device comprising: forming a side surface portion of the first hetero semiconductor region by solid-phase diffusion of impurities contained in the first hetero semiconductor region at a portion of the first hetero semiconductor region.   10. The method of manufacturing a semiconductor device according to claim 9, further comprising a source electrode forming step of forming the source electrode at least in contact with the side surface portion of the first hetero semiconductor region. Manufacturing method.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the source electrode formed in the source electrode forming step is in contact with a surface of the second hetero semiconductor region. Method.   12. The method of manufacturing a semiconductor device according to claim 1, wherein the drain is applied to the junction between the hetero semiconductor region and the semiconductor substrate in the vicinity of the surface layer portion of the first main surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: an electric field relaxation region forming step of forming an electric field relaxation region for relaxing an electrode drain electric field.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the electric field relaxation region forming step uses any one of a semiconductor having a conductivity type different from that of the semiconductor substrate, a high resistance body, or an insulator. Forming a semiconductor device.   14. The method of manufacturing a semiconductor device according to claim 1, wherein any one of silicon carbide, gallium nitride, and diamond is used as a material for the semiconductor substrate.   15. The method of manufacturing a semiconductor device according to claim 1, wherein the first hetero semiconductor region and / or the second hetero semiconductor region is made of single crystal silicon, polycrystalline silicon, or A method for manufacturing a semiconductor device, wherein any one of amorphous silicon is used.   A semiconductor substrate having a semiconductor region formed on a substrate, a hetero semiconductor region in contact with the semiconductor substrate and made of a semiconductor material having a band gap different from that of the semiconductor substrate, and a junction between the hetero semiconductor region and the semiconductor substrate A gate electrode formed via a gate insulating film at a position close to the semiconductor device, a source electrode connected to the hetero semiconductor region, and a drain electrode connected to the semiconductor substrate. A part of the hetero semiconductor region in contact with the semiconductor device has a region of the same conductivity type as the semiconductor substrate as the first hetero semiconductor region, and a region in contact with the source electrode at least on the side surface .   17. The semiconductor device according to claim 16, wherein the hetero semiconductor region has a conductivity type different from the conductivity type of the semiconductor substrate, in addition to the first hetero semiconductor region, and It has a second hetero semiconductor region formed in a groove formed in a predetermined region on one main surface, and the second hetero semiconductor region is in contact with the source electrode Semiconductor device.   18. The semiconductor device according to claim 17, wherein the first hetero semiconductor region and the second hetero semiconductor region have a region in contact with each other.   19. The semiconductor device according to claim 16, wherein the drain of the drain electrode is applied to a junction between the hetero semiconductor region and the semiconductor substrate in the vicinity of a surface layer portion of the first main surface of the semiconductor substrate. A semiconductor device, wherein an electric field relaxation region for relaxing an electric field is formed.   20. The semiconductor device according to claim 19, wherein the electric field relaxation region is made of any one of a semiconductor having a conductivity type different from that of the semiconductor substrate, a high resistance body, or an insulator.   21. The semiconductor device according to claim 16, wherein a material of the semiconductor substrate is any of silicon carbide, gallium nitride, or diamond.   The semiconductor device according to any one of claims 16 to 21, wherein a material of the first hetero semiconductor region and / or the second hetero semiconductor region is single crystal silicon, polycrystalline silicon, or amorphous silicon. A semiconductor device comprising any one of the above.

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