JP2007274260A - Signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing circuit the circuit scale of which can be reduced by simplifying the configuration independently of values of filter coefficients. <P>SOLUTION: The FIR filter 1A wherein values of the filter coefficients are symmetrical includes first adder sections (21, 22) for summating an output signal from a prescribed tap of a pre-stage side from the center to an output signal from a prescribed tap at a post-stage side from the center; multiplier sections (31 to 34) for multiplying filter coefficients corresponding to outputs of the first adder sections (21, 22) with the outputs of the first adder sections (21, 22); and band limit output sections (D101, 52) for outputting an output signal subjected to prescribed band limit by each unit time on the basis of the outputs of the multiplier sections (31 to 34). A 1/2 interleaving circuit 51 interleaves the output signal from the band limit output sections (D101, 52) every other interval to apply frequency conversion to the output signal subjected to the prescribed band limit to a half the sampling frequency and provides an output of the result. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal processing circuit, and more particularly to a technique for reducing the circuit scale of an FIR digital filter and a signal processing circuit using the FIR (Finite Impulse Response) filter.

  Conventionally, as a signal processing circuit, there is a sampling frequency conversion circuit shown in FIG. This sampling frequency conversion circuit (hereinafter referred to as “fs conversion circuit”) includes an 8-tap FIR filter 5 and a ½ decimation circuit 51. This FIR filter 5 includes a delay unit using seven consecutive flip-flops D1 to D7 and eight multipliers whose coefficients to be multiplied are a1, a2, a3, a4, a5, a6, a7, and a8, respectively. 31 to 38 and seven adders 21 to 27 for adding the output signals of the multipliers.

  The fs conversion circuit of FIG. 5 performs a 1/2 down-sampling of the signal F (T) band-limited by the FIR filter 5 with respect to the signal input from the outside by performing a thinning process by the 1/2 thinning circuit 51. Perform fs conversion.

  In FIG. 5, especially when the arrangement of the coefficients of the multiplier of the FIR filter 5 is symmetric, that is, when a1 = a8, a2 = a7, a3 = a6, and a4 = a5, the fs conversion circuit shown in FIG. It is possible to replace the circuit with a reduced number of multipliers.

  The FIR filter 6 in FIG. 6 first adds the tap output signals having the same coefficients, and then multiplies the coefficients by a multiplier. As a result, the number of multipliers in the entire circuit is reduced from eight to four. In FIG. 6, D1 to D7 are flip-flops, 21 to 27 are adders, 31 to 34 are multipliers, and 51 is a 1/2 decimation circuit.

  The operation of the fs conversion circuit in FIG. 6 will be described below.

  First, the filter output F (T) when data is input from the outside to the FIR filter 6 of FIG. 6 will be described.

Data _d 1 from the _{outside, d 2, ..., d 8} , d 9, d 10, ..., d n, sequentially inputs ... every unit time, in the order the output of each tap at a certain time _{T 1} is from the right, d1 , D2,..., D8, the filter output F (T ₁ ) at this time can be expressed by the following equation.
F (T ₁ ) = a1 (d ₈ + d ₁ ) + a2 (d ₇ + d ₂ )
+ A3 (d ₆ + d ₃ ) + a4 (d ₅ + d ₄ )
Further, at T ₂ after a unit time of T ₁ , the output of each tap is d2, d3,..., D9 in order from the right.
F (T ₂ ) = a1 (d ₉ + d ₂ ) + a2 (d ₈ + d ₃ )
+ A3 (d ₇ + d ₄ ) + a4 (d ₆ + d ₅ )
It becomes. That is, at time T _n , the output F (T _n ) of the FIR filter 6 is
F (T _n ) = a1 (d _{n + 7} + d _n )
+ A2 (dn _{+ 6} + dn _{+ 1} )
+ A3 (dn _{+ 5} + dn _{+ 2} )
+ A4 (dn _{+ 4} + dn _{+ 3} ) ... [Formula 1]
It can be expressed.

Therefore, after time T _n , F (T _n ), F (T _{n + 1} ), F (T _{n + 2} ), F (T _{n + 3} ), F (T _{n + 4} ), F (T _{n + 5} ), F (T _{Tn + 6} ),... Are sequentially output every unit time.

The fs conversion circuit of FIG. 6 outputs the data input to the ½ decimation circuit 51 for each of the data of the output F (T) from the FIR filter 6 to the outside of the decimation. Here, if the odd-numbered data is thinned out, even numbers such as F (T _n ), F (T _{n + 2} ), F (T _{n + 4} ), F (T _{n + 6} ),. Only the second data is sequentially output outside the fs conversion circuit every two unit times.

  As described above, the fs conversion circuit in FIG. 6 outputs data obtained by performing 1/2 downsampling fs conversion on input data from the outside.

  However, in the fs conversion circuit having the configuration shown in FIG. 6, the number of necessary multipliers and adders increases as the number of taps of the FIR filter increases, so that the scale of the entire circuit increases and the power consumption also increases. There is a problem.

  In order to solve this problem, techniques for simplifying the FIR filter by various methods and reducing the scale of the entire circuit have been implemented.

  As conventional techniques, FIG. 7 and FIG. 8 show a filter circuit and a Kaiser filter coefficient used for fs conversion for down-sampling by 1/2 decimation using a Kaizer window. In FIG. 7, D162 to D7 are flip-flops, 21 to 26 are adders, and 31 to 34 are multipliers.

  Similar circuits and coefficients are also disclosed in Japanese Patent Laid-Open No. 2001-358562 (Patent Document 1).

  As is apparent from FIG. 8, the 163 coefficients of the Kaiser filter have a characteristic that the value is “0” for each tap (except for the coefficient at the 82nd tap which is the center tap).

  The filter circuit shown in FIG. 7 is a 163 tap FIR filter having 162 delay devices. This FIR filter adds the tap outputs having the same coefficients as the FIR filter of the circuit shown in FIG. 6 and then multiplies the coefficients. The coefficient values shown in the coefficient table of FIG. Since the output signal of the tap with “0” does not need to be processed, the adder and multiplier of the tap are omitted. Specifically, the adders and multipliers of the second, fourth, sixth,..., 160, 162, even-numbered taps (except for the 82nd center) are omitted.

  As described above, the FIR filter shown in FIG. 7 reduces the circuit scale by omitting unnecessary adders and multipliers.

However, the FIR filter shown in FIG. 7 is applicable only when the coefficient has a feature that “a value is“ 0 ”for each tap”, that is, a feature that a part of the coefficients is “0”. Yes, the circuit scale can be reduced, but the filter coefficients that are not so cannot be applied.
JP 2001-358562 A (FIGS. 3 and 5)

  Accordingly, an object of the present invention is to provide a signal processing circuit that can simplify the configuration and reduce the circuit scale in a signal processing circuit using an FIR filter regardless of the filter coefficient of the FIR filter.

In order to solve the above problems, a signal processing circuit according to the present invention provides:
A first delay section having M (M is an integer of 3 or more) delay elements connected in series and having M + 1 taps for sequentially shifting an input signal inputted per unit time based on the sampling frequency by the delay elements. When M is an odd number, the value of the filter coefficient is symmetric with the (M + 1) / 2th delay element as the center, and when M is an even number, the M / 2 + 1th tap is the center. An FIR filter;
A thinning circuit that thins out every other output signal per unit time from the FIR filter,
The FIR filter is
A first adder for adding an output signal from a predetermined tap upstream of the center and an output signal from a predetermined tap downstream of the center; and the output corresponding to the output of the first adder A multiplier that multiplies the output of the first adder by a filter coefficient; and a band-limited output unit that outputs a predetermined band-limited output signal per unit time based on the output of the multiplier;
The decimation circuit is
By thinning out every other output signal per unit time from the band limited output unit of the FIR filter, the predetermined band limited output signal is frequency-converted to ½ the sampling frequency and output. It is characterized by doing.

  According to the signal processing circuit having the above configuration, the first delay unit of the FIR filter having the first delay unit in which M (M is an integer of 3 or more) delay elements are connected in series and the filter coefficient values are symmetric. The adder, multiplier, and band-limited output unit output a predetermined band-limited output signal for each unit time based on the sampling frequency. Then, every other unit of the output signal from the band-limited output unit of the FIR filter is thinned out by the decimation circuit, so that the predetermined band-limited output signal is reduced to ½ of the sampling frequency. Frequency-converted and output. As a result, the number of adders can be reduced by performing addition processing of the outputs of specific two consecutive taps, which has conventionally been added by two separate adders, with one adder. Therefore, in the signal processing circuit using the FIR filter, the configuration can be simplified and the circuit scale can be reduced regardless of the filter coefficient of the FIR filter.

In addition, the signal processing circuit of one embodiment
In the first delay unit of the FIR filter, 4m−1 (m is an integer of 1 or more) the delay elements are connected in series,
The FIR filter is
At time Tn per unit time (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k) th (k = 1 (when m = 1) or k = 1,2 of the first delay unit) (when m = 2) or k = 1,..., m−1, m (when m ≧ 3)), the output signal is selected and output, while when n is an odd number, the first A first signal selection unit that selects and outputs an output signal from the (2m + 2k-2) th tap of the delay unit;
The first adder of the FIR filter includes the first delay unit when the output signal from the (2m-2k + 1) -th tap of the first delay unit and n from the first signal selection unit are an even number. Or the output signal of the (2m + 2k) th tap of the first delay unit when n from the first signal selection unit is an odd number. outputs the (m−k + 1) th addition signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient, and (2m−2k + 1) th. The (m−k + 1) th addition signal from the first adder is multiplied by the (2m−2k + 2) th filter coefficient to multiply the (2m−2k + 2) th filter signal. Outputs the multiplication signal,
Furthermore, the FIR filter is
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the multiplication unit is selected and output, while when n is an odd number, the second multiplication signal is output. When m is 2 or more, at time Tn, when n is an even number, the (2m-2k + 1) -th multiplication signal from the multiplication unit is selected while n is an odd number. Includes a second signal selection unit that selects the (2m-2k + 2) th multiplication signal, adds the selected multiplication signals, and outputs the result.
The band-limited output unit of the FIR filter includes a second delay unit that delays an output signal from the second signal selection unit by the unit time, an output signal from the second signal selection unit, and the second delay unit. A second adder for adding the output signal from
The decimation circuit is
At time Tn, when n is an odd number, the output signal from the second adder is thinned out. When n is an even number, the output signal from the second adder is output.

  According to the signal processing circuit of the above embodiment, the first delay unit of the FIR filter is configured in the signal processing circuit having a configuration in which 4m−1 delay elements (m is an integer of 1 or more) are connected in series. Can be simplified and the circuit scale can be reduced.

In addition, the signal processing circuit of one embodiment
In the first delay unit of the FIR filter, 4m (m is an integer of 1 or more) the delay elements are connected in series,
The FIR filter is
At time Tn per unit time (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k + 1) -th (k = 1 (when m = 1)) or k = 1,2 of the first delay unit (when m = 2) or k = 1,..., m−1, m (when m ≧ 3)), the output signal is selected and output, while when n is an odd number, the first A first signal selection unit that selects and outputs an output signal from the (2m + 2k−1) -th tap of the delay unit;
The first adder of the FIR filter includes the first delay unit when the output signal from the (2m-2k + 1) -th tap of the first delay unit and n from the first signal selection unit are an even number. Or the output signal of the (2m + 2k + 1) th tap of the first delay unit when n from the first signal selection unit is an odd number, and the output signal of the (2m + 2k + 1) th tap of outputs the (m−k + 1) th addition signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient, and (2m−2k + 1) th. The (m−k + 1) th addition signal from the first adder is multiplied by the (2m−2k + 2) th filter coefficient to multiply the (2m−2k + 2) th filter signal. A first multiplier for outputting a multiplication signal, and an output signal from the (2m + 1) th tap of the first delay unit is multiplied by the (2m + 1) th filter coefficient to obtain a (2m + 1) th multiplication signal. A second multiplier for outputting,
Furthermore, the FIR filter is
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the first multiplication unit is selected and output, while when n is an odd number, the second multiplication is performed. When m is equal to or greater than 2, when m is equal to or greater than 2, when n is an even number, the (2m-2k + 1) th multiplication signal from the first multiplication unit is selected, while n A second signal selection unit that selects the (2m−2k + 2) th multiplication signal when the number is an odd number, and adds and outputs the selected multiplication signals;
At time Tn, when n is an even number, the (2m + 1) th multiplication signal from the second multiplication unit is selected, and when n is an odd number, a signal representing a constant 0 is selected and selected. A third signal selection unit that adds and outputs the output signal from the second signal selection unit,
The band-limited output unit of the FIR filter includes a second delay unit that delays an output signal from the third signal selection unit by the unit time, an output signal from the third signal selection unit, and the second delay unit. A second adder for adding the output signal from
The decimation circuit is
At time Tn, when n is an odd number, the output signal from the second adder is thinned out. When n is an even number, the output signal from the second adder is output.

  According to the signal processing circuit of the above embodiment, the configuration of the first delay unit of the FIR filter is simplified in the signal processing circuit in which 4m delay elements (m is an integer of 1 or more) are connected in series. Circuit scale can be reduced.

In addition, the signal processing circuit of one embodiment
The first delay unit of the FIR filter includes 4m + 1 (m is an integer of 1 or more) delay elements connected in series.
The FIR filter is
At time Tn per unit time (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k + 2) th (k = 1 (when m = 1) or k = 1,2 of the first delay unit) (when m = 2) or k = 1,..., m−1, m (when m ≧ 3)), the output signal is selected and output, while when n is an odd number, the first A first signal selection unit that selects and outputs an output signal from the (2m + 2k) th tap of the delay unit;
The first adder of the FIR filter includes the first delay unit when the output signal from the (2m-2k + 1) -th tap of the first delay unit and n from the first signal selection unit are an even number. The (2m + 2k + 2) -th tap output signal or the (2m + 2k) -th tap output signal of the first delay unit when n is an odd number from the first signal selection unit is added to the (m -K + 1) output the added signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient, and (2m−2k + 1) th. The (m−k + 1) th addition signal from the first adder is multiplied by the (2m−2k + 2) th filter coefficient to multiply the (2m−2k + 2) th filter signal. A first multiplier for outputting a multiplication signal, and an output signal from the (2m + 1) th tap of the first delay unit is multiplied by the (2m + 1) th filter coefficient to obtain a (2m + 1) th multiplication signal. A second multiplier for outputting,
Furthermore, the FIR filter is
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the first multiplication unit is selected and output, while when n is an odd number, the second multiplication is performed. When m is equal to or greater than 2, when m is equal to or greater than 2, when n is an even number, the (2m-2k + 1) th multiplication signal from the first multiplication unit is selected, while n A second signal selection unit that selects the (2m−2k + 2) th multiplication signal when the number is an odd number, and adds and outputs the selected multiplication signals;
A second adder that adds the output signal from the second signal selector and the (2m + 1) -th multiplied signal from the second multiplier and outputs the result.
The band-limited output unit of the FIR filter includes a second delay unit that delays the output signal from the second adder unit by the unit time, an output signal from the second adder unit, and a second delay unit. A third adder for adding the output signal;
The decimation circuit is
At time Tn, when n is an odd number, the output signal from the third adder is thinned out. When n is an even number, the output signal from the third adder is output.

  According to the signal processing circuit of the above embodiment, the configuration of the first delay unit of the FIR filter is simplified in the signal processing circuit in which 4m + 1 delay elements (m is an integer of 1 or more) are connected in series. Circuit scale can be reduced.

In addition, the signal processing circuit of one embodiment
In the first delay unit of the FIR filter, 4m + 2 (m is an integer of 1 or more) the delay elements are connected in series,
The FIR filter is
At time Tn per unit time (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k + 3) th (k = 1 (when m = 1) or k = 1,2 of the first delay unit) (when m = 2) or k = 1,..., m−1, m (when m ≧ 3)), the output signal is selected and output, while when n is an odd number, the first A first signal selection unit that selects and outputs an output signal from the (2m + 2k + 1) -th tap of the delay unit;
The first adder of the FIR filter includes the first delay unit when the output signal from the (2m-2k + 1) -th tap of the first delay unit and n from the first signal selection unit are an even number. The (2m + 2k + 1) -th tap output signal or the (2m + 2k + 1) -th tap output signal of the first delay unit when n from the first signal selection unit is an odd number is added, and the (m -K + 1) output the addition signal and add the output signal from the (2m + 1) th tap of the first delay unit and the output signal from the (2m + 3) th tap of the first delay unit , Output the (m + 1) th addition signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient, and (2m−2k + 1) th. The (m−k + 1) th addition signal from the first adder is multiplied by the (2m−2k + 2) th filter coefficient to multiply the (2m−2k + 2) th filter signal. A first multiplier that outputs a multiplication signal, and a (2m + 1) th multiplication signal by multiplying the (m + 1) th addition signal from the first addition unit by the (2m + 1) th filter coefficient. A second multiplier that outputs and outputs the (2m + 2) th multiplied signal by multiplying the output signal from the (2m + 1) th tap of the first delay unit by the (2m + 2) th filter coefficient Have
Furthermore, the FIR filter is
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the multiplication unit is selected and output, while when n is an odd number, the second multiplication signal is output. When m is 2 or more, at time Tn, when n is an even number, the (2m-2k + 1) -th multiplication signal from the multiplication unit is selected while n is an odd number. Selects a (2m-2k + 2) th multiplication signal, adds the selected multiplication signals, and outputs the second signal selection unit;
At time Tn, when n is an even number, the (2m + 1) th multiplication signal from the second multiplication unit is selected, while when n is an odd number, the (2m + 2) th multiplication signal from the second multiplication unit is selected. A third signal selection unit that selects the multiplication signal, adds the selected signal and the output signal from the second signal selection unit, and outputs the added signal;
The band-limited output unit of the FIR filter includes a second delay unit that delays an output signal from the third signal selection unit by the unit time, an output signal from the third signal selection unit, and the second delay unit. A second adder for adding the output signal from
The decimation circuit is
At time Tn, when n is an odd number, the output signal from the second adder is thinned out. When n is an even number, the output signal from the second adder is output.

  According to the signal processing circuit of the above embodiment, the configuration of the first delay unit of the FIR filter is simplified in the signal processing circuit in which 4m + 2 (m is an integer of 1 or more) delay elements are connected in series. Circuit scale can be reduced.

  As is apparent from the above, according to the signal processing circuit of the present invention, in the signal processing circuit using the FIR filter, the signal processing circuit capable of simplifying the configuration and reducing the circuit scale regardless of the filter coefficient of the FIR filter. Can be realized.

  The signal processing circuit of the present invention will be described in detail below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1A shows the configuration of a signal processing circuit according to the first embodiment of the present invention. The signal processing circuit shown in FIG. 1A includes an FIR filter having a first delay unit in which 4m−1 (m = 2) delay elements are connected in series. In the FIR filter according to the first embodiment, the filter coefficient values are symmetric about the fourth delay element.

  The signal processing circuit shown in FIG. 1A is composed of an 8-tap FIR filter 1 and a 1/2 decimation circuit 51. The sampling frequency of 1/2 down-sampling is applied to the data input from the outside to the input unit 54. This is an fs conversion circuit that outputs a signal subjected to conversion (fs conversion) from the output unit 55 to the outside.

  The configuration and operation of the signal processing circuit shown in FIG. 1A will be described in detail below.

  First, the configuration of the FIR filter 1A will be described. The FIR filter 1A includes flip-flops D1 to D7 as examples of seven consecutive delay elements, selectors 41 and 42 as examples of a first signal selection unit, and adders 21 as examples of a first addition unit. 22, multipliers 31 to 34 as an example of a multiplier, selectors 43 and 44, an adder 26, a flip-flop D101 as an example of a second delay unit, and an adder as an example of a second adder 52.

  The flip-flops D1 to D7 constitute a first delay unit. The selectors 43 and 44 and the adder 26 constitute a second signal selection unit. Further, the flip-flop D101 and the adder 52 constitute a band limited output unit.

  In the FIR filter 1A, the first tap on the input side of the first delay unit is connected to one input terminal of the adder 21, and the third tap is connected to one input terminal of the adder 22.

  The fourth tap is connected to the input terminal A of the selector 41, the sixth tap is connected to the input terminal B of the selector 41, and the output terminal OP of the selector 41 is connected to the other input terminal of the adder 22. ing. Further, the sixth tap is connected to the input terminal A of the selector 42, the eighth tap is connected to the input terminal B of the selector 42, and the output terminal OP of the selector 42 is connected to the other input terminal of the adder 21. ing.

  The output terminal of the adder 21 is connected to the input terminals of the multipliers 31 and 32, and the output terminal of the adder 22 is connected to the input terminals of the multipliers 33 and 34.

  The output terminal of the multiplier 31 is connected to the input terminal B of the selector 43, and the output terminal of the multiplier 32 is connected to the input terminal A of the selector 43. The output terminal of the multiplier 33 is connected to the input terminal B of the selector 44, and the output terminal of the multiplier 34 is connected to the input terminal A of the selector 44.

  The output terminal OP of the selector 43 is connected to one input terminal of the adder 26, and the output terminal OP of the selector 44 is connected to the other input terminal of the adder 26. Further, the output terminal of the adder 26 is connected to the input terminal of the flip-flop D101 and one input terminal of the adder 52. The output terminal of the flip-flop D101 is connected to the other input terminal of the adder 52. The output terminal of the adder 52 is connected to the input terminal of the ½ thinning circuit 51.

  The selectors 41 to 44 have two input terminals A and B and one output terminal OP, and two input terminals are set by setting a switching control signal (not shown) given from the outside. Is a selector having a function of an output changeover switch that selects one of the input signals A and B from the signals input from the A and outputs the selected signal to the output terminal OP.

  Further, the multipliers 31 to 34 output the results of multiplying the signals input to the multipliers by a1, a2, a3, and a4, respectively, as FIR filter coefficients.

  Here, the coefficients a1, a2, a3, and a4 are arbitrary real numbers, and some of the coefficients need not be “0” as in the conventional filter coefficient shown in FIG.

  Next, the operation of the FIR filter 1A will be described.

Data _d 1 from the outside to the input unit _{54, d 2, ..., d} 8, d 9, d 10, ..., d n, ... an the sequentially input per unit time, of the taps at a certain time _{T 1} output Are d1, d2,..., D8 in order from the right as shown in FIG.

Note that switching settings of the selectors 41 to 44 at time T _n is, n is the time of the odd set to output from the select input from the input terminal A the output terminal OP, when n is an even number from B Are selected and output from the output terminal OP.

Here, if the output of the adder 26 at time T _n is G (T _n ), at time T ₁ , since the selectors 41 to 44 select the input of A, the adder 26 at time T ₁ The output G (T ₁ ) can be expressed by the following equation.
G (T ₁ ) = a2 (d ₈ + d ₃ )
+ A4 (d ₆ + d ₅ )
Next, at time _{T 2,} the selector 41-44 from input B is selected, the output G _{(T 2)} of the adder 26 can be expressed by the following equation.
G (T ₂ ) = a1 (d ₉ + d ₂ )
+ A3 (d ₇ + d ₄ )
Next, at time T ₃ , the selectors 41 to 44 select the input of A, so the output G (T ₃ ) of the adder 26 can be expressed by the following equation.
G (T ₃ ) = a2 (d ₁₀ + d ₅ )
+ A4 (d ₈ + d ₇ )
The output F (T _n ) of the FIR filter 1A at time T _n is added by the adder 52 to the output G (T _n ) of the adder 26 and the output G (T _n−1 ) of the flip-flop D101. F (T _n ) is expressed by the following equation.
F ( _Tn ) = G ( _Tn-1 ) + G ( _Tn )
Accordingly, the output of the FIR filter 1A at time _{T 2} and time _{T 3} respectively expressed by the following equation.
F (T ₂ ) = G (T ₁ ) + G (T ₂ )
= A1 (d ₉ + d ₂ )
+ A2 (d ₈ + d ₃ )
+ A3 (d ₇ + d ₄ )
+ A4 (d ₆ + d ₅ )
F (T ₃ ) = G (T ₂ ) + G (T ₃ )
= A1 (d ₉ + d ₂ )
+ A2 (d ₁₀ + d ₅ )
+ A3 (d ₇ + d ₄ )
+ A4 (d ₈ + d ₇ )

That is, F (T _n ) is expressed by the following equation. However, since the settings of the selectors 41 to 44 differ depending on whether n is an even number or an odd number, there are two types depending on the value of n.
[When n is an even number]
F (T _n ) = a1 (d _{n + 7} + d _n )
+ A2 (dn _{+ 6} + dn _{+ 1} )
+ A3 (dn _{+ 5} + dn _{+ 2} )
+ A4 (dn _{+ 4} + dn _{+ 3} ) ... [Formula 2]
[When n is an odd number]
F ( _Tn ) = a1 (dn _{+ 6} + dn _-1 )
+ A2 (dn _{+ 7} + dn _{+ 2} )
+ A3 (dn _{+ 4} + dn _{+ 1} )
+ A4 (dn _{+ 5} + dn _{+ 4} ) ... [Formula 3]
Therefore, as the output F (T _n ) of the FIR filter 1A, the calculation result of [Expression 2] and the calculation result of [Expression 3] are alternately output at every unit time.

  Next, the operation of the ½ thinning circuit 51 in FIG. 1A will be described.

The output data F (T _n ) from the FIR filter 1A is continuously input to the ½ thinning circuit 51 one by one per unit time. For the input data F (T _n ), one of the two consecutive data is thinned out, and the remaining one data is output as it is. Here, when thinning data, F (T _n ) when n is an odd number is thinned. Therefore, the ½ decimation circuit 51 has F (T _n ), F (T _{n + 2} ), F (T _{n + 4} ), F (T _{n + 6} ), etc. (where n is an even number) shown in [Equation 2]. Data is sequentially output one by one every two unit times.

  Further, the output of the 1/2 thinning circuit 51 is output to the outside as the output of the signal processing circuit of FIG. 1A.

  Here, the calculation result of [Expression 2] is the same as [Expression 1], which is the output of the FIR filter used in the fs conversion circuit of FIG. 6 described in the related art.

  Therefore, the signal processing circuit shown in FIG. 1A according to the first embodiment of the present invention is data obtained by performing 1/2 downsampling fs conversion on input data from the outside in the same manner as the fs conversion circuit shown in FIG. It is obvious that this is an fs conversion circuit that outputs.

  In the signal processing circuit shown in FIG. 1A, the signal processing circuit including the FIR filter having the first delay unit in which 4m−1 (m = 2) delay elements are connected in series has been described. The present invention may be applied to a signal processing circuit including an FIR filter having a first delay section in which -1 delay elements (m is 1 or 3 or more) are connected in series.

As a configuration of the signal processing circuit in this case,
FIR filter
At time Tn per unit time based on the sampling frequency (n is an integer greater than or equal to 1), when n is an even number, (2m + 2k) th (k = 1 (when m = 1)) or k = 1 , 2 (when m = 2) or k = 1,..., M−1, m (when m ≧ 3)) are selected and output, while when n is an odd number, A first signal selection unit that selects and outputs an output signal from the (2m + 2k−2) th tap of the one delay unit;
The first adder of the FIR filter includes the output signal from the (2m-2k + 1) th tap of the first delay unit and the (2m + 2k) th of the first delay unit when n from the first signal selection unit is an even number. Or the output signal of the (2m + 2k−2) th tap of the first delay unit when n from the first signal selection unit is an odd number, and the (m−k + 1) th tap signal is added. Output the addition signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient and outputs the (2m−2k + 1) th multiplication signal. And the (m−k + 1) th addition signal from the first addition unit is multiplied by the (2m−2k + 2) th filter coefficient to output the (2m−2k + 2) th multiplication signal.
Furthermore, the FIR filter
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the multiplication unit is selected and output, while when n is an odd number, the second multiplication signal is selected. When m is 2 or more, at time Tn, when n is an even number, the (2m-2k + 1) -th multiplication signal from the multiplier is selected, while when n is an odd number, (2m -2k + 2) including a second signal selection unit that selects the multiplication signal, adds the selected multiplication signals, and outputs the result.
The band limited output unit of the FIR filter includes a second delay unit that delays the output signal from the second signal selection unit by a unit time, an output signal from the second signal selection unit, and an output signal from the second delay unit. A second adding unit for adding,
The thinning circuit may be any circuit that thins out the output signal from the second addition unit when n is an odd number at time Tn and outputs the output signal from the second addition unit when n is an even number.

  For example, FIG. 1B shows a configuration of a signal processing circuit including an FIR filter having a first delay unit in which 4m−1 (m = 3) delay elements are connected in series. The signal processing circuit shown in FIG. 1B has the same effect as the signal processing circuit shown in FIG. 1A except for the difference in filter characteristics due to the increase in the number of taps from 8 to 12.

  The FIR filter 1B of the signal processing circuit shown in FIG. 1B includes flip-flops D1 to D11 as examples of eleven consecutive delay elements, selectors 41 to 43 as examples of a first signal selection unit, and a first addition unit. Adders 21 to 23 as an example, multipliers 31 to 36 as an example of a multiplier, selectors 44 to 46, an adder 26, a flip-flop D101 as an example of a second delay unit, and a second And an adder 52 as an example of an adder.

  The flip-flops D1 to D11 constitute a first delay unit. The selectors 44 to 46 and the adders 25 and 26 constitute a second signal selection unit. Further, the flip-flop D101 and the adder 52 constitute a band limited output unit.

(Second Embodiment)
FIG. 2A shows a configuration of a signal processing circuit according to the second embodiment of the present invention. The signal processing circuit shown in FIG. 2A includes an FIR filter having a first delay unit in which 4m (m = 2) delay elements are connected in series. In the FIR filter of the second embodiment, the filter coefficient values are symmetric with the fifth tap as the center.

  The signal processing circuit shown in FIG. 2A includes a 9-tap FIR filter 2A and a ½ thinning circuit 51, and ½ downsampling sampling frequency is applied to data input to the input unit 54 from the outside. This is an fs conversion circuit that outputs a signal subjected to conversion (fs conversion) from the output unit 55 to the outside.

  The configuration and operation of the signal processing circuit shown in FIG. 2A will be described in detail below.

  First, the configuration of the FIR filter 2A will be described. The FIR filter 2A includes flip-flops D1 to 8 as an example of eight consecutive delay elements, selectors 41 and 42 as an example of a first signal selection unit, and an adder 21 as an example of a first addition unit. 22, multipliers 31 to 35, selectors 43 to 45, adders 25 and 26, a flip-flop D101 as an example of a second delay unit, an adder 52 as an example of a second adder, and a constant And a constant generation circuit 56 as means for generating 0.

  The flip-flops D1 to 8 constitute a first delay unit. The multipliers 31 to 34 constitute a first multiplier, and the multiplier 35 constitutes a second multiplier. The selectors 43 and 44 and the adder 25 constitute a second signal selection unit. The selector 45 and the adder 26 constitute a third signal selection unit. Further, the flip-flop D101 and the adder 52 constitute a band limited output unit.

  In the FIR filter 2A, the first tap on the input side of the first delay unit is connected to one input terminal of the adder 21, and the third tap is connected to one input terminal of the adder 22.

  The fifth tap is connected to the input terminal A of the selector 41, the seventh tap is connected to the input terminal B of the selector 41, and the output terminal OP of the selector 41 is connected to the other input terminal of the adder 22. ing. The seventh tap is connected to the input terminal A of the selector 42, the ninth tap is connected to the input terminal B of the selector 42, and the output terminal OP of the selector 42 is connected to the other input terminal of the adder 21. ing.

  The output terminal of the adder 21 is connected to the input terminals of the multipliers 31 and 32, and the output terminal of the adder 22 is connected to the input terminals of the multipliers 33 and 34. The fifth tap is connected to the input terminal of the multiplier 35.

  The output terminal of the multiplier 31 is connected to the input terminal B of the selector 43, and the output terminal of the multiplier 32 is connected to the input terminal A of the selector 43. The output terminal of the multiplier 33 is connected to the input terminal B of the selector 44, and the output terminal of the multiplier 34 is connected to the input terminal A of the selector 44. The output terminal OP of the selector 43 is connected to one input terminal of the adder 25, and the output terminal OP of the selector 44 is connected to the other input terminal of the adder 25.

  The output terminal of the multiplier 35 is connected to the input terminal B of the selector 45, and the output terminal of the constant generation circuit 56 is connected to the input terminal A of the selector 45. Further, the output terminal of the adder 25 is connected to one input terminal of the adder 26, and the output terminal OP of the selector 45 is connected to the other input terminal of the adder 26.

  The output terminal of the adder 26 is connected to the input terminal of the flip-flop D101 and one input terminal of the adder 52. The output terminal of the flip-flop D101 is connected to the other input terminal of the adder 52. The output terminal of the adder 52 is connected to the input terminal of the ½ thinning circuit 51.

  The selectors 41 to 45 have two input terminals A and B and one output terminal OP, and two input terminals are set by setting a switching control signal (not shown) given from the outside. Is a selector having a function of an output changeover switch that selects one of the input signals A and B from the signals input from the A and outputs the selected signal to the output terminal OP.

  The multipliers 31 to 35 output the results of multiplying the signals input to the multipliers by a1, a2, a3, a4, and a5, respectively, as FIR filter coefficients.

  Next, the operation of the FIR filter 2A will be described.

Data _d 1 from the outside to the input unit _{54, d 2, ..., d} 8, d 9, d 10, ..., d n, ... an the sequentially input per unit time, of the taps at a certain time _{T 1} output Are d1, d2,..., D9 in order from the right as shown in FIG. 2A.

Note that switching settings of the selectors 41 to 45 at time T _n is, n is the time of the odd set to output from the select input from the input terminal A the output terminal OP, when n is an even number from B Are selected and output from the output terminal OP.

Here, the output of the adder 26 at time _{T n} When G _{(T n),} at time _{T 1} and _{T 3,} the selector 41 to 45 input A is selected, at time _{T 2,} the selector 41 Since the input of B is selected for .about.45, the outputs G (T ₁ ), G (T ₂ ) and G (T ₃ ) of the adder 26 at times T ₁ , T ₂ and T ₃ are respectively expressed by the following equations. I can express.
G (T ₁ ) = a2 (d ₉ + d ₃ )
+ A4 (d ₇ + d ₅ )
+0
G (T ₂ ) = a1 (d ₁₀ + d ₂ )
+ A3 (d ₈ + d ₄ )
+ A5 (d ₆ )
G (T ₃ ) = a2 (d ₁₁ + d ₅ )
+ A4 (d ₉ + d ₇ )
+0
The output F (T _n ) of the FIR filter 2A at time T _n is added by the adder 52 to the output G (T _n ) of the adder 26 and the output G (T _n−1 ) of the flip-flop D101. F (T _n ) is expressed by the following equation.
F ( _Tn ) = G ( _Tn-1 ) + G ( _Tn )
Accordingly, the output of the FIR filter 2A at time _{T 2} and time _{T 3} respectively expressed by the following equation.
F (T ₂ ) = G (T ₁ ) + G (T ₂ )
= A1 (d ₁₀ + d ₂ )
+ A2 (d ₉ + d ₃ )
+ A3 (d ₈ + d ₄ )
+ A4 (d ₇ + d ₅ )
+ A5 (d ₆ )
F (T ₃ ) = G (T ₂ ) + G (T ₃ )
= A1 (d ₁₀ + d ₂ )
+ A2 (d ₁₁ + d ₅ )
+ A3 (d ₈ + d ₄ )
+ A4 (d ₉ + d ₇ )
+ A5 (d ₆ )

That is, F (T _n ) is expressed by the following equation. However, since the settings of the selectors 41 to 45 differ depending on whether n is an even number or an odd number, the selectors 41 to 45 are divided into two types depending on the value of n.
[When n is an even number]
_{F (T n) = a1 (} d n + 8 + d n)
+ A2 (dn _{+ 7} + dn _{+ 1} )
+ A3 (dn _{+ 6} + dn _{+ 2} )
+ A4 (dn _{+ 5} + dn _{+ 3} )
+ A5 (dn _{+ 4} ) ......... [Formula 4]
[When n is an odd number]
F ( _Tn ) = a1 (dn _{+ 7} + dn _-1 )
+ A2 (dn _{+ 8} + dn _{+ 2} )
+ A3 (dn _{+ 5} + dn _{+ 1} )
+ A4 (dn _{+ 6} + dn _{+ 4} )
+ A5 (dn _{+ 3} ) ......... [Formula 5]
Therefore, as the output F (T _n ) of the FIR filter 2A, the calculation result of [Expression 4] and the calculation result of [Expression 5] are alternately output at every unit time.

2A operates in the same manner as the 1/2 thinning circuit 51 in FIG. 1A. That is, the data of F (T _n ), F (T _{n + 2} ), F (T _{n + 4} ), F (T _{n + 6} ),... (Where n is an even number) shown in [Equation 4] is obtained every two unit times. Output sequentially one by one. Then, the data is output to the outside of the signal processing circuit of FIG.

As described above, the signal processing circuit illustrated in FIG. 2A is an fs conversion circuit that outputs data obtained by performing 1/2 downsampling fs conversion on input data from the outside. In the signal processing circuit shown, the signal processing circuit including the FIR filter having the first delay unit in which 4m (m = 2) delay elements are connected in series has been described, but 4m (m is 1 or 3 or more). The present invention may be applied to a signal processing circuit provided with an FIR filter having a first delay unit in which delay elements (1) are connected in series.

As a configuration of the signal processing circuit in this case,
FIR filter
At time Tn per unit time based on the sampling frequency (n is an integer of 1 or more), when n is an even number, (2m + 2k + 1) th (k = 1 (when m = 1)) or k = 1 of the first delay unit , 2 (when m = 2) or k = 1,..., M−1, m (when m ≧ 3)) are selected and output, while when n is an odd number, Including a first signal selection unit that selects and outputs an output signal from the (2m + 2k−1) -th tap of one delay unit;
The first adder of the FIR filter includes the output signal from the (2m-2k + 1) th tap of the first delay unit and the (2m + 2k + 1) th of the first delay unit when n from the first signal selection unit is an even number. Or the output signal of the (2m + 2k−1) th tap of the first delay unit when n from the first signal selection unit is an odd number, and the (m−k + 1) th tap signal is added. Output the addition signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient and outputs the (2m−2k + 1) th multiplication signal. In addition, the (m−k + 1) th addition signal from the first addition unit is multiplied by the (2m−2k + 2) th filter coefficient to output the (2m−2k + 2) th multiplication signal. And a second multiplier that multiplies the output signal from the (2m + 1) th tap of the first delay unit by the (2m + 1) th filter coefficient and outputs the (2m + 1) th multiplied signal,
Furthermore, the FIR filter
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the first multiplication unit is selected and output, while when n is an odd number, the second multiplication signal is output. When m is 2 or more, at time Tn, when n is an even number, the (2m-2k + 1) -th multiplication signal from the first multiplier is selected, while n is an odd number. Selects a (2m-2k + 2) th multiplication signal, adds the selected multiplication signals, and outputs the second signal selection unit;
At time Tn, when n is an even number, the (2m + 1) -th multiplication signal from the second multiplication unit is selected, while when n is an odd number, a signal representing a constant 0 is selected and the selected signal is A third signal selection unit that adds and outputs the output signal from the second signal selection unit,
The band limited output unit of the FIR filter includes a second delay unit that delays an output signal from the third signal selection unit by a unit time, an output signal from the third signal selection unit, and an output signal from the second delay unit. A second adding unit for adding,
The thinning circuit may be any circuit that thins out the output signal from the second addition unit when n is an odd number at time Tn and outputs the output signal from the second addition unit when n is an even number.

  For example, FIG. 2B shows a configuration of a signal processing circuit including an FIR filter having a first delay unit in which 4m (m = 3) delay elements are connected in series. The signal processing circuit shown in FIG. 2B has the same effect as the signal processing circuit shown in FIG. 2A except for the difference in filter characteristics due to the increase in the number of taps from 9 to 13.

  The FIR filter 2B of the signal processing circuit shown in FIG. 2B includes flip-flops D1 to 12 as examples of twelve consecutive delay elements, first signal selectors 41 to 43, and first adders 21 to 21. 23, multipliers 31 to 37, selectors 44 to 47, adders 25 and 26, a flip-flop D101 as an example of a second delay unit, an adder 52 as an example of a second adder, and a constant And a constant generation circuit 56 as means for generating 0.

  The flip-flops D1 to D12 constitute a first delay unit. The multipliers 31 to 36 constitute a first multiplier, and the multiplier 37 constitutes a second multiplier. The selectors 4 to 46 and the adders 25 and 26 constitute a second signal selection unit. The selector 47 and the adder 27 constitute a third signal selection unit. Further, the flip-flop D101 and the adder 52 constitute a band limited output unit.

(Third embodiment)
FIG. 3A shows the configuration of a signal processing circuit according to the third embodiment of the present invention. The signal processing circuit shown in FIG. 3A includes an FIR filter having a first delay unit in which 4m + 1 (m = 2) delay elements are connected in series. In the FIR filter according to the third embodiment, the filter coefficient values are symmetric about the fifth delay element.

  The signal processing circuit shown in FIG. 3A includes a 10-tap FIR filter 3A and a ½ thinning circuit 51, and ½ down-sampling sampling frequency for data inputted from the outside to the input unit 54. This is an fs conversion circuit that outputs a signal subjected to conversion (fs conversion) from the output unit 55 to the outside.

  The configuration and operation of the signal processing circuit shown in FIG. 3A will be described in detail below.

  First, the configuration of the FIR filter 3A will be described. The FIR filter 3A includes flip-flops D1 to 9 as an example of nine consecutive delay elements, selectors 41 and 42 as an example of a first signal selection unit, and an adder 21 as an example of a first addition unit. 22, multipliers 31 to 35, selectors 43 and 44, adders 25 and 26, a flip-flop D <b> 101 as an example of a second delay unit, and an adder 52 as an example of a third adder. ing.

  The flip-flops D1 to D9 constitute a first delay unit. The multipliers 31 to 34 constitute a first multiplier, and the multiplier 35 constitutes a second multiplier. The selectors 43 and 44 and the adder 25 constitute a second signal selection unit. The adder 26 constitutes a second adder. Further, the flip-flop D101 and the adder 52 constitute a band limited output unit.

  In the FIR filter 3A, the first tap on the input side of the first delay unit is connected to one input terminal of the adder 21, and the third tap is connected to one input terminal of the adder 22.

  Further, the sixth tap is connected to the input terminal A of the selector 41, the eighth tap is connected to the input terminal B of the selector 41, and the output terminal OP of the selector 41 is connected to the other input terminal of the adder 22. ing. Further, the eighth tap is connected to the input terminal A of the selector 42, the tenth tap is connected to the input terminal B of the selector 42, and the output terminal OP of the selector 42 is connected to the other input terminal of the adder 21. ing.

  The output terminal of the adder 21 is connected to the input terminals of the multipliers 31 and 32, and the output terminal of the adder 22 is connected to the input terminals of the multipliers 33 and 34. The fifth tap is connected to the input terminal of the multiplier 35.

  The output terminal of the multiplier 31 is connected to the input terminal B of the selector 43, and the output terminal of the multiplier 32 is connected to the input terminal A of the selector 43. The output terminal of the multiplier 33 is connected to the input terminal B of the selector 44, and the output terminal of the multiplier 34 is connected to the input terminal A of the selector 44.

  The output terminal OP of the selector 43 is connected to one input terminal of the adder 25, and the output terminal OP of the selector 44 is connected to the other input terminal of the adder 25. Further, the output terminal of the adder 25 is connected to one input terminal of the adder 26, and the output terminal of the multiplier 35 is connected to the other input terminal of the adder 26.

  The output terminal of the adder 26 is connected to the input terminal of the flip-flop D101 and one input terminal of the adder 52. The output terminal of the flip-flop D101 is connected to the other input terminal of the adder 52. The output terminal of the adder 52 is connected to the input terminal of the ½ thinning circuit 51.

  The selectors 41 to 44 have two input terminals A and B and one output terminal OP, and two input terminals are set by setting a switching control signal (not shown) given from the outside. Is a selector having a function of an output changeover switch that selects one of the input signals A and B from the signals input from the A and outputs the selected signal to the output terminal OP.

  The multipliers 31 to 35 output the results of multiplying the signals input to the multipliers by a1, a2, a3, a4, and a5, respectively, as FIR filter coefficients.

  Next, the operation of the FIR filter 3A will be described.

When the data d ₁ , d ₂ ,..., D ₈ , d ₉ , d ₁₀ ,..., D _n , etc. are sequentially input from the outside into the unit time, the output of each tap at a certain time T ₁ . Are d1, d2,..., D10 in order from the right, as shown in FIG. 3A.

Note that switching settings of the selectors 41 to 44 at time T _n may, when n is an odd number, set by selecting the input from the input terminal A to output from the output terminal OP, when n is an even number , B is selected and set to output from the output terminal OP.

Here, the output of the adder 26 at time _{T n} When G _{(T n),} at time _{T 1} and _{T 3,} the selector 41-44 input A is selected, at time _{T 2,} the selector 41 to 44 is because the input of B is selected, the time _{T 1,} T 2, _{T 3} of the adder 26 output _{G (T 1), G (} T 2), G (T 3) respectively by the following formula I can express.
G (T ₁ ) = a2 (d ₁₀ + d ₃ )
+ A4 (d ₈ + d ₅ )
+ A5 (d ₆ )
G (T ₂ ) = a1 (d ₁₁ + d ₂ )
+ A3 (d ₉ + d ₄ )
+ A5 (d ₇ )
G (T ₃ ) = a2 (d ₁₂ + d ₅ )
+ A4 (d ₁₀ + d ₇ )
+ A5 (d ₈ )
The output F (T _n ) of the FIR filter 3A at time T _n is added by the adder 52 with the output G (T _n ) of the adder 26 and the output G (T _n-1 ) of the flip-flop D101. F (T _n ) is expressed by the following equation.
F ( _Tn ) = G ( _Tn-1 ) + G ( _Tn )
Accordingly, the output of the FIR filter 3A at the time _{T 2} and time _{T 3} respectively expressed by the following equation.
F (T ₂ ) = G (T ₁ ) + G (T ₂ )
_{= A1 (d 11 + d 2} )
+ A2 (d ₁₀ + d ₃ )
+ A3 (d ₉ + d ₄ )
+ A4 (d ₈ + d ₅ )
+ A5 (d ₇ + d ₆ )
F (T ₃ ) = G (T ₂ ) + G (T ₃ )
_{= A1 (d 11 + d 2} )
_{+ A2 (d 12 + d 5} )
+ A3 (d ₉ + d ₄ )
+ A4 (d ₁₀ + d ₇ )
+ A5 (d ₈ + d ₇ )

That is, F (T _n ) is expressed by the following equation. However, since the settings of the selectors 41 to 44 differ depending on whether n is an even number or an odd number, there are two types depending on the value of n.
[When n is an even number]
_{F (Tn) = a1 (d} n + 9 + d n)
+ A2 (dn _{+ 8} + dn _{+ 1} )
+ A3 (dn _{+ 7} + dn _{+ 2} )
+ A4 (dn _{+ 6} + dn _{+ 3} )
+ A5 (dn _{+ 5} + dn _{+ 4} ) ... [Formula 6]
[When n is an odd number]
F ( _Tn ) = a1 (dn _{+ 8} + dn _-1 )
+ A2 (dn _{+ 9} + dn _{+ 2} )
+ A3 (dn _{+ 6} + dn _{+ 1} )
+ A4 (dn _{+ 3} + dn _{+ 4} )
+ A5 (dn _{+ 2} + dn _{+ 1} ) [Equation 7]
Therefore, as the output F (T _n ) of the FIR filter 3A, the calculation result of [Expression 6] and the calculation result of [Expression 7] are alternately output at every unit time.

3A operates in the same manner as the half-thinning circuit 51 of FIG. 1A. That is, the data of F (T _n ), F (T _{n + 2} ), F (T _{n + 4} ), F (T _{n + 6} ),... (Where n is an even number) shown in [Equation 6] is obtained every two unit times. Output sequentially one by one. Then, the data is output to the outside of the signal processing circuit of FIG.

  As described above, the signal processing circuit illustrated in FIG. 3A is an fs conversion circuit that outputs data obtained by performing 1/2 downsampling fs conversion on externally input data.

  In the signal processing circuit shown in FIG. 2A, the signal processing circuit including the FIR filter having the first delay unit in which 4m + 1 (m = 2) delay elements are connected in series has been described. The present invention may be applied to a signal processing circuit including an FIR filter having a first delay unit in which delay elements with m being 1 or 3 or more are connected in series.

As a configuration of the signal processing circuit in this case,
FIR filter
At time Tn per unit time based on the sampling frequency (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k + 2) th (k = 1 (when m = 1)) or k = 1 of the first delay unit , 2 (when m = 2) or k = 1,..., M−1, m (when m ≧ 3)) are selected and output, while when n is an odd number, A first signal selection unit that selects and outputs an output signal from the (2m + 2k) -th tap of one delay unit;
The first adder of the FIR filter includes the output signal from the (2m−2k + 1) th tap of the first delay unit and the (2m + 2k + 2) th of the first delay unit when n from the first signal selection unit is an even number. Or the (2m + 2k) th tap output signal of the first delay unit when n from the first signal selection unit is an odd number, and the (m−k + 1) th addition signal is added. Output
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient and outputs the (2m−2k + 1) th multiplication signal. In addition, the (m−k + 1) th addition signal from the first addition unit is multiplied by the (2m−2k + 2) th filter coefficient to output the (2m−2k + 2) th multiplication signal. And a second multiplication unit that multiplies the output signal from the (2m + 1) th tap of the first delay unit by the (2m + 1) th filter coefficient and outputs the (2m + 1) th multiplication signal. ,
Furthermore, the FIR filter
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the first multiplication unit is selected and output, while when n is an odd number, the second multiplication signal is output. When m is 2 or more, at time Tn, when n is an even number, the (2m-2k + 1) -th multiplication signal from the first multiplier is selected, while n is an odd number. Selects a (2m-2k + 2) th multiplication signal, adds the selected multiplication signals, and outputs the second signal selection unit;
A second adder that adds and outputs the output signal from the second signal selector and the (2m + 1) -th multiplied signal from the second multiplier,
The band limited output unit of the FIR filter adds the second delay unit that delays the output signal from the second adder unit by a unit time, the output signal from the second adder unit, and the output signal from the second delay unit. A third adding unit,
The thinning circuit may be any circuit as long as it thins out the output signal from the third adder when n is an odd number at time Tn and outputs the output signal from the third adder when n is an even number.

  For example, FIG. 3B shows a configuration of a signal processing circuit including an FIR filter having a first delay unit in which 4m + 1 (m = 3) delay elements are connected in series. The signal processing circuit shown in FIG. 3B has the same effect as the signal processing circuit shown in FIG. 3A except for the difference in filter characteristics due to the increase in the number of taps from 10 to 14.

  The FIR filter 3B of the signal processing circuit shown in FIG. 3B includes flip-flops D1 to 13 as an example of 13 consecutive delay elements, selectors 41 to 43 as an example of a first signal selection unit, and a first addition unit. Examples of adders 21 to 23, multipliers 31 to 35, selectors 44 to 46, adders 24 to 26, a flip-flop D101 as an example of a second delay unit, and an example of a third adder As an adder 52.

  The flip-flops D1 to 13 constitute a first delay unit. The multipliers 31 to 36 constitute a first multiplier, and the multiplier 37 constitutes a second multiplier. The selectors 44 to 46 and the adders 24 and 25 constitute a second signal selection unit. The adder 26 constitutes a second adder. Further, the flip-flop D101 and the adder 52 constitute a band limited output unit.

(Fourth embodiment)
FIG. 4A shows the configuration of a signal processing circuit according to the fourth embodiment of the present invention. The signal processing circuit shown in FIG. 4A includes an FIR filter having a first delay unit in which 4m + 2 (m = 2) delay elements are connected in series. In the FIR filter of the fourth embodiment, the filter coefficient values are symmetric about the sixth tap.

  The signal processing circuit shown in FIG. 4A includes an 11-tap FIR filter 4A and a ½ thinning circuit 51, and ½ downsampling sampling frequency for data input from the outside to the input unit 54. This is an fs conversion circuit that outputs a signal subjected to conversion (fs conversion) from the output unit 55 to the outside.

  The configuration and operation of the signal processing circuit shown in FIG. 4A will be described in detail below.

  First, the configuration of the FIR filter 4A will be described. The FIR filter 4A includes flip-flops D1 to 10 as an example of ten consecutive delay elements, selectors 41 and 42 as an example of a first signal selection unit, and adders 21 to as an example of a first addition unit. 23, multipliers 31 to 36, selectors 43 to 45, adders 25 and 26, a flip-flop D101 as an example of a second delay unit, and an adder 52 as an example of a second adder. ing.

  The flip-flops D1 to D10 constitute a first delay unit. The multipliers 31 to 34 constitute a first multiplier, and the multipliers 35 and 36 constitute a second multiplier. The selectors 43 and 44 and the adder 25 constitute a second signal selection unit. The selector 45 and the adder 26 constitute a third signal selection unit. Further, the flip-flop D101 and the adder 52 constitute a band limited output unit.

  In the FIR filter 4A, the first tap on the input side of the first delay unit is connected to one input terminal of the adder 21, and the third tap is connected to one input terminal of the adder 22. The fifth tap is connected to one input terminal of the adder 23, and the seventh tap is connected to the other input terminal of the adder 23.

  Further, the seventh tap is connected to the input terminal A of the selector 41, the ninth tap is connected to the input terminal B of the selector 41, and the output terminal OP of the selector 41 is connected to the other input terminal of the adder 22. ing. The ninth tap is connected to the input terminal A of the selector 42, the eleventh tap is connected to the input terminal B of the selector 42, and the output terminal OP of the selector 42 is connected to the other input terminal of the adder 21. ing.

  The output terminal of the adder 21 is connected to the input terminals of the multipliers 31 and 32, and the output terminal of the adder 22 is connected to the input terminals of the multipliers 33 and 34. The output terminal of the adder 23 is connected to the input terminal of the multiplier 35, and the fifth tap is connected to the input terminal of the multiplier 36.

  The output terminal of the multiplier 31 is connected to the input terminal B of the selector 43, and the output terminal of the multiplier 32 is connected to the input terminal A of the selector 43. The output terminal of the multiplier 33 is connected to the input terminal B of the selector 44, and the output terminal of the multiplier 34 is connected to the input terminal A of the selector 44. The output terminal of the multiplier 35 is connected to the input terminal B of the selector 45, and the output terminal of the multiplier 36 is connected to the input terminal A of the selector 45.

  The output terminal OP of the selector 43 is connected to one input terminal of the adder 25, and the output terminal OP of the selector 44 is connected to the other input terminal of the adder 25. Further, the output terminal of the adder 25 is connected to one input terminal of the adder 26, and the output terminal OP of the selector 45 is connected to the other input terminal of the adder 26.

  The output terminal of the adder 26 is connected to the input terminal of the flip-flop D101 and one input terminal of the adder 52. The output terminal of the flip-flop D101 is connected to the other input terminal of the adder 52. The output terminal of the adder 52 is connected to the input terminal of the ½ thinning circuit 51.

  The selectors 41 to 45 have two input terminals A and B and one output terminal OP, and two input terminals are set by setting a switching control signal (not shown) given from the outside. Is a selector having a function of an output changeover switch that selects one of the input signals A and B from the signals input from the A and outputs the selected signal to the output terminal OP.

  Further, the multipliers 31 to 36 output the result of multiplying the signals input to the multiplier by a1, a2, a3, a4, a5, and a6, respectively, as the coefficients of the FIR filter.

  Next, the operation of the FIR filter 4A will be described.

Data _d 1 from the outside to the input unit _{54, d 2, ..., d} 8, d 9, d 10, ..., d n, ... an the sequentially input per unit time, of the taps at a certain time _{T 1} output As shown in FIG. 2A, d1, d2,..., D11 are sequentially from the right.

  The switching setting of each selector 41 to 45 at time Tn is set so that when n is an odd number, the input from the input terminal A is selected and output from the output terminal OP, and when n is an even number, The input from B is selected and set to output from the output terminal OP.

Here, the output of the adder 26 at time _{T n} When G _{(T n),} at time _{T 1} and _{T 3,} the selector 41 to 45 input A is selected, at time _{T 2,} the selector 41 Since the input of B is selected for .about.45, the outputs G (T ₁ ), G (T ₂ ) and G (T ₃ ) of the adder 26 at times T ₁ , T ₂ and T ₃ are respectively expressed by the following equations. I can express.
G (T ₁ ) = a2 (d ₁₁ + d ₃ )
+ A4 (d ₉ + d ₅ )
+ A6 (d ₇ )
G (T ₂ ) = a1 (d ₁₂ + d ₂ )
+ A3 (d ₁₀ + d ₄ )
+ A5 (d ₈ + d ₆ )
G (T ₃ ) = a2 (d ₁₃ + d ₅ )
+ A4 (d ₁₁ + d ₇ )
+ A5 (d ₉ )
The output F (T _n ) of the FIR filter 4A at time T _n is added by the adder 52 with the output G (T _n ) of the adder 26 and the output G (T _n−1 ) of the flip-flop D101. F (T _n ) is expressed by the following equation.
F ( _Tn ) = G ( _Tn-1 ) + G ( _Tn )
Accordingly, the output of the FIR filter 4A at time _{T 2} and time _{T 3} respectively expressed by the following equation.
F (T ₂ ) = G (T ₁ ) + G (T ₂ )
_{= A1 (d 12 + d 2} )
_{+ A2 (d 11 + d 3} )
+ A3 (d ₁₀ + d ₄ )
+ A4 (d ₉ + d ₅ )
+ A5 (d ₈ + d ₆ )
+ A6 (d ₇ )
F (T ₃ ) = G (T ₂ ) + G (T ₃ )
_{= A1 (d 12 + d 2} )
_{+ A2 (d 13 + d 5} )
+ A3 (d ₁₀ + d ₄ )
+ A4 (d ₁₁ + d ₇ )
+ A5 (d ₈ + d ₆ )
+ A6 (d ₉ )

That is, F (T _n ) is expressed by the following equation. However, since the settings of the selectors 41 to 45 differ depending on whether n is an even number or an odd number, the selectors 41 to 45 are divided into two types depending on the value of n.
[When n is an even number]
F (T _n ) = a1 (d _{n + 9} + d _n )
+ A2 (dn _{+ 8} + dn _{+ 1} )
+ A3 (dn _{+ 7} + dn _{+ 2} )
+ A4 (dn _{+ 6} + dn _{+ 3} )
+ A5 (dn _{+ 5} + dn _{+ 4} ) ... [Formula 8]
[When n is an odd number]
F ( _Tn ) = a1 (dn _{+ 8} + dn _-1 )
+ A2 (dn _{+ 9} + dn _{+ 2} )
+ A3 (dn _{+ 6} + dn _{+ 1} )
+ A4 (dn _{+ 3} + dn _{+ 4} )
+ A5 (dn _{+ 2} + dn _{+ 1} ) ... [Equation 9]
Therefore, as the output F (T _n ) of the FIR filter 4A, the calculation result of [Expression 8] and the calculation result of [Expression 9] are alternately output for each unit time.

4A operates in the same manner as the ½ thinning circuit 51 in FIG. 1A. That is, the data of F (T _n ), F (T _{n + 2} ), F (T _{n + 4} ), F (T _{n + 6} ),... (Where n is an even number) shown in [Equation 8] is 1 every 2 unit times. Output sequentially. Then, the data is output to the outside of the signal processing circuit of FIG.

  As described above, the signal processing circuit shown in FIG. 4A is an fs conversion circuit that outputs data obtained by performing 1/2 downsampling fs conversion on externally input data.

  In the signal processing circuit shown in FIG. 2A, the signal processing circuit including the FIR filter having the first delay unit in which 4m + 1 (m = 2) delay elements are connected in series has been described. The present invention may be applied to a signal processing circuit including an FIR filter having a first delay unit in which delay elements with m being 1 or 3 or more are connected in series.

As a configuration of the signal processing circuit in this case,
FIR filter
At time Tn per unit time based on the sampling frequency (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k + 3) th (k = 1 (when m = 1)) or k = 1 of the first delay unit , 2 (when m = 2) or k = 1,..., M−1, m (when m ≧ 3)) are selected and output, while when n is an odd number, A first signal selection unit that selects and outputs an output signal from the (2m + 2k + 1) -th tap of one delay unit;
The first adder of the FIR filter includes the output signal from the (2m−2k + 1) th tap of the first delay unit and the (2m + 2k + 3) th of the first delay unit when n from the first signal selection unit is an even number. Or the (2m + 2k + 1) th tap output signal of the first delay unit when n from the first signal selection unit is an odd number, and the (m−k + 1) th added signal is added. And the output signal from the (2m + 1) -th tap of the first delay unit and the output signal from the (2m + 3) -th tap of the first delay unit are added to obtain the (m + 1) -th added signal Output
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient and outputs the (2m−2k + 1) th multiplication signal. In addition, the (m−k + 1) th addition signal from the first addition unit is multiplied by the (2m−2k + 2) th filter coefficient to output the (2m−2k + 2) th multiplication signal. And the (2m + 1) th filter signal by multiplying the (m + 1) th addition signal from the first addition unit by the (2m + 1) th filter coefficient and outputting the (2m + 1) th multiplication signal. A second multiplication unit that multiplies the output signal from the second tap by the (2m + 2) th filter coefficient and outputs the (2m + 2) th multiplication signal;
Furthermore, the FIR filter
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the multiplication unit is selected and output, while when n is an odd number, the second multiplication signal is selected. When m is 2 or more, at time Tn, when n is an even number, the (2m-2k + 1) -th multiplication signal from the multiplier is selected, while when n is an odd number, (2m A -2k + 2) th multiplication signal, a second signal selection unit for adding and outputting the selected multiplication signals;
At time Tn, when n is an even number, the (2m + 1) th multiplication signal from the second multiplication unit is selected, and when n is an odd number, the (2m + 2) th multiplication signal from the second multiplication unit is selected. A third signal selection unit that selects and outputs the selected signal and the output signal from the second signal selection unit,
The band limited output unit of the FIR filter includes a second delay unit that delays an output signal from the third signal selection unit by a unit time, an output signal from the third signal selection unit, and an output signal from the second delay unit. A second adding unit for adding,
The thinning circuit may be any circuit that thins out the output signal from the second addition unit when n is an odd number at time Tn and outputs the output signal from the second addition unit when n is an even number.

  For example, FIG. 4B shows a configuration of a signal processing circuit including an FIR filter having a first delay unit in which 4m + 2 (m = 3) delay elements are connected in series. The signal processing circuit shown in FIG. 4B has the same effect as the signal processing circuit shown in FIG. 4A except for the difference in filter characteristics due to the increase in the number of taps from 11 to 15.

  The FIR filter 4B of the signal processing circuit shown in FIG. 4B includes flip-flops D1 to 14 as an example of 14 consecutive delay elements, selectors 41 to 43 as an example of a first signal selection unit, and a first addition unit. Examples of adders 21 to 24, multipliers 31 to 38, selectors 44 to 47, adders 25 to 27, a flip-flop D101 as an example of a second delay unit, and an example of a second adder As an adder 52.

  The flip-flops D1 to D14 constitute a first delay unit. The multipliers 31 to 36 constitute a first multiplier, and the multipliers 37 and 38 constitute a second multiplier. The selectors 44 to 46 and the adders 25 and 26 constitute a second signal selection unit. The selector 47 and the adder 27 constitute a third signal selection unit. Further, the flip-flop D101 and the adder 52 constitute a band limited output unit.

  FIR filters 1A, 1B, 2A, 2B, 3A of the signal processing circuit shown in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B of the first to fourth embodiments. In 3B, 4A, and 4B, the addition processing of the output of two specific continuous taps that has been added by two separate adders in the conventional signal processing circuit shown in FIG. Addition processing is made common by the unit. For example, the addition process of the first and second taps in FIG. 1A is shared by one adder 21 to reduce the number of adders. In the whole circuit, FIG. 6 uses seven adders, but in FIG. 1A, the number is reduced to four.

  That is, the signal processing circuit in the prior art shown in FIG. 6 and the signal processing circuit in the present invention shown in FIG. 1A perform the same operation, but the signal processing circuit in FIG. The circuit scale is reduced as compared with the signal processing circuit.

  In addition, the conventional technique for reducing the circuit scale shown in FIG. 7 has the disadvantage that it cannot be applied unless the filter has a part of the FIR filter coefficient of “0” in the signal processing circuit. Rather, it can be adapted to general filters.

  Therefore, according to the signal processing circuit of the first to fourth embodiments of the present invention, in the signal processing circuit using the FIR filter, the configuration is simplified and the circuit scale is reduced regardless of the filter coefficient of the FIR filter. Can do.

FIG. 1A is a block diagram showing a configuration of a signal processing circuit according to the first embodiment of the present invention. FIG. 1B is a block diagram showing a configuration of a signal processing circuit when there are 4m−1 delay elements (m = 3). FIG. 2A is a block diagram showing a configuration of a signal processing circuit according to the second embodiment of the present invention. FIG. 2B is a block diagram showing the configuration of the signal processing circuit when there are 4m delay elements (m = 3). FIG. 3A is a block diagram showing a configuration of a signal processing circuit according to the third embodiment of the present invention. FIG. 3B is a block diagram showing the configuration of the signal processing circuit when there are 4m + 1 delay elements (m = 3). FIG. 4A is a block diagram showing a configuration of a signal processing circuit according to the fourth embodiment of the present invention. FIG. 4B is a block diagram showing the configuration of the signal processing circuit when there are 4m + 2 delay elements (m = 3). FIG. 5 shows a signal processing circuit using a general FIR filter. FIG. 6 shows an example of a signal processing circuit with a reduced circuit scale in the prior art. FIG. 7 shows another example of a signal processing circuit with a reduced circuit scale in the prior art. FIG. 8 is a table showing the Kaiser filter coefficients used in the signal processing circuit shown in FIG.

Explanation of symbols

1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B ... FIR filters D1-D14, D101 ... flip-flops 21-27, 52 ... adders 31-38 ... multipliers 41-47 ... selectors 51 ... 1/2 Thinning-out circuit 54 ... Input unit 55 ... Output unit 56 ... Constant generation circuit

Claims (5)

A first delay section having M (M is an integer of 3 or more) delay elements connected in series and having M + 1 taps for sequentially shifting an input signal inputted per unit time based on the sampling frequency by the delay elements. When M is an odd number, the value of the filter coefficient is symmetric with the (M + 1) / 2th delay element as the center, and when M is an even number, the M / 2 + 1th tap is the center. An FIR filter;
A thinning circuit that thins out every other output signal per unit time from the FIR filter,
The FIR filter is
A first adder for adding an output signal from a predetermined tap upstream of the center and an output signal from a predetermined tap downstream of the center; and the output corresponding to the output of the first adder A multiplier that multiplies the output of the first adder by a filter coefficient; and a band-limited output unit that outputs a predetermined band-limited output signal per unit time based on the output of the multiplier;
The decimation circuit is
By thinning out every other output signal per unit time from the band limited output unit of the FIR filter, the predetermined band limited output signal is frequency-converted to ½ the sampling frequency and output. And a signal processing circuit. The signal processing circuit according to claim 1,
In the first delay unit of the FIR filter, 4m−1 (m is an integer of 1 or more) the delay elements are connected in series,
The FIR filter is
At time Tn per unit time (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k) th (k = 1 (when m = 1) or k = 1,2 of the first delay unit) (when m = 2) or k = 1,..., m−1, m (when m ≧ 3)), the output signal is selected and output, while when n is an odd number, the first A first signal selection unit that selects and outputs an output signal from the (2m + 2k-2) th tap of the delay unit;
The first adder of the FIR filter includes the first delay unit when the output signal from the (2m-2k + 1) -th tap of the first delay unit and n from the first signal selection unit are an even number. Or the output signal of the (2m + 2k) th tap of the first delay unit when n from the first signal selection unit is an odd number. outputs the (m−k + 1) th addition signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient, and (2m−2k + 1) th. The (m−k + 1) th addition signal from the first adder is multiplied by the (2m−2k + 2) th filter coefficient to multiply the (2m−2k + 2) th filter signal. Outputs the multiplication signal,
Furthermore, the FIR filter is
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the multiplication unit is selected and output, while when n is an odd number, the second multiplication signal is output. When m is 2 or more, at time Tn, when n is an even number, the (2m-2k + 1) -th multiplication signal from the multiplication unit is selected while n is an odd number. Includes a second signal selection unit that selects the (2m-2k + 2) th multiplication signal, adds the selected multiplication signals, and outputs the result.
The band-limited output unit of the FIR filter includes a second delay unit that delays an output signal from the second signal selection unit by the unit time, an output signal from the second signal selection unit, and the second delay unit. A second adder for adding the output signal from
The decimation circuit is
At time Tn, when n is an odd number, the output signal from the second addition section is thinned out, and when n is an even number, the signal processing circuit outputs the output signal from the second addition section. . The signal processing circuit according to claim 1,
In the first delay unit of the FIR filter, 4m (m is an integer of 1 or more) the delay elements are connected in series,
The FIR filter is
At time Tn per unit time (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k + 1) -th (k = 1 (when m = 1)) or k = 1,2 of the first delay unit (when m = 2) or k = 1,..., m−1, m (when m ≧ 3)), the output signal is selected and output, while when n is an odd number, the first A first signal selection unit that selects and outputs an output signal from the (2m + 2k−1) -th tap of the delay unit;
The first adder of the FIR filter includes the first delay unit when the output signal from the (2m-2k + 1) -th tap of the first delay unit and n from the first signal selection unit are an even number. Or the output signal of the (2m + 2k + 1) th tap of the first delay unit when n from the first signal selection unit is an odd number, and the output signal of the (2m + 2k + 1) th tap of outputs the (m−k + 1) th addition signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient, and (2m−2k + 1) th. The (m−k + 1) th addition signal from the first adder is multiplied by the (2m−2k + 2) th filter coefficient to multiply the (2m−2k + 2) th filter signal. A first multiplier for outputting a multiplication signal, and an output signal from the (2m + 1) th tap of the first delay unit is multiplied by the (2m + 1) th filter coefficient to obtain a (2m + 1) th multiplication signal. A second multiplier for outputting,
Furthermore, the FIR filter is
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the first multiplication unit is selected and output, while when n is an odd number, the second multiplication is performed. When m is equal to or greater than 2, when m is equal to or greater than 2, when n is an even number, the (2m-2k + 1) th multiplication signal from the first multiplication unit is selected, while n A second signal selection unit that selects the (2m−2k + 2) th multiplication signal when the number is an odd number, and adds and outputs the selected multiplication signals;
At time Tn, when n is an even number, the (2m + 1) th multiplication signal from the second multiplication unit is selected, and when n is an odd number, a signal representing a constant 0 is selected and selected. A third signal selection unit that adds and outputs the output signal from the second signal selection unit,
The band-limited output unit of the FIR filter includes a second delay unit that delays an output signal from the third signal selection unit by the unit time, an output signal from the third signal selection unit, and the second delay unit. A second adder for adding the output signal from
The decimation circuit is
At time Tn, when n is an odd number, the output signal from the second addition section is thinned out, and when n is an even number, the signal processing circuit outputs the output signal from the second addition section. . The signal processing circuit according to claim 1,
The first delay unit of the FIR filter includes 4m + 1 (m is an integer of 1 or more) delay elements connected in series.
The FIR filter is
At time Tn per unit time (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k + 2) th (k = 1 (when m = 1) or k = 1,2 of the first delay unit) (when m = 2) or k = 1,..., m−1, m (when m ≧ 3)), the output signal is selected and output, while when n is an odd number, the first A first signal selection unit that selects and outputs an output signal from the (2m + 2k) th tap of the delay unit;
The first adder of the FIR filter includes the first delay unit when the output signal from the (2m-2k + 1) -th tap of the first delay unit and n from the first signal selection unit are an even number. The (2m + 2k + 2) -th tap output signal or the (2m + 2k) -th tap output signal of the first delay unit when n is an odd number from the first signal selection unit is added to the (m -K + 1) output the added signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient, and (2m−2k + 1) th. The (m−k + 1) th addition signal from the first adder is multiplied by the (2m−2k + 2) th filter coefficient to multiply the (2m−2k + 2) th filter signal. A first multiplier for outputting a multiplication signal, and an output signal from the (2m + 1) th tap of the first delay unit is multiplied by the (2m + 1) th filter coefficient to obtain a (2m + 1) th multiplication signal. A second multiplier for outputting,
Furthermore, the FIR filter is
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the first multiplication unit is selected and output, while when n is an odd number, the second multiplication is performed. When m is equal to or greater than 2, when m is equal to or greater than 2, when n is an even number, the (2m-2k + 1) th multiplication signal from the first multiplication unit is selected, while n A second signal selection unit that selects the (2m−2k + 2) th multiplication signal when the number is an odd number, and adds and outputs the selected multiplication signals;
A second adder for adding and outputting the output signal from the second signal selector and the (2m + 1) -th multiplied signal from the second multiplier,
The band-limited output unit of the FIR filter includes a second delay unit that delays the output signal from the second adder unit by the unit time, an output signal from the second adder unit, and a second delay unit. A third adder for adding the output signal;
The decimation circuit is
At time Tn, when n is an odd number, the output signal from the third adder is thinned out, and when n is an even number, the signal processing circuit outputs the output signal from the third adder. . The signal processing circuit according to claim 1,
In the first delay unit of the FIR filter, 4m + 2 (m is an integer of 1 or more) the delay elements are connected in series,
The FIR filter is
At time Tn per unit time (n is an integer equal to or greater than 1), when n is an even number, (2m + 2k + 3) th (k = 1 (when m = 1) or k = 1,2 of the first delay unit) (when m = 2) or k = 1,..., m−1, m (when m ≧ 3)), the output signal is selected and output, while when n is an odd number, the first A first signal selection unit that selects and outputs an output signal from the (2m + 2k + 1) -th tap of the delay unit;
The first adder of the FIR filter includes the first delay unit when the output signal from the (2m-2k + 1) -th tap of the first delay unit and n from the first signal selection unit are an even number. The (2m + 2k + 1) -th tap output signal or the (2m + 2k + 1) -th tap output signal of the first delay unit when n from the first signal selection unit is an odd number is added, and the (m -K + 1) output the addition signal and add the output signal from the (2m + 1) th tap of the first delay unit and the output signal from the (2m + 3) th tap of the first delay unit , Output the (m + 1) th addition signal,
The multiplication unit of the FIR filter multiplies the (m−k + 1) th addition signal from the first addition unit by the (2m−2k + 1) th filter coefficient, and (2m−2k + 1) th. The (m−k + 1) th addition signal from the first adder is multiplied by the (2m−2k + 2) th filter coefficient to multiply the (2m−2k + 2) th filter signal. A first multiplier that outputs a multiplication signal, and a (2m + 1) th multiplication signal by multiplying the (m + 1) th addition signal from the first addition unit by the (2m + 1) th filter coefficient. A second multiplier that outputs and outputs the (2m + 2) th multiplied signal by multiplying the output signal from the (2m + 1) th tap of the first delay unit by the (2m + 2) th filter coefficient Have
Furthermore, the FIR filter is
When m is 1, at time Tn, when n is an even number, the first multiplication signal from the multiplication unit is selected and output, while when n is an odd number, the second multiplication signal is output. When m is 2 or more, at time Tn, when n is an even number, the (2m-2k + 1) -th multiplication signal from the multiplication unit is selected while n is an odd number. Selects a (2m-2k + 2) th multiplication signal, adds the selected multiplication signals, and outputs the second signal selection unit;
At time Tn, when n is an even number, the (2m + 1) th multiplication signal from the second multiplication unit is selected, while when n is an odd number, the (2m + 2) th multiplication signal from the second multiplication unit is selected. A third signal selection unit that selects the multiplication signal, adds the selected signal and the output signal from the second signal selection unit, and outputs the added signal;
The band-limited output unit of the FIR filter includes a second delay unit that delays an output signal from the third signal selection unit by the unit time, an output signal from the third signal selection unit, and the second delay unit. A second adder for adding the output signal from
The decimation circuit is
At time Tn, when n is an odd number, the output signal from the second addition section is thinned out, and when n is an even number, the signal processing circuit outputs the output signal from the second addition section. .

Images