JP2007273667A - Electroplating method - Google Patents

Electroplating method Download PDF

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JP2007273667A
JP2007273667A JP2006096515A JP2006096515A JP2007273667A JP 2007273667 A JP2007273667 A JP 2007273667A JP 2006096515 A JP2006096515 A JP 2006096515A JP 2006096515 A JP2006096515 A JP 2006096515A JP 2007273667 A JP2007273667 A JP 2007273667A
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hole
plating
substrate
shielding plate
holes
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Hisahiro Minoshima
久博 簑島
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Hitachi Kokusai Electric Inc
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Hitachi Kokusai Electric Inc
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/008Current shielding devices

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electroplating method which forms fine pattern of high aspect ratio, that has been incapable of forming by electrolytic copper plating (e.g. subtractive (panel plating)) method. <P>SOLUTION: A printed board 5-1' is electroplated, by using shield plates 9' having holes 21-1 to 21-3, corresponding to holes 22-1 to 22-3 for through-holes of the printed board 5-1' by inhibiting the electroplating current from flowing to the printed board 5-1'. This plating method is effective, especially on a multilayer printed board that is to have a high aspect ratio. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、例えば、プリント基板の製造方法に関し、特に、スルホールに対する電解めっきに関する。   The present invention relates to, for example, a method for manufacturing a printed circuit board, and more particularly to electrolytic plating for through holes.

従来のプリント基板の製造方法を図1(a) 〜(d) を参照して説明する。
図1は、プリント基板の積層プレス工程における製造の様子の一例として、4層基板及び6層基板を組み合わせて製造する際の積層の断面の一例を示してある。
まず、図1(a) に示すように、内層パターン 2 をその両面に形成したコア材 1-1 と 1-2 とを作成し、上から順に、銅箔 4-1 、プリプレグ 3-1 、コア材 1-1 、プリプレグ 3-2 、コア材 1-2 、プリプレグ 3-3 、銅箔 4-2 を順に重ねる。その後、積層プレス機で加熱接着して、1枚の基板(積層後の基板)を作成する。
A conventional method for manufacturing a printed circuit board will be described with reference to FIGS.
FIG. 1 shows an example of a cross-section of a laminate when manufacturing a combination of a four-layer substrate and a six-layer substrate as an example of the state of manufacture in the multilayer press step of the printed circuit board.
First, as shown in FIG. 1 (a), core materials 1-1 and 1-2 with inner layer pattern 2 formed on both sides are prepared, and copper foil 4-1 prepreg 3-1, Core material 1-1, prepreg 3-2, core material 1-2, prepreg 3-3, and copper foil 4-2 are stacked in this order. Then, it heat-bonds with a lamination press machine, and produces one board | substrate (board | substrate after lamination | stacking).

次に、図1(b) に示すように、積層後の基板にNC 穴あけ機でスルホール用の穴 90 をあけ、デスミア処理を施して、無電解銅めっきを行い、無電解銅めっき膜 6 を形成する(基板 5-1 )。
次に、図1(c) に示すように、基板 5-1 に電解銅めっきをして、更に厚い銅めっき膜 7 を形成する(基板 5-2 )。なお、図1(c) 中に描かれた矢印は電解めっきの銅イオンの流れを模式的に示している。
次に、図1(d) に示すように、基板 5-2 にエッチング等によって銅めっき層 7 から余分の部分を除去して、外層パターン 8 を形成後、ソルダーレジストを印刷し、更に表面処理を行って基板 5-3 が完成する。
Next, as shown in Fig. 1 (b), through-holes 90 are drilled on the laminated substrate with an NC drilling machine, desmeared, electroless copper plated, and electroless copper plated film 6 is formed. Form (Substrate 5-1).
Next, as shown in FIG. 1C, electrolytic copper plating is applied to the substrate 5-1 to form a thicker copper plating film 7 (substrate 5-2). In addition, the arrow drawn in FIG.1 (c) has shown the flow of the copper ion of electrolytic plating typically.
Next, as shown in FIG. 1 (d), an extra portion is removed from the copper plating layer 7 by etching or the like on the substrate 5-2 to form an outer layer pattern 8, and then a solder resist is printed, and further surface treatment is performed. To complete the substrate 5-3.

図1(c) の電解銅めっきを行うための電解銅めっき槽について図2を用いて説明する。図2(a) は電解銅めっき槽を上から見た図(上面図)、図2(b) は電解銅めっき槽を右(図2(a) 矢印 A の方向)から見た場合の遮蔽板 9 の図である。
図2において、電解銅めっき槽にはめっき液が入れられ、めっき液中に基板 5 、遮蔽板 9 、及び、アノードボール(陽極棒)10 が浸漬されている。
遮蔽板 9 には、中央に開口部(貫通)が設けられ、銅イオンが移動し易いようにしている。
基板 5 の左右に遮蔽板 9 とアノードボール 10 とを所定の距離をおいて設置する。このとき、遮蔽板 9 とアノードボール 10 は固定されている。
The electrolytic copper plating tank for performing the electrolytic copper plating of FIG. 1 (c) will be described with reference to FIG. Fig. 2 (a) is a top view of the electrolytic copper plating bath, and Fig. 2 (b) is a shield when the electrolytic copper plating bath is viewed from the right (in the direction of arrow A in Fig. 2 (a)). It is a diagram of plate 9.
In FIG. 2, a plating solution is put in an electrolytic copper plating tank, and a substrate 5, a shielding plate 9, and an anode ball (anode rod) 10 are immersed in the plating solution.
The shielding plate 9 has an opening (penetration) in the center so that copper ions can easily move.
The shielding plate 9 and the anode ball 10 are placed on the left and right sides of the substrate 5 at a predetermined distance. At this time, the shielding plate 9 and the anode ball 10 are fixed.

近年の電子機器の小型化、高機能化の要求があり、それに伴いプリント基板も小型化、高密度化が要求されている。従来の方法では、高アスペクト比(基材 14 の板厚 t /キリ径 Φ)の基板の場合、スルホール穴内の均一電着性(めっきつきまわり)が悪いため、スルホール穴内のめっき厚を確保しようとすると、表面のめっき厚が厚くなる。   In recent years, there has been a demand for downsizing and high functionality of electronic devices, and accordingly, printed boards are also required to be downsized and high in density. In the conventional method, in the case of a substrate with a high aspect ratio (base material 14 thickness t / drilling diameter Φ), the uniform electrodeposition (through the plating) in the through hole is poor, so ensure the plating thickness in the through hole. Then, the plating thickness of the surface becomes thick.

図4は、プリント基板の表面のめっき厚が大きい場合のパターン形成上の問題点を説明するための図で、基板の一部の断面構造を示している。
図1(c) のようなサブトラクティブ法(パネルめっき法)による電解銅めっきを行うために、上記図2のような電解銅めっき槽を用いためっき法(例えば、特許文献1参照。)を用いる場合、めっき厚が薄い方がパターン形成に有利である。このため、図4(a) に示すようにエッチングレジスト 11 の間隙が狭いと、銅めっき膜 7 から余分の部分を除去してできる外層パターン 8 は、図4(b) に示すようにエッチング後導体パターン側壁でショートが発生してしまい、微細なパターンの形成が難しい。
特開2002−121694号公報
FIG. 4 is a diagram for explaining a problem in pattern formation when the plating thickness on the surface of the printed circuit board is large, and shows a partial cross-sectional structure of the substrate.
In order to perform electrolytic copper plating by a subtractive method (panel plating method) as shown in FIG. 1 (c), a plating method using an electrolytic copper plating tank as shown in FIG. 2 (for example, see Patent Document 1). When used, a thinner plating thickness is advantageous for pattern formation. For this reason, when the gap between the etching resists 11 is narrow as shown in FIG. 4 (a), the outer layer pattern 8 formed by removing the excess portion from the copper plating film 7 is etched after the etching as shown in FIG. 4 (b). A short circuit occurs on the side wall of the conductor pattern, making it difficult to form a fine pattern.
JP 2002-121694 A

上述の従来技術には、高アスペクト比の基板の場合、微細パターンの形成が困難であるという欠点があった。
本発明の目的は、上記のような欠点を除去し、従来の電解銅めっき法(例えば、サブトラクティブ法(パネルめっき法))では不可能であった微細パターンを形成可能となる電解めっき方法を提供することにある。
The prior art described above has a drawback that it is difficult to form a fine pattern in the case of a high aspect ratio substrate.
An object of the present invention is to provide an electrolytic plating method that eliminates the above-described drawbacks and enables formation of a fine pattern that is impossible with conventional electrolytic copper plating methods (for example, subtractive method (panel plating method)). It is to provide.

上記の目的を達成するため、本発明のめっき方法は、プリント基板のスルホールと対応させた位置に穴をあけた遮蔽板を使用して電解めっきするものである。
そして、穴を開けた部分以外は、遮蔽板によって、プリント基板表面には電解めっきの電流が流れないようにする。
In order to achieve the above object, the plating method of the present invention is to perform electrolytic plating using a shielding plate having a hole in a position corresponding to a through hole of a printed board.
Then, except for the portion where the hole is formed, the shielding plate prevents the electrolytic plating current from flowing on the surface of the printed board.

本発明によれば、プリント基板の穴(スルホール)と対応している位置にあいた穴を備えた遮蔽板を用いて電解銅めっきを行うため、アスペクト比の高い基板のサブトラクティブ法(パネルめっき法)による微細なパターンの形成が容易になる。更に、穴内の均一電着性をあげることができるため、高アスペクト比の基板のスルホールの接続信頼性が向上する。また更に、遮蔽板を作成するのに通常のNC 穴あけ機とデータが利用できるので、効率的であり、開発コストを削減できる。   According to the present invention, since electrolytic copper plating is performed using a shielding plate provided with a hole in a position corresponding to a hole (through hole) of a printed circuit board, a subtractive method (panel plating method) for a substrate having a high aspect ratio is performed. ) Makes it easy to form a fine pattern. Furthermore, since the electrodeposition in the hole can be improved, the through hole connection reliability of the high aspect ratio substrate is improved. Furthermore, the normal NC drilling machine and data can be used to create the shielding plate, which is efficient and can reduce development costs.

本発明の一実施例を、図5〜図7を参照して説明する。図5は、本発明の一実施例の遮蔽板とプリント基板との関係を説明するための図である。また、図6は、めっき槽中のプリント基板の一部の断面図と、電解めっき銅の動きを矢印で示した図である。また、図7は、プリント基板の表面のめっきとパターン形成について説明するための図で、本発明の遮蔽板を使用する際の無電解銅めっき後の6層板の一実施例を示した基板の一部の断面図である。
図5(a) は本発明の遮蔽板 9′の一実施例を示す斜視図である。図5(a) において、塩化ビニール製の板を用意し、NC 穴あけ機を用いて、NC ドリル 13 で、基板 5-1′のスルホール穴位置に対応する位置に、穴をあける。その穴径は、例えば、基板5-1′ のスルホール穴径より大きな穴である。例えば、基板5-1′のスルホール穴径の n 倍等である( n は、正の数で、1より小さくても良い)。もちろんこの穴径は、基板の中央部と端部では異なる比率にしても良い。また、遮蔽板の表側と裏側で穴径が異なる等、穴の断面がテーパ状等一定でなくても良い。図5(b) は遮蔽板 9′の穴あけ後の平面図である。
この穴の位置は、スルホールの穴位置と同じである場合には、スルホール用の穴位置データ、即ち、NC 穴あけ機のデータが利用可能である。
An embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a diagram for explaining the relationship between the shielding plate and the printed board according to an embodiment of the present invention. FIG. 6 is a cross-sectional view of a part of the printed circuit board in the plating tank, and the movement of the electrolytically plated copper indicated by arrows. FIG. 7 is a diagram for explaining the plating and pattern formation on the surface of the printed board, and is a board showing an example of a six-layer board after electroless copper plating when using the shielding plate of the present invention. FIG.
FIG. 5 (a) is a perspective view showing an embodiment of the shielding plate 9 'of the present invention. In FIG. 5 (a), a vinyl chloride plate is prepared, and an NC drill 13 is used to drill a hole at a position corresponding to the through hole position of the substrate 5-1 'using an NC drilling machine. The hole diameter is, for example, a hole larger than the through-hole diameter of the substrate 5-1 ′. For example, it is n times the through-hole diameter of the substrate 5-1 ′ (n is a positive number and may be smaller than 1). Of course, this hole diameter may be a different ratio between the central portion and the end portion of the substrate. Moreover, the hole cross-section may not be constant, such as a tapered shape, such as the hole diameter being different between the front side and the back side of the shielding plate. FIG. 5 (b) is a plan view of the shielding plate 9 'after drilling.
If the position of the hole is the same as the hole position of the through hole, the hole position data for the through hole, that is, the data of the NC drilling machine can be used.

図5(c) は遮蔽板 9′を使用するためのスルホール用穴があるめっき前のプリント基板である。図5(a) 〜(c) においては、記載が煩雑なため、一部の穴の関係についてだけ説明する。
図5(a) に示す遮蔽板 9′の穴 21-1 、21-2 、及び 21-3 と図5(b) に示す遮蔽板 9′の穴 21-1 、21-2 、及び 21-3 は同じ穴であり、図5(c) に示す基板 5-1′ でのスルホール用の穴 22-1 、22-2 、及び 22-3 とは、それぞれの枝番に対応する穴が中心で同じ位置で配置している。
FIG. 5 (c) shows a printed circuit board before plating with a through hole for using the shielding plate 9 '. 5 (a) to 5 (c), since the description is complicated, only the relationship between some holes will be described.
The holes 21-1, 21-2, and 21-3 of the shielding plate 9 'shown in FIG. 5 (a) and the holes 21-1, 21-2, and 21- of the shielding plate 9' shown in FIG. 5 (b). 3 is the same hole, and the holes 22-1, 22-2, and 22-3 for the through hole in the substrate 5-1 ′ shown in FIG. 5 (c) are centered on the holes corresponding to the respective branch numbers. In the same position.

図5(d) は、本発明の電解銅めっきを行うための電解銅めっき槽について説明するための図で、図5(d) は電解銅めっき槽を上から見た図(上面図)である。
図5(d) において、電解銅めっき槽にはめっき液が入れられ、めっき液中に基板 5-1′ 、遮蔽板 9′、及び、アノードボール 10 が浸漬されている。このように、図5(a) (b) で説明した遮蔽板 9’を、基板 5-1′とアノードボール 10 との間に、基板 5-1′からの間隔を狭く(例えば、10 mm 以下)設置する。
即ち、遮蔽板 9′の穴位置と基板 5-1′の穴位置は、アノードボール10 から基板 5-1′のスルホール用の穴 22-1 を遮蔽板 9′の穴 21-1 を通してみることができる位置にある。基板 5-1′の他のスルホール用穴と遮蔽板 9′の他の穴との関係も、対応する穴同士で同様の関係である。
FIG. 5 (d) is a view for explaining an electrolytic copper plating tank for performing electrolytic copper plating of the present invention, and FIG. 5 (d) is a view (top view) of the electrolytic copper plating tank as viewed from above. is there.
In FIG. 5 (d), a plating solution is put in an electrolytic copper plating tank, and a substrate 5-1 ', a shielding plate 9', and an anode ball 10 are immersed in the plating solution. In this way, the shielding plate 9 ′ described in FIGS. 5 (a) and 5 (b) has a narrow space between the substrate 5-1 ′ and the anode ball 10 from the substrate 5-1 ′ (for example, 10 mm). Below) Install.
That is, the hole position of the shielding plate 9 'and the hole position of the substrate 5-1' are as follows: from the anode ball 10 through the hole 22-1 for the through hole of the substrate 5-1 'through the hole 21-1 of the shielding plate 9'. Is in a position where The relationship between the other hole for the substrate 5-1 'and the other hole for the shielding plate 9' is the same for the corresponding holes.

次に、図6に示すように、図5(d) の本発明の一実施例のめっき槽中で電解銅めっきを行い、スルホール壁面に、厚い銅めっき膜(スルホール壁面めっき層 12 )を形成する。なお、図6中に描かれた矢印は電解めっきの銅イオンの流れを模式的に示している。
図に示すように、電解めっきのための銅イオンの流れは、基板 5-1′の表面では遮蔽板 9′で遮断されてめっき厚を小さくでき、一方、スルホール用の穴の壁面はめっき厚を大きくすることができる。
更に、電解めっきの電流量(電流密度)を減らす効果もある。
Next, as shown in FIG. 6, electrolytic copper plating is performed in the plating tank of one embodiment of the present invention shown in FIG. 5 (d) to form a thick copper plating film (through hole wall surface plating layer 12) on the through hole wall surface. To do. In addition, the arrow drawn in FIG. 6 has shown typically the flow of the copper ion of electroplating.
As shown in the figure, the flow of copper ions for electrolytic plating is blocked by the shielding plate 9 'on the surface of the substrate 5-1', and the plating thickness can be reduced, while the wall surface of the hole for the through hole has a plating thickness. Can be increased.
Furthermore, there is an effect of reducing the amount of current (current density) of electrolytic plating.

次に、図7に示すように、基板 5′(図7(a) )の外層パターン 7′からエッチング等によって余分の部分を除去し、外層パターン 8′を形成後、ソルダーレジストを印刷し、更に表面処理を行って基板 5′が完成する(図7(b) )。
以上のように、図5(d) のように、スルホール用の穴の位置に対応して穴あけをした遮蔽板9’を設置することで、基板 5′の表面の電流密度を下げ、表面のめっきが厚くなるのを防ぐことができる。
Next, as shown in FIG. 7, the excess portion is removed from the outer layer pattern 7 'of the substrate 5' (FIG. 7 (a)) by etching or the like, and after forming the outer layer pattern 8 ', a solder resist is printed. Further surface treatment is performed to complete the substrate 5 '(FIG. 7 (b)).
As described above, as shown in FIG. 5 (d), by installing the shielding plate 9 'in which holes are drilled corresponding to the positions of through holes, the current density on the surface of the substrate 5' is reduced, and the surface It is possible to prevent the plating from becoming thick.

上記のようにして、表面のめっき厚のばらつきを低減することで、エッチングによるパターン側壁のショートがなくなり、回路パターン形成時において微細なパターンを形成することができる。   As described above, by reducing the variation in the plating thickness of the surface, there is no short circuit of the pattern side wall due to etching, and a fine pattern can be formed at the time of circuit pattern formation.

本発明の他の実施例を、図8を参照して説明する。図8は、スルホール用の穴内にめっきが厚くつくことが知られている噴流装置等のめっき液をめっき槽中で流動させる銅めっき法と併用したものである。   Another embodiment of the present invention will be described with reference to FIG. FIG. 8 is used in combination with a copper plating method in which a plating solution such as a jet apparatus known to have a thick plating in a through hole is flowed in a plating tank.

なお、上述の実施例では、めっき材として銅を用いたが、銅に限る必要はなく、例えば、ニッケル、はんだ、等でも良い。また、遮蔽板の材質も塩化ビニールである必要はなく、絶縁性がある材料であれば良い。   In the above-described embodiment, copper is used as the plating material. However, the plating material is not limited to copper, and may be nickel, solder, or the like. Further, the material of the shielding plate does not need to be vinyl chloride, and any material having an insulating property may be used.

上記実施例に拠れば、プリント基板のスルホール穴と対応している位置にあいた穴をもつ遮へい板を用いて、プリント基板のスルホール穴とアノード電極とを結ぶ直線状に遮蔽板の穴を配置して電解銅めっきを行うため、アスペクト比5 以上を有するプリント基板のサブトラクティブ法(パネルめっき法)による微細なパターン(例えば、ライン幅 75 μm 以下)の形成が容易に実現できた。   According to the above embodiment, using the shielding plate having the hole corresponding to the through hole hole of the printed circuit board, the hole of the shielding plate is arranged in a straight line connecting the through hole hole of the printed circuit board and the anode electrode. Since electrolytic copper plating is performed, formation of a fine pattern (for example, a line width of 75 μm or less) by a subtractive method (panel plating method) of a printed circuit board having an aspect ratio of 5 or more was easily realized.

更に、スルホール穴内の均一電着性をあげることができるため、高アスペクト比の基板のスルホールの接続信頼性が向上した。
また更に、本発明の遮蔽板を作成するための遮蔽板の穴あけに、通常の NC 穴あけ機のデータが利用できるため、効率的であり、開発コストを削減できた。
なお、本発明は、特に高アスペクト比となる多層プリント基板で有効である。
Furthermore, since it is possible to improve the throwing power in the through hole, the connection reliability of the through hole of the high aspect ratio substrate is improved.
Furthermore, since data of a normal NC drilling machine can be used for drilling the shielding plate for producing the shielding plate of the present invention, it is efficient and the development cost can be reduced.
The present invention is particularly effective for a multilayer printed board having a high aspect ratio.

従来の電解銅めっき方法を用いた6層板の製造例を説明するための断面図。Sectional drawing for demonstrating the manufacture example of the 6 layer board using the conventional electrolytic copper plating method. 電解銅めっき槽を上から見た図と遮蔽板を示した正面図。The front view which showed the figure which looked at the electrolytic copper plating tank from the top, and the shielding board. 高アスペクト比の時の基板の断面図。Sectional drawing of a board | substrate at the time of a high aspect ratio. 表面のめっき厚が厚い場合について説明するための断面図。Sectional drawing for demonstrating the case where the plating thickness of the surface is thick. 本発明の一実施例を説明するための図。The figure for demonstrating one Example of this invention. 本発明の一実施例を説明するための図。The figure for demonstrating one Example of this invention. 本発明の一実施例を説明するための図。The figure for demonstrating one Example of this invention. 本発明の一実施例を説明するための図。The figure for demonstrating one Example of this invention.

符号の説明Explanation of symbols

1-1,1-2:コア材、 2:内層パターン、 3-1,3-2、3-3:プリプレグ、 4-1,4-2:銅箔、 5,5′,5-1,5-1′,5-2,5-3:基板、 6:無電解銅めっき膜、 7,7′:銅めっき膜、 8,8′:外層パターン、 9,9′:遮蔽板、 10:アノードボール、 11:エッチングレジスト、 12:スルホール壁面めっき層、 13:NC ドリルビット、 14:基材、 21:穴、 22:スルホール用穴。   1-1, 1-2: Core material, 2: Inner layer pattern, 3-1, 3-2, 3-3: Prepreg, 4-1, 4-2: Copper foil, 5, 5 ', 5-1, 5-1 ', 5-2, 5-3: substrate, 6: electroless copper plating film, 7, 7': copper plating film, 8, 8 ': outer layer pattern, 9, 9': shielding plate, 10: Anode ball, 11: etching resist, 12: through hole wall plating layer, 13: NC drill bit, 14: base material, 21: hole, 22: hole for through hole.

Claims (1)

プリント基板のスルホールと対応させた位置に穴をあけた遮蔽板を使用したことを特徴とする電解めっき方法。 An electrolytic plating method characterized by using a shielding plate having a hole in a position corresponding to a through hole of a printed board.
JP2006096515A 2006-03-31 2006-03-31 Electroplating method Pending JP2007273667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006096515A JP2007273667A (en) 2006-03-31 2006-03-31 Electroplating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006096515A JP2007273667A (en) 2006-03-31 2006-03-31 Electroplating method

Publications (1)

Publication Number Publication Date
JP2007273667A true JP2007273667A (en) 2007-10-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006096515A Pending JP2007273667A (en) 2006-03-31 2006-03-31 Electroplating method

Country Status (1)

Country Link
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