JP2007267257A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the increase of a circuit area and reduce the number of fuses which are cut. <P>SOLUTION: The semiconductor device is provided with a plurality of regular fuses and logical information fuses which are the fuses to generate information stored by the regular fuse by generating a logical relation with the output of the regular fuse and are provided with one set with respect to the N pieces (N is natural integer of higher than 2) of the regular fuses to show logical information in reference to the cut of the corresponding regular fuse. When many regular fuses are cut, the logical information fuse is cut and logics are converted so as to cut the regular fuse which is not cut by an original logic, whereby the number of cut fuses can be reduced without changing the circuit area substantially. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a fuse.

  In recent years, the number of fuses mounted in a semiconductor device such as an LSI has increased with an increase in circuit scale, and the number of fuses sometimes exceeds 1000. Usually, after performing a tester test on a wafer, a fuse mounted on a semiconductor device is cut using a fuse cutting device. Due to an increase in the number of fuses mounted on a semiconductor device, the time required for cutting a fuse per chip increases and becomes enormous.

  As a method for avoiding this problem, as disclosed in Patent Document 1, a positive logic block and a negative logic block are separately prepared in a redundant logic circuit of a memory, and fuses are respectively provided in a positive logic block and a negative logic block. A separate one has been proposed. When the fuse is cut according to the address to be written, if the address to be cut has a large value “0”, the fuse in the positive logic block is cut by the positive logic, and the address to be cut has a large value “1”. In this case, the number of fuses to be cut is reduced by cutting the fuses in the negative logic block with negative logic.

JP-A-9-288900

  However, in the method described in Patent Document 1, it is necessary to provide each logic block (positive logic block and negative logic block), and the circuit area is about twice that of a normal circuit system. When the circuit area increases and the chip size increases, this leads to a decrease in yield and an increase in price. Therefore, such an increase in circuit area is difficult to tolerate.

  The present invention has been made in view of such circumstances, and an object thereof is to suppress an increase in circuit area and to reduce the number of fuses to be cut.

  The semiconductor device of the present invention includes a plurality of first fuses and a logic information fuse provided one for N (N is a natural number of 2 or more) first fuses. The first fuse stores binary information, and the logic information fuse indicates logic information related to the cutting of the corresponding N first fuses. The information stored by the first fuse is generated by taking the logic of the output from the first fuse and the logic information fuse.

  According to the present invention, in the first fuse corresponding to the logic information fuse, when a large number of fuses are cut, for example, the number of fuses to be cut exceeds a majority, the logic information fuse is cut and inverted. The first fuse is cut by logic. By cutting the logic information fuse and inverting the logic related to the cutting of the first fuse, the number of fuses to be cut can be reduced with almost no change in circuit area.

  According to the present invention, for a plurality of fuses, one logic information fuse indicating logic information related to the cutting is provided, and the logic related to the cutting of the corresponding fuse is controlled depending on whether the logic information fuse is cut or not. Thus, the number of fuses to be cut can be reduced while suppressing an increase in circuit area.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the following description, the value output from the fuse depending on whether the fuse is cut or not is output with the value “0” (the signal level is low) when the fuse is not cut. If it is, the value “1” (the signal level is high) is output.

  1A to 1C are explanatory views of the principle of a semiconductor device according to an embodiment of the present invention. FIG. 1A shows a hierarchical structure of fuses included in the semiconductor device of this embodiment.

  The semiconductor device in the present embodiment has a plurality of normal fuses, and further provides one logical information fuse for N (N is a natural number of 2 or more) normal fuses. In the example shown in FIG. 1A, a case where one logical information fuse FA1 is provided for eight normal fuses F1 to F8 is shown.

  Normally, the fuse can store binary information, and is used for storing redundancy switching information for improving yield, chip relief in an SRAM or the like, and a chip ID for identifying a chip. The logic information fuse is used to indicate logic information related to the cutting of the corresponding normal fuse. The logical information fuse indicates information on whether the fuse is cut with positive logic or negative logic according to binary information to be stored in the normal fuse.

  Specifically, when the logic information fuse is not cut, the normal fuse is cut with positive logic, and when the logic information fuse is cut, the normal fuse is cut with negative logic. That is, in this embodiment, the logic related to the cutting of the corresponding fuse is controlled by the presence or absence of the cutting of the logic information fuse, and the logic related to the cutting of the corresponding fuse is inverted according to the cutting of the logic information fuse. Let

  For example, when the number of fuses to be cut exceeds half, the logic information fuse is cut to invert the logic, and the fuse that is not cut by the original logic is cut. As a result, the number of fuses to be cut becomes half or less, and the number of fuses to be cut can be reduced. Further, since only one logical information fuse is provided for a plurality of fuses, the above function can be realized with almost no change in circuit area, and the number of fuses to be cut can be reduced while suppressing an increase in circuit area. .

  For example, in the example shown in FIG. 1A, when the number of normal fuses to be cut is four or less, the logical information fuse FA1 is not cut and the normal fuses are replaced with the same logic (positive logic). Disconnect. On the other hand, when the number of normal fuses to be cut exceeds four (five or more), the logic information fuse FA1 is cut and the normal fuses are cut with inverted logic (negative logic). Therefore, the number of fuses to be cut is always less than half.

  In FIG. 1A, a case where one logical information fuse FA1 is provided for the normal fuses F1 to F8 is shown as an example. However, as will be described later, M pieces (M is a natural number of 2 or more). The logic information fuses may be hierarchized by providing one logic information fuse indicating logic information related to the cutting of the logic information fuses. In that case, the appropriate logic may be selected by appropriately cutting the hierarchical logic information fuses so that the total number of fuses to be cut in the normal fuse and the logic information fuse is minimized.

  FIG. 1B shows a logical configuration related to the fuse output in the semiconductor device of this embodiment, and FIG. 1C shows a truth table of the fuse output.

  In FIG. 1B, FOUT1, FOUT2, FOUT3,... Are output values based on the respective normal fuses, and FOUTA1 is an output value based on the logical information fuse corresponding to the normal fuses. OP1, OP2, OP3,... Are arithmetic circuits that perform logical operations on the output values FOUT1, FOUT2, FOUT3,... And the output value FOUTA1, and output the calculation results as output values OUT1, OUT2, OUT3,. To do. For the arithmetic circuits OP1, OP2, OP3,..., An EX-OR arithmetic circuit that performs an exclusive OR (EX-OR) operation using two inputs and outputs the operation result is used.

  That is, the logic configuration related to the fuse output in the present embodiment takes the logic (exclusive OR) of the values FOUT1, FOUT2, FOUT3,... Of each bit by the normal fuse and the value FOUTA1 by the logic information fuse, Fuse outputs OUT1, OUT2, OUT3,... Reflecting the logic information indicated by the logic information fuse are generated.

  Specifically, as shown in the truth table in FIG. 1C, when the output value based on the logical information fuse is “0”, that is, when the logical information fuse is not cut, the output value based on the normal fuse. Is output as a fuse output. On the other hand, when the output value based on the logical information fuse is “1”, that is, when the logical information fuse is cut, the output value based on the normal fuse is inverted and output as a fuse output.

  2A to 2C are diagrams illustrating specific configuration examples of fuses included in the semiconductor device according to the present embodiment.

  FIG. 2A shows a case where one logical information fuse is provided for a plurality of normal fuses. As an example, one logical information fuse is provided for 32 normal fuses F01 to F32. The case where FA1 is provided is shown. When cutting less than half of the fuses, the logic information fuse is not cut and the normal fuse is cut with the same logic (positive logic). On the other hand, when a majority of the fuses are to be cut, the logic information fuse is cut, and the normal fuse is cut with inverted logic (negative logic).

  For example, when there are 32 normal fuses F01 to F32, the number of fuses to be cut is 32 at maximum if there is no logical information fuse FA1. On the other hand, by providing the logic information fuse FA1 as in this embodiment, the number of fuses to be cut is (32/2) = 16 at the maximum, and the circuit area is slightly increased by providing the logic information fuse FA1. Only by increasing, the number of fuses to be cut can be reduced with almost no change in circuit area.

  FIG. 2B shows the case where the logical information fuses are hierarchized. For example, the first-layer logic information fuses FA1, FA2, FA3, and FA4 are provided for each of the 32 normal fuses F01 to F32 in units of eight. The logic information fuse FA1 is provided for the eight normal fuses F01 to F08, and the logic information fuse FA2 is provided for the eight normal fuses F09 to F16. Similarly, the logic information fuse FA3 is provided for the eight normal fuses F17 to F24, and the logic information fuse FA4 is provided for the eight normal fuses F25 to F32. Further, one second-level logic information fuse FB1 is provided for the four first-level logic information fuses FA1 to FA4.

  As shown in FIG. 2B, when hierarchical logic information fuses FA1 to FA4 and FB1 are provided for the 32 normal fuses F01 to F32, the number of fuses to be cut is maximum ( 8/2) × 4 + (4/2) = 18, and the number of fuses to be cut can be reduced.

  FIG. 2C shows a case where a logical information fuse is provided only for a normal fuse having a high cutting frequency among a plurality of normal fuses. The example shown in FIG. 2C shows a case where one logical information fuse FA1 ′ is provided for the normal fuses F17 to F24 having a high cutting frequency among the 32 normal fuses F01 to F32. . The fuse with a high cutting frequency varies depending on the logic of the chip, but the chip designer often knows a fuse with a high cutting frequency such as a redundant portion of the SRAM. Therefore, by providing the logic information fuse only for the fuse having a high cutting frequency, the number of fuses to be cut can be efficiently reduced, and an increase in circuit area can be further suppressed.

  FIG. 3 is a diagram illustrating a configuration example of a fuse output generation unit that generates a fuse output reflecting the logic information indicated by the logic information fuse based on the value stored in the fuse in the present embodiment. The fuse output generation unit in the present embodiment is configured on the same chip as the chip on which the fuse is mounted, and includes a reading circuit 31 and a logic synthesis circuit 32.

  The reading circuit 31 receives the fuse check signal FCHK and the clock signal CLK and outputs an output value FOUT. The reading circuit 31 reads the value stored by the fuse based on the fuse check signal FCHK, and outputs the read value as the output value FOUT based on the clock signal CLK.

FIG. 4A is a diagram illustrating a configuration example of the reading circuit 31.
In the reading circuit 31, the P-channel transistor TR1 has a source connected to the power supply and a drain connected to the drain of the N-channel transistor TR2. The N-channel transistor TR2 has a source connected to the ground level. A fuse check signal FCHK is supplied to the gates of the transistors TR1 and TR2. Here, the P-channel transistor TR1 is a so-called weak transistor having a small driving capability.

The fuse FUSE having the other end connected to the ground level and the capacitor C1 having the other end connected to the ground level are connected to the interconnection point of the drains of the transistors TR1 and TR2.
The flip-flop FF1 is supplied with a clock signal CLK via a clock input terminal, and a data input terminal is connected to an interconnection point between the drains of the transistors TR1 and TR2. The flip-flop FF1 outputs an output value FOUT from the data output terminal.

  As shown in FIG. 4B, the reading circuit 31 is reset when a positive pulse fuse check signal FCHK is input, and then the value stored by the fuse FUSE when the fuse check signal FCHK is inactivated. In the flip-flop FF1. Next, when the positive pulse clock signal CLK is input, the value fetched into the flip-flop FF1 is output as the output value FOUT.

  Here, the reading circuit 31 outputs a high level (“1”) signal as the output value FOUT when the fuse FUSE is cut, and the low level as the output value FOUT when the fuse FUSE is not cut. The signal (“0”) is output.

  Returning to FIG. 3, the logic synthesis circuit 32 is configured by, for example, a combinational circuit, and the output value FOUT from the reading circuit 31 is input and stored in the fuse output OUT reflecting the logic information indicated by the logic information fuse, that is, the normal fuse. Output information. Specifically, the logic synthesis circuit 32 performs a logical operation (exclusive OR operation) between the value of the normal fuse and the value of the logical information fuse supplied as the output value FOUT from the reading circuit 31, and the operation result is obtained. Output as fuse output OUT.

FIG. 5 is a diagram illustrating a configuration example of the logic synthesis circuit 32.
FIG. 5B shows a configuration example of the logic synthesis circuit 32 corresponding to the case where one logic information fuse FA1 is provided for the eight normal fuses F1 to F8 as shown in FIG. ing.

  In FIG. 5B, the output value FOUTi and the output value FOUTA1 supplied from the reading circuit 31 are input to the arithmetic circuit OPi (i is a subscript, i = 1 to 8). Each arithmetic circuit OPi performs an exclusive OR operation using these two inputs, and outputs the operation result as a fuse output OUTi. Here, the output value FOUTi is an output value read from the normal fuse Fi, and the output value FOUTA1 is an output value read from the logic information fuse FA1.

FIG. 6 is a diagram illustrating another configuration example of the logic synthesis circuit 32.
As shown in FIG. 6A, one first-tier logic information fuse FA1 is provided for eight normal fuses F1 to F8, and a plurality of first-tier logic information fuses FA1 provided similarly. , FA2,..., One second hierarchy logic information fuse is provided, that is, a configuration example of the logic synthesis circuit 32 corresponding to the case where the logic information fuses are hierarchized is shown in FIG. Show.

  In FIG. 6B, the output value FOUTAj and the output value FOUTB1 supplied from the reading circuit 31 are input to the arithmetic circuit OPAj (j is a subscript, j is a natural number). Each arithmetic circuit OPAj performs an exclusive OR operation using these two inputs and outputs the operation result. The operation circuit OPi (i is a subscript, i = 1 to 8) is inputted with the output of the operation circuit OPA1 and the output value FOUTi supplied from the reading circuit 31. Each arithmetic circuit OPi performs an exclusive OR operation using these two inputs, and outputs the operation result as a fuse output OUTi. Here, the output value FOUTi is an output value read from the normal fuse Fi, the output value FOUTAj is an output value read from the logic information fuse FAj, and the output value FOUTB1 is an output value read from the logic information fuse FB1. It is.

The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Supplementary Note 1) A plurality of first fuses that store binary information;
A fuse for generating information stored by the first fuse by taking the logic of the output from the first fuse, and N (N is a natural number of 2 or more) first fuses. A semiconductor device comprising: a logic information fuse that is provided for each of the N first fuses and indicates logic information related to the cutting of the corresponding N first fuses.
(Supplementary note 2) One M information (M is a natural number of 2 or more) logic information fuses are provided, and the logic information fuses further indicate logic information related to the cutting of the corresponding M logic information fuses. The semiconductor device according to appendix 1, which is characterized.
(Supplementary note 3) The semiconductor device according to Supplementary note 1 or 2, wherein the logic relating to the cutting of the fuse corresponding to the logical information fuse is inverted in accordance with the cutting of the logical information fuse.
(Supplementary note 4) When the logical information fuse is not cut, the fuse corresponding to the logical information fuse is cut with positive logic. When the logical information fuse is cut, the fuse corresponding to the logical information fuse is 3. The semiconductor device according to appendix 1 or 2, wherein the semiconductor device is cut by negative logic.
(Supplementary Note 5) Among the p fuses corresponding to the logic information fuse, when the number of fuses to be cut is equal to or greater than q (q is the minimum natural number satisfying q> (p / 2)), the logic 5. The semiconductor device according to any one of appendices 1 to 4, wherein the information fuse is cut and the logic related to the cutting of the fuse corresponding to the logic information fuse is inverted.
(Supplementary note 6) The supplementary note 1 is characterized in that the logic related to the cutting of the fuse can be selected by cutting the logical information fuse so that the total number of the first fuse and the logical information fuse to be cut is minimized. The semiconductor device of any one of -4.
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein the logic information fuse is provided only for the first fuse having a high cutting frequency.
(Supplementary note 8) a reading circuit for reading stored values from the first fuse and the logical information fuse;
A logic synthesis circuit that performs a logical operation on the value of the first fuse read by the reading circuit and the value of the logic information fuse, and generates information stored by the first fuse. The semiconductor device according to any one of appendices 1 to 7.
(Supplementary note 9) The semiconductor device according to supplementary note 8, wherein the logic synthesis circuit performs an exclusive OR operation between the value of the first fuse and the value of the logic information fuse.
(Additional remark 10) The reading circuit which reads the value memorize | stored in the said 1st fuse and the said logic information fuse which the semiconductor device of any one of Additional remark 1-7 has,
A logic synthesis circuit that performs a logical operation on the value of the first fuse read by the reading circuit and the value of the logic information fuse, and generates information stored by the first fuse. Semiconductor device.

It is a figure for demonstrating the principle of the semiconductor device by one Embodiment of this invention. It is a figure which shows the specific structural example of the fuse which the semiconductor device in this embodiment has. It is a figure which shows the structural example of the fuse output production | generation part in this embodiment. It is a figure which shows the structural example of the reading circuit in this embodiment. It is a figure which shows the structural example of the logic synthesis circuit in this embodiment. It is a figure which shows the other structural example of the logic synthesis circuit in this embodiment.

Explanation of symbols

F1-F32 Normal fuse FA1-FA4, FB1 Logic information fuse OP1-OP8, OPA arithmetic circuit (exclusive OR circuit)
31 Reading circuit 32 Logic synthesis circuit FOUT Normal fuse output FOUTA, FOUTB Logic information fuse output OUT Fuse output

Claims (5)

A plurality of first fuses for storing binary information;
A fuse for generating information stored by the first fuse by taking the logic of the output from the first fuse, and N (N is a natural number of 2 or more) first fuses. A semiconductor device comprising: a logic information fuse that is provided for each of the N first fuses and indicates logic information related to the cutting of the corresponding N first fuses.   One is provided for M (M is a natural number of 2 or more) logical information fuses, and further includes a logical information fuse indicating logical information related to cutting of the corresponding M logical information fuses. Item 14. A semiconductor device according to Item 1.   3. The semiconductor device according to claim 1, wherein the logic relating to the cutting of the fuse corresponding to the logic information fuse is inverted in accordance with the cutting of the logic information fuse.   Of the p fuses corresponding to the logical information fuse, when the number of fuses to be cut is q (q is the minimum natural number satisfying q> (p / 2)) or more, the logical information fuse is cut. 4. The semiconductor device according to claim 1, wherein logic relating to cutting of a fuse corresponding to the logic information fuse is inverted. 5.   4. The logic according to claim 1, wherein the logic information fuse is cut to select a logic related to the cutting of the fuse so that a total number of the first fuse and the logic information fuse to be cut is minimized. The semiconductor device according to any one of the above.

Images