JP2007258243A - Mos transistor characteristics detection device and cmos circuit characteristic automatic adjusting arrangement - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To automatically adjust an operation state of a CMOS circuit so that a MOS transistor in an objective circuit operates in a saturation region, while increase in circuit scale and power consumption is suppressed. <P>SOLUTION: A CMOS circuit characteristics automatic adjusting arrangement is provided with a replica signal generating circuit (10) for generating a replica signal that makes the drain voltage in the MOS transistor (101a) in the objective circuit (100) a minimum, a replica circuit (20) for receiving the replica signal, voltage buffers (30a and 30b) for receiving drain voltage of the MOS transistor in the objective circuit and the replica circuit, the MOS transistors (101c and 101d) for receiving output voltage of the voltage buffers in respective drains, a comparison circuit (40) for comparing the size of current flowing in the MOS transistors, and an adjusting circuit (50) for adjusting the operating states of the objective circuit and the replica circuit, based on the comparison result. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a device for detecting the operating state of a MOS transistor, and in particular, detects whether or not a MOS transistor used as a constant current source in a CMOS circuit operates in a saturation region (hereinafter also referred to as saturation region operability). And an apparatus for automatically adjusting the operating state of a CMOS circuit based on the detection result.

  Conventionally, in a CMOS circuit, it is known that the threshold voltage of a MOS transistor fluctuates due to process variations and temperature fluctuations, and the transistor characteristics are affected. On the other hand, with the recent process miniaturization, the withstand voltage of the gate oxide film is lowered and the power supply voltage is lowered, and the influence of the fluctuation of the threshold voltage of the MOS transistor on the transistor characteristics is increasing.

  For example, in the case of a constant current source that is an important element in an analog circuit, the MOS transistor that constitutes the constant current source needs to operate in a saturation region. However, as the power supply voltage decreases, the operation range of the transistor decreases and the threshold voltage varies. As a result, it becomes difficult to guarantee operation in the saturation region. For this reason, means for detecting the saturation region operability of the MOS transistor and, in some cases, means for automatically adjusting the operation state of the MOS transistor are required in order to guarantee the saturation region operability.

To solve this problem, conventionally, a threshold voltage of a MOS transistor is measured using a measurement circuit such as an AD converter, and the operation result of the MOS transistor is automatically adjusted by feeding back the measurement result (for example, Patent Documents). 1).
Japanese Patent Laid-Open No. 2002-76280 (page 7, FIG. 1)

  However, in the conventional method, the circuit scale and the power consumption increase because it is necessary to provide an AD converter. In view of this problem, the present invention is a device for detecting the saturation region operability of a MOS transistor while suppressing an increase in circuit scale and power consumption, and further, the operation state of the CMOS circuit so that the MOS transistor operates in the saturation region. It is an object of the present invention to provide an apparatus for automatically adjusting.

  The means taken by the present invention to solve the above problem is that the first MOS transistor in the target circuit is a device for detecting whether or not the first MOS transistor is operating in the saturation region. A replica signal generating circuit for generating a replica signal that minimizes the drain voltage of the MOS transistor, and a replica of the target circuit, the second MOS transistor corresponding to the first MOS transistor, and a replica signal , A first voltage buffer to which the drain voltage of the first MOS transistor is input, a second voltage buffer to which the drain voltage of the second MOS transistor is input, characteristics and a gate, The voltage applied to the source is the same as that of the first MOS transistor, and the output voltage of the first voltage buffer is applied to the drain M A first MOS transistor group having at least one S transistor, a MOS transistor having the same characteristics and an applied voltage of the gate and the source as the first MOS transistor, and an output voltage of the second voltage buffer applied to the drain And a comparison circuit for comparing the magnitude of the first current flowing in the first MOS transistor group and the second current flowing in the second MOS transistor group And

  According to this, the minimum drain voltage that can be taken by the first MOS transistor in the target circuit is reproduced in the second MOS transistor in the replica circuit, and these drain voltages are respectively obtained by the first and second voltage buffers. It is reproduced as the drain voltage of each MOS transistor in the first and second MOS transistor groups, and the comparison circuit compares the first and second currents flowing in the first and second MOS transistor groups, respectively. . Then, from the result of comparing the magnitudes of the first and second currents, it can be determined whether or not the first MOS transistor in the target circuit is operating in the saturation region.

  Specifically, the comparison circuit includes a first IV conversion circuit that converts a first current into a first voltage, a second IV conversion circuit that converts a second current into a second voltage, And a comparator for comparing the magnitudes of the first and second voltages.

  More specifically, each of the first and second IV conversion circuits is a diode-connected MOS transistor or a resistance element.

  Specifically, the first voltage buffer includes an operational amplifier to which the drain voltage of the first MOS transistor and the drain voltage of the MOS transistor in the first MOS transistor group are input, and the first MOS transistor group. And a MOS transistor connected to the gate and to which the output voltage of the operational amplifier is applied. Similarly, the second voltage buffer is connected to the operational amplifier to which the drain voltage of the second MOS transistor and the drain voltage of the MOS transistor in the second MOS transistor group are input, and to the second MOS transistor group. And a MOS transistor to which the output voltage of the operational amplifier is applied.

  Further, the means taken by the present invention in order to solve the above problems is an apparatus for automatically adjusting the operating state of the CMOS circuit so that the first MOS transistor in the target circuit in the CMOS circuit operates in a saturation region. A replica signal generation circuit that generates a replica signal that minimizes the drain voltage of the first MOS transistor if input to the target circuit, and a replica of the target circuit, which corresponds to the first MOS transistor. A replica circuit to which a replica signal is input; a first voltage buffer to which a drain voltage of the first MOS transistor is input; and a drain circuit to which a drain voltage of the second MOS transistor is input. 2 voltage buffer, the characteristics and the applied voltage of the gate and the source are the same as the first MOS transistor, The first MOS transistor group having at least one MOS transistor to which the output voltage of the first voltage buffer is applied in the rain, the characteristics, the applied voltage of the gate and the source are the same as those of the first MOS transistor, and the drain is A second MOS transistor group having at least one MOS transistor to which an output voltage of the second voltage buffer is applied; a first current flowing through the first MOS transistor group; and a second current flowing through the second MOS transistor group. It is assumed that a comparison circuit for comparing the current levels of the current circuit and an adjustment circuit for adjusting the operation states of the target circuit and the replica circuit based on the comparison result of the comparison circuit are provided.

  According to this, the minimum drain voltage that can be taken by the first MOS transistor in the target circuit is reproduced in the second MOS transistor in the replica circuit, and these drain voltages are respectively obtained by the first and second voltage buffers. It is reproduced as the drain voltage of each MOS transistor in the first and second MOS transistor groups, and the comparison circuit compares the first and second currents flowing in the first and second MOS transistor groups, respectively. . Then, from the result of the magnitude comparison of the first and second currents, it can be determined whether or not the first MOS transistor in the target circuit is operating in the saturation region, and the target circuit is based on the comparison result. By adjusting the operation state of the replica circuit, the first MOS transistor in the target circuit can be automatically adjusted so as to operate in the saturation region.

  Preferably, the comparison circuit outputs a digital signal indicating the presence or absence of a current difference between the first and second currents as a comparison result. The adjustment circuit adjusts the operation state of the target circuit and the replica circuit so that the second current approaches the first current when the digital signal indicates that the current difference is present. And

  According to this, the operating range of the first MOS transistor in the target circuit can be moved stepwise into the saturation region.

  More preferably, the adjustment circuit sets the operation state of the target circuit and the replica circuit to the limit of the adjustable range in one adjustment.

  According to this, the operation range of the first MOS transistor in the target circuit can be moved into the saturation region earlier.

  More preferably, the adjustment circuit is configured such that when the digital signal indicates that there is no current difference, the adjustment circuit is configured so that the operating point of the second MOS transistor approaches the pinch-off point. The operating state shall be adjusted.

  According to this, the power consumption can be reduced while the first MOS transistor in the target circuit operates in the saturation region.

  Furthermore, it is preferable that the adjustment width when the second current is brought close to the first current is larger than the adjustment width when the operating point of the second MOS transistor is brought close to the pinch-off point.

  According to this, when the operation range is outside the saturation region, the first MOS transistor in the target circuit is moved into the saturation region relatively quickly, and when the operation range is within the saturation region, the saturation region operability is achieved. The power consumption can be gradually reduced while maintaining the above.

  Preferably, the comparison circuit outputs an analog signal having a magnitude corresponding to the current difference between the first and second currents as a comparison result. The adjustment circuit adjusts the operation states of the target circuit and the replica circuit so that the operation point of the second MOS transistor approaches the pinch-off point according to the analog signal.

  According to this, the operation range of the first MOS transistor in the target circuit can be moved to the optimum operation range in which the power consumption is minimized within the saturation region.

  Specifically, the adjustment circuit adjusts the power supply voltage applied to the target circuit and the replica circuit.

  Specifically, the adjustment circuit adjusts the bias applied to the target circuit and the replica circuit.

  Specifically, the adjustment circuit adjusts the substrate voltage applied to each MOS transistor in the first and second MOS transistors and the first and second MOS transistor groups.

  As described above, according to the present invention, it is possible to detect the saturation region operability of the MOS transistor in the target circuit while suppressing an increase in circuit scale and power consumption, and further, in order to operate the MOS transistor in the saturation region. The operating state of the circuit can be automatically adjusted. For this reason, the yield of LSI can be improved.

  Further, since it is possible to reduce the influence of circuit characteristics due to process variations and temperature fluctuations on the LSI, it is not necessary to secure an extra operation margin at the time of design, and the operation margin can be reduced. The present invention is particularly effective for a low voltage circuit whose operating range is limited.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows the configuration of the CMOS circuit characteristic automatic adjustment device according to the first embodiment. This apparatus includes a replica circuit 10, a replica signal generation circuit 20, voltage buffers 30a and 30b, a comparison circuit 40, an adjustment circuit 50, and nMOS transistors 101c and 101d. An nMOS transistor 101a as a constant current source in the target circuit 100 is provided. The operation state of the target circuit 100 is adjusted so as to operate in the saturation region. The target circuit 100 is an arbitrary CMOS circuit. Hereinafter, for convenience, the target circuit 100 will be described as a differential amplifier circuit.

  The target circuit 100 includes an nMOS transistor 101a, pMOS transistors 102a and 103a, and nMOS transistors 104a and 105a. A bias Vbn is applied to the gate of the nMOS transistor 101a, and a reference voltage is applied to the source. A bias Vbp is applied to the gates of the pMOS transistors 102a and 103a, and a reference voltage is applied to the sources. Voltages VI1 and VI2 as differential input signals VI are applied to the gates of the nMOS transistors 104a and 105a, respectively.

  The replica circuit 10 is a replica of the target circuit 100, and is configured as a differential amplifier circuit in the present embodiment. In the replica circuit 10, nMOS transistors 101b, 104b and 105b and pMOS transistors 102b and 103b correspond to the nMOS transistors 101a, 104a and 105a and the pMOS transistors 102a and 103a in the target circuit 100, respectively. The nMOS transistor and the pMOS transistor in the replica circuit 10 have the same characteristics as the nMOS transistor and the pMOS transistor in the target circuit 100, respectively. Similar to the target circuit 100, a bias Vbn is applied to the gate of the nMOS transistor 101a, and a reference voltage is applied to the source. Further, a bias Vbp is applied to the gates of the pMOS transistors 102b and 103b, and a reference voltage is applied to the sources. However, unlike the target circuit 100, the replica signal Vrep is input to the gates of the nMOS transistors 104b and 105b.

  The replica signal generation circuit 20 generates a replica signal Vrep. The replica signal Vrep is a signal that minimizes the drain voltage Vd1 of the nMOS transistor 101a when input to the target circuit 100. In the case of the differential amplifier circuit, the drain voltage Vd1 is minimized when the differential inputs are in-phase and at the amplitude center level. Therefore, in the present embodiment, the replica signal generation circuit 10 outputs a voltage at the amplitude center level of the differential input signal VI as the replica signal Vrep. Specifically, the voltage at the amplitude center level of the differential input signal VI can be obtained by resistance-dividing the voltages VI1 and VI2.

  The voltage buffer 30a includes an operational amplifier 31a and an nMOS transistor 32a. The operational amplifier 31a receives the drain voltage Vd1 of the nMOS transistor 101a and the drain voltage Vd3 of the nMOS transistor 101c in the target circuit 100. The nMOS transistor 32a is connected to the nMOS transistor 101c, and the output voltage of the operational amplifier 31a is applied to the gate. That is, the voltage buffer 30a operates so that the drain voltages Vd1 and Vd3 are equal. Since the impedance at the inverting and non-inverting input terminals of the operational amplifier 31a is sufficiently high, the influence of the operational amplifier 31a on the target circuit 100 and the nMOS transistor 101c can be ignored.

  The voltage buffer 30b includes an operational amplifier 31b and an nMOS transistor 32b. The operational amplifier 31b receives the drain voltage Vd2 of the nMOS transistor 101b and the drain voltage Vd4 of the nMOS transistor 101d in the replica circuit 10. The nMOS transistor 32b is connected to the nMOS transistor 101d, and the output voltage of the operational amplifier 31b is applied to the gate. That is, the voltage buffer 30b operates so that the drain voltages Vd2 and Vd4 are equal. Since the impedance of the inverting and non-inverting input terminals of the operational amplifier 31b is sufficiently high, the operational effects of the operational amplifier 31b on the replica circuit 10 and the nMOS transistor 101d can be ignored.

  The comparison circuit 40 compares the drain currents Id3 and Id4 flowing through the nMOS transistors 101c and 101d, respectively. Here, each of the nMOS transistors 101c and 101d has the same characteristics as the nMOS transistor 101a in the target circuit 100, and a bias Vbn is applied to the gate and a reference voltage is applied to the source. Therefore, the drain current Id1 flowing through the nMOS transistor 101a is mirrored and the drain current Id3 flows through the nMOS transistor 101c. Similarly, the current Id2 flowing through the nMOS transistor 101b is mirrored and the drain current Id4 flows through the nMOS transistor 101d. That is, the comparison circuit 40 substantially compares the drain currents Id1 and Id2.

  Specifically, the comparison circuit 40 includes diode-connected pMOS transistors 41 a and 41 b and a comparator 42. The pMOS transistor 41a operates as an active load or an IV conversion circuit that converts the drain current Id3 flowing through the nMOS transistor 101c into the voltage V1. Similarly, the pMOS transistor 41b operates as an active load or an IV conversion circuit that converts the drain current Id4 flowing through the nMOS transistor 101d into the voltage V2. The comparator 42 compares the voltages V1 and V2 converted by the pMOS transistors 41a and 41b, respectively. That is, the comparison circuit 40 indirectly compares the drain currents Id3 and Id4 after converting these currents into a voltage. Of course, the drain currents Id3 and Id4 may be directly compared in magnitude.

  The output of the comparison circuit 40 may be either a digital signal or an analog signal. In the case of a digital signal, it can be simply expressed whether or not there is a current difference between the drain currents Id3 and Id4. On the other hand, in the case of an analog signal, the magnitude of the current difference can be expressed.

  The adjustment circuit 50 adjusts the operation states of the target circuit 100 and the replica circuit 10 based on the comparison result of the comparison circuit 40. Specifically, when the comparison result of the comparison circuit 40 indicates that there is a current difference between the drain currents Id3 and Id4, the adjustment circuit 50 adjusts the target circuit 100 and the target circuit 100 so that the drain current Id2 approaches the drain current Id1. The operation state of the replica circuit 10 is adjusted. On the other hand, when the comparison result of the comparison circuit 40 indicates that there is no current difference between the drain currents Id3 and Id4, the characteristics of the target circuit 100 and the replica circuit 10 are set so that the operating point of the nMOS transistor 101b approaches the pinch-off point. adjust.

  The principle of adjustment by the adjustment circuit 50 will be described with reference to FIG. The nMOS transistor 101a used as a constant current source needs to operate in a saturation region. Furthermore, the drain voltage is preferably smaller from the viewpoint of low power operation. Thus, the range A is the optimum operating range of the nMOS transistor 101a. However, in practice, the nMOS transistor 101a may operate in a range B including a linear region due to process variations, temperature fluctuations, and the like. In this case, there is a current difference between the lower limit of the range B, that is, the drain current at the operating point of the nMOS transistor 101b and the drain current at the operating point of the nMOS transistor 101a. And nMOS transistor 101d. When the adjustment circuit 50 detects that there is a current difference from the comparison result of the comparison circuit 40, the operation state of the target circuit 100 and the replica circuit 10 is set so that the drain current of the nMOS transistor 101b approaches the drain current of the nMOS transistor 101a. Adjust. As a result, the operating range of the nMOS transistor 101a moves in the direction α so that the entire operating range is included in the linear region.

  If the adjustment amount by the adjustment circuit 50 is too large, the operation range of the nMOS transistor 101a may reach the range C past the range A which is the optimum operation range. In this case, since the nMOS transistor 101b operates in the saturation region, there is no current difference between the drain current at the operating point of the nMOS transistor 101b, which is the lower limit point of the range C, and the drain current at the operating point of the nMOS transistor 101a. It has not occurred. Therefore, no current difference is generated between the nMOS transistor 101c and the nMOS transistor 101d. When the adjustment circuit 50 detects from the comparison result of the comparison circuit 40 that there is no current difference, the adjustment circuit 50 adjusts the operation state of the target circuit 100 and the replica circuit 10 so that the operation point of the nMOS transistor 101b approaches the pinch-off point. As a result, the operation range of the nMOS transistor 101a moves in the direction β returning to the range A which is the optimum operation range.

  For example, the adjustment circuit 50 may be a variable power supply capable of adjusting the power supply voltage and the bias Vbp applied to the target circuit 100 and the replica circuit 10. By adjusting the power supply voltage or the bias Vbp, the drain voltages Vd1 and Vd2 and the drain voltages Vd3 and Vd4 change in conjunction with each other, and the operating point of the nMOS transistor 101b can be moved arbitrarily.

The adjustment circuit 50 may be a variable power source that can adjust the substrate voltage applied to the nMOS transistors 101a to 101d. The threshold voltage of the nMOS transistors 101a to 101d may be shifted to a higher one due to process variations, temperature conditions, and the like, and the operation region may shift to a linear region, but the thresholds of the nMOS transistors 101a to 101d may be adjusted by adjusting the substrate voltage. The voltage changes and the pinch-off point can be moved arbitrarily. Therefore, the operating point of the nMOS transistor 101b can be brought close to the pinch-off point without changing the drain voltage. The following equation holds between the substrate voltage Vbs and the threshold voltage Vt.
Vt = Vt0 + γ (√ (Vbs + 2φF) −√ (2φF))
However, Vt0 is a threshold voltage when the substrate-source voltage is zero, γ is a coefficient representing the effect of the substrate bias, and φF is a Fermi potential. Thus, the threshold voltage affects as a function of the square root of the substrate voltage.

  When the power supply voltage is adjusted, the entire CMSO circuit is affected. On the other hand, when the substrate voltage is adjusted, the range of influence is local, for example, only on the p substrate. Accordingly, it is advantageous to adjust the substrate voltage in consideration of the influence on others. The substrate voltage has a setting limit. For example, the substrate voltage of a p-substrate has an upper limit value on the reliability of the nMOS transistor. When the substrate voltage exceeds the set limit, the PN junction between the substrate and the source and between the substrate and the drain becomes a forward direction, current flows to the substrate, and the transistor does not function. If this characteristic is used, even if the substrate voltage is set to the set limit value, if a current difference appears between the drain current Id1 and the drain current Id2, the CMOS circuit cannot compensate within the rated voltage. It can be determined that the product is defective.

  A processing sequence of the CMOS circuit characteristic automatic adjustment device according to the present embodiment will be described with reference to the flowchart of FIG. First, a comparison is made between the drain current Id3 of the nMOS transistor 101c and the drain current Id4 of the nMOS transistor 101d (step S10). If there is a difference between the drain currents Id3 and Id4 (YES in step S11), (1) increase the power supply voltage of the target circuit 100 and the replica circuit 10, (2) decrease the bias Vbp, or (3 ) One of the processes of increasing the substrate voltage of the nMOS transistors 101a to 101d is performed (step S12). On the other hand, if there is no current difference between the drain currents Id3 and Id4 (NO in step S11), the process opposite to that in step S12, that is, (1) reduce the power supply voltage of the target circuit 100 and the replica circuit 10 or (2 The process of either increasing the bias Vbp or (3) decreasing the substrate voltage of the nMOS transistors 101a to 101d is performed (step S13). Then, following step S12 or S13, it is determined whether or not the adjustment process is to be ended, and when continuing, the process returns to step S10 (NO in step S14). With this processing sequence, the operating range of the nMOS transistor 101a can be brought close to the optimum operating range (see FIG. 2).

  The above processing sequence may be executed at a predetermined time (for example, 1 ms) at the time of circuit initialization such as when the CMOS circuit is activated or within a range that does not affect the circuit operation. By executing the above-described processing sequence at the time of circuit initialization, it is possible to cope with deviations in sample-dependent operating points such as process variations. Further, by executing the above processing sequence at regular intervals, it is possible to cope with a shift in operating point depending on the operating state due to temperature fluctuation or the like.

  The adjustment of various voltages in steps S12 and S13 may be continuous or discrete. That is, when an analog signal having a magnitude corresponding to the current difference between the drain currents Id3 and Id4 is output from the comparison circuit 40, various voltages may be continuously adjusted according to the analog signal. On the other hand, when a digital signal indicating the presence or absence of the current difference between the drain currents Id3 and Id4 is output from the comparison circuit 40, various voltages may be discretely adjusted with a predetermined width, for example, a step of 100 mV.

  Furthermore, the adjustment width in step S12 may be set larger than the adjustment width in step S13. For example, in step S12, the adjustment is performed at a step of 100 mV, and in step S13, the adjustment is performed at a step of 10 mV, which is 1/10 of that. This is because, when the nMOS transistor 101a is not operating in the saturation region, it is necessary to operate in the saturation region earlier, whereas when the nMOS transistor 101a is operating in the saturation region, it is abrupt. This is because if the adjustment is performed, the operating range of the nMOS transistor 101a may protrude from the saturation region again.

  Step S13 may be omitted in particular. The intended purpose of operating the nMOS transistor 101a in the saturation region can be achieved only by the processing in step S12. In step S12, the operation range of the nMOS transistor 101a can be moved to the saturation region most quickly by setting various voltages to the limit of the adjustable range in one adjustment.

  As described above, according to this embodiment, the CMOS circuit characteristics can be automatically adjusted so that the MOS transistor as the constant current source in the target circuit operates in the saturation region without particularly increasing the circuit scale and power consumption.

(Second Embodiment)
FIG. 4 shows the configuration of a CMOS circuit characteristic automatic adjustment device according to the second embodiment. This apparatus includes a replica circuit 10, a replica signal generation circuit 20, voltage buffers 30a ′ and 30b ′, a comparison circuit 40 ′, an adjustment circuit 50, and MOS transistor groups 60a and 60b, and serves as a constant current source in the target circuit 100. The operation state of the target circuit 100 is adjusted so that the nMOS transistor 101a operates in the saturation region. Note that the replica circuit 10, the replica signal generation circuit 20, and the adjustment circuit 50 are the same as the components of the apparatus according to the first embodiment, and thus description thereof will be omitted. Hereinafter, differences from the first embodiment will be described. Only explained.

  The MOS transistor group 60a includes four nMOS transistors 101c1, 101c2, 101c3, and 101c4. The MOS transistor group 60b is composed of four nMOS transistors 101d1, 101d2, 101d3, and 101d4. The nMOS transistors 101c1 to 101c4 and 101d1 to 101d4 all have the same characteristics as the nMOS transistor 101a in the target circuit 100, and a bias Vbn is applied to the gate and a reference voltage is applied to the source. Note that the number of nMOS transistors constituting the MOS transistor groups 60a and 60b is arbitrary, and is four here for convenience of explanation.

  The voltage buffer 30a 'is a voltage follower circuit including an operational amplifier 31a. The drain voltage Vd1 of the nMOS transistor 101a in the target circuit 100 is input to the operational amplifier 31a. In the voltage buffer 30a ', since the output terminal of the operational amplifier 31a is directly connected to the MOS transistor group 60a, the accuracy is slightly inferior to that of the voltage buffer 30a shown in FIG. The drain voltage Vd3 of the nMOS transistors 101c1 to 101c4 in the transistor group 60a can be made equal to the drain voltage Vd1.

  The voltage buffer 30b 'is a voltage follower circuit including an operational amplifier 31b. The drain voltage Vd2 of the nMOS transistor 101b in the replica circuit 10 is input to the operational amplifier 31b. Since the output terminal of the operational amplifier 31b is directly connected to the MOS transistor group 60b, the voltage buffer 30b ′ has a slightly lower accuracy than the voltage buffer 30b shown in FIG. The drain voltage Vd4 of the nMOS transistors 101d1 to 101d4 in the transistor group 60b can be made equal to the drain voltage Vd2.

  In each of the nMOS transistors 101c1 to 101c4, the drain current Id1 flowing in the nMOS transistor 101a is mirrored to cause a drain current Id3 to flow, and in the MOS transistor group 60a, a current (4 * Id3) four times larger than that. Similarly, in each of the nMOS transistors 101d1 to 101d4, the current Id2 flowing in the nMOS transistor 101b is mirrored to cause the drain current Id4 to flow, and in the MOS transistor group 60b, a current (4 * Id4) that is four times the current flows. Therefore, currents corresponding to four times the drain currents Id1 and Id2 flow through the MOS transistor groups 60a and 60b, respectively.

  The comparison circuit 40 'includes a comparator 42 and resistors 43a and 43b. The resistor 43a operates as an active load or an IV conversion circuit that converts the current (4 * Id3) flowing through the MOS transistor group 60a into the voltage V1 '. Similarly, the resistor 43b operates as an active load or an IV conversion circuit that converts a current (4 * Id4) flowing through the MOS transistor group 60b into a voltage V2 '. The comparator 42 compares the voltages V1 'and V2' converted by the resistors 43a and 43b, respectively. That is, the comparison circuit 40 'performs a magnitude comparison between a current substantially equivalent to four times the drain current Id1 and a current equivalent to four times the drain current Id2.

  As described above, according to the present embodiment, the current difference between the drain current of the MOS transistor as the constant current source in the target circuit and the drain current of the equivalent MOS transistor in the replica circuit is detected with four times the accuracy of the first embodiment. be able to. Therefore, even when the current flowing through each of the MOS transistors in the target circuit and the replica circuit is very small, the difference between these currents can be detected.

  Although the above description is for ensuring the saturation region operability of the nMOS transistor in the target circuit, the present invention can also be applied to ensure the saturation region operability of the pMOS transistor in the target circuit. . In that case, for example, it goes without saying that the adjustments in steps S12 and S13 in FIG. 2 are reversed.

  Further, the adjustment circuit 50 may be omitted in the first and second embodiments as long as the saturation region operability of the MOS transistor in the target circuit can be detected. This functions as a MOS transistor characteristic detection device.

  The device according to the present invention can detect the saturation region operability of the MOS transistor in the target circuit while suppressing an increase in circuit scale and power consumption, and further, the CMOS circuit so that the MOS transistor operates in the saturation region. Therefore, it is particularly useful for a low voltage operation CMOS circuit having a MOS transistor as a constant current source.

It is a block diagram of the CMOS circuit characteristic automatic adjustment apparatus which concerns on 1st Embodiment. It is a figure for demonstrating the principle of characteristic adjustment. It is a flowchart of characteristic adjustment. It is a block diagram of the CMOS circuit characteristic automatic adjustment apparatus which concerns on 2nd Embodiment.

Explanation of symbols

10 replica circuit 20 replica signal generation circuit 30a, 30a ′ voltage buffer (first voltage buffer)
30b, 30b ′ voltage buffer (second voltage buffer)
31a, 31b operational amplifiers 32a, 32b nMOS transistors (MOS transistors)
40, 40 'comparison circuit 41a pMOS transistor (first IV conversion circuit, MOS transistor)
41b pMOS transistor (second IV conversion circuit, MOS transistor)
42 Comparator 43a Resistance (first IV conversion circuit, resistance element)
43b Resistance (second IV conversion circuit, resistance element)
50 adjustment circuit 60a MOS transistor group (first MOS transistor group)
60b MOS transistor group (second MOS transistor group)
101a nMOS transistor (first MOS transistor)
101b nMOS transistor (second MOS transistor)
101c, 101c1 to 101c4 nMOS transistors (MOS transistors in the first MOS transistor group)
101d, 101d1 to 101d4 nMOS transistors (MOS transistors in the second MOS transistor group)

Claims (14)

A device for detecting whether or not the first MOS transistor in the target circuit operates in a saturation region,
A replica signal generation circuit that generates a replica signal that minimizes the drain voltage of the first MOS transistor if input to the target circuit;
A replica of the target circuit, having a second MOS transistor corresponding to the first MOS transistor, to which the replica signal is input;
A first voltage buffer to which a drain voltage of the first MOS transistor is input;
A second voltage buffer to which the drain voltage of the second MOS transistor is input;
A first MOS transistor group having at least one MOS transistor having characteristics and a gate and source applied voltage that are the same as those of the first MOS transistor and having a drain applied with the output voltage of the first voltage buffer;
A second MOS transistor group having at least one MOS transistor having characteristics and an applied voltage of a gate and a source that are the same as those of the first MOS transistor, and having an output voltage of the second voltage buffer applied to a drain;
A MOS transistor characteristic detecting device comprising: a comparison circuit for comparing the magnitude of a first current flowing through the first MOS transistor group and a second current flowing through the second MOS transistor group. In the MOS transistor characteristic detection device according to claim 1,
The comparison circuit is
A first IV conversion circuit for converting the first current into a first voltage;
A second IV conversion circuit for converting the second current into a second voltage;
And a comparator for comparing the magnitudes of the first and second voltages. In the MOS transistor characteristic detection device according to claim 2,
Both the first and second IV conversion circuits are diode-connected MOS transistors. In the MOS transistor characteristic detection device according to claim 2,
Both of the first and second IV conversion circuits are resistance elements, and the MOS transistor characteristic detection device. In the MOS transistor characteristic detection device according to claim 1,
The first voltage buffer includes:
An operational amplifier to which the drain voltage of the first MOS transistor and the drain voltage of the MOS transistor in the first MOS transistor group are input;
A MOS transistor connected to the first MOS transistor group and having a gate to which an output voltage of the operational amplifier is applied;
The second voltage buffer is
An operational amplifier to which the drain voltage of the second MOS transistor and the drain voltage of the MOS transistor in the second MOS transistor group are input;
And a MOS transistor connected to the second MOS transistor group and having a gate to which the output voltage of the operational amplifier is applied. An apparatus for automatically adjusting the operation state of the CMOS circuit so that the first MOS transistor in the target circuit in the CMOS circuit operates in a saturation region,
A replica signal generation circuit that generates a replica signal that minimizes the drain voltage of the first MOS transistor if input to the target circuit;
A replica of the target circuit, having a second MOS transistor corresponding to the first MOS transistor, to which the replica signal is input;
A first voltage buffer to which a drain voltage of the first MOS transistor is input;
A second voltage buffer to which the drain voltage of the second MOS transistor is input;
A first MOS transistor group having at least one MOS transistor having characteristics and a gate and source applied voltage that are the same as those of the first MOS transistor and having a drain applied with the output voltage of the first voltage buffer;
A second MOS transistor group having at least one MOS transistor having characteristics and an applied voltage of a gate and a source that are the same as those of the first MOS transistor, and having an output voltage of the second voltage buffer applied to a drain;
A comparison circuit for comparing the magnitude of the first current flowing through the first MOS transistor group and the second current flowing through the second MOS transistor group;
An automatic adjustment circuit for CMOS circuit characteristics, comprising: an adjustment circuit for adjusting an operation state of the target circuit and the replica circuit based on a comparison result of the comparison circuit. In the CMOS circuit characteristic automatic adjustment device according to claim 6,
The comparison circuit outputs a digital signal indicating the presence or absence of a current difference between the first and second currents as the comparison result,
The adjustment circuit adjusts the operation state of the target circuit and the replica circuit so that the second current approaches the first current when the digital signal indicates that there is the current difference. CMOS circuit characteristic automatic adjustment device characterized by being a thing. In the CMOS circuit characteristic automatic adjustment device according to claim 7,
The CMOS circuit characteristic automatic adjustment device according to claim 1, wherein the adjustment circuit sets the operation state of the target circuit and the replica circuit to a limit of an adjustable range by one adjustment. In the CMOS circuit characteristic automatic adjustment device according to claim 7,
The adjustment circuit adjusts the operation state of the target circuit and the replica circuit so that the operation point of the second MOS transistor approaches the pinch-off point when the digital signal indicates that there is no current difference. A device for automatically adjusting CMOS circuit characteristics, characterized in that: In the CMOS circuit characteristic automatic adjustment device according to claim 9,
A CMOS circuit characteristic automatic adjustment characterized in that an adjustment width when the second current is brought close to the first current is larger than an adjustment width when the operating point of the second MOS transistor is brought close to the pinch-off point. apparatus. In the CMOS circuit characteristic automatic adjustment device according to claim 6,
The comparison circuit outputs an analog signal having a magnitude corresponding to a current difference between the first and second currents as the comparison result;
The adjustment circuit adjusts the operation state of the target circuit and the replica circuit so that the operation point of the second MOS transistor approaches a pinch-off point in accordance with the analog signal. Automatic characteristic adjustment device. In the CMOS circuit characteristic automatic adjustment device according to claim 6,
The CMOS circuit characteristic automatic adjustment device, wherein the adjustment circuit adjusts a power supply voltage applied to the target circuit and the replica circuit. In the CMOS circuit characteristic automatic adjustment device according to claim 6,
The CMOS circuit characteristic automatic adjustment device according to claim 1, wherein the adjustment circuit adjusts a bias applied to the target circuit and the replica circuit. In the CMOS circuit characteristic automatic adjustment device according to claim 6,
The adjustment circuit adjusts a substrate voltage applied to each of the first and second MOS transistors and each MOS transistor in the first and second MOS transistor groups. Adjustment device.

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