JP2002076280A - Circuit and method of automatically adjusting cmos circuit characteristics - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit and method of automatically adjusting CMOS circuit characteristics with which circuit characteristics in an LSI are controlled according to the calculated results. SOLUTION: An adjustment section is provided, which calculates the threshold value of a transistor when it is operated in a saturation region, from the binary gate voltage and the value of a binary source-to-drain current, which is caused to flow after gate voltage is applied. The threshold voltage is calculated, by digitizing the value of the voltage applied to a gate electrode and the outputted source-to-drain current, and according to the calculation result, control parameters for a circuit in the LSI are determined. Consequently, stable circuit characteristics which are independent of the change in the threshold voltage can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for automatically adjusting the characteristics of a CMOS circuit and a method therefor, and more particularly, to a circuit for calculating a threshold voltage of a transistor in an LSI, and the LSI in accordance with the calculated result. The present invention relates to a circuit for automatically adjusting the characteristics of a CMOS circuit for controlling the characteristics of a circuit therein and a method thereof.

[0002]

2. Description of the Related Art Conventionally, it has been known that fluctuations in the threshold voltage of a transistor in a CMOS circuit affect the characteristics of the CMOS circuit.

For example, a charge pump circuit used in a phase comparator of a PLL circuit converts a phase comparison result into a current value of a Pch transistor or an Nch transistor, controls an oscillator connected to a subsequent stage, and When the current capability ratios of the Pch transistors are equal,
Stable phase pull-in is possible.

That is, if the current capability ratio between the Pch transistor and the Nch transistor can be kept constant, a stable frequency pull-in can be guaranteed.

[0005] Not only the PLL circuit but also a circuit closer to the target characteristic can be provided if the characteristic fluctuation due to the threshold voltage fluctuation can be suppressed. In addition, a circuit with particularly severe required characteristics is required to have its fluctuation value within the target specification.

[0006]

However, the above-mentioned fluctuations in the circuit characteristics cannot be avoided due to fluctuations in the characteristics of the transistors, particularly, fluctuations in the threshold voltage of the transistors.

For example, when the current capability ratio of the Nch transistor and the Pch transistor of the charge pump circuit used in the phase comparator of the PLL circuit is not equal,
Stable phase pull-in cannot be performed.

Accordingly, an object of the present invention in view of the above problems is to provide a circuit for automatically adjusting CMOS circuit characteristics and a method therefor that solves these problems.

If the current capability ratio of the Pch transistor and the Nch transistor can be kept constant by the circuit of the present invention, a stable frequency pull-in can be guaranteed.

[0010]

An automatic adjustment circuit for CMOS circuit characteristics according to the present invention generates n (n is a positive integer) bit data, and performs D / A conversion on the n bit data. Receiving the A-converted data at the gate of the field effect transistor, generating a drain voltage of the field effect transistor, A / D converting the drain voltage,
The threshold value of the field effect transistor is calculated based on the converted data, the threshold value is decoded, and the circuit current is controlled by the decoded value.

Further, the automatic adjustment circuit for CMOS circuit characteristics according to the present invention is characterized in that n (n is a positive integer) bit data is D / A
A D / A converter for converting, an A / D converter for A / D converting analog data, an n-bit data generating circuit for generating a plurality of the n-bit data, and an output of the n-bit data generating circuit. A P-channel transistor and an N-channel transistor which convert the analog value into an analog value by a D / A converter and receive the analog value at its gate; a changeover switch for switching a drain voltage of the P-channel transistor or a drain voltage of the N-channel transistor;
a threshold voltage calculator for converting a drain voltage of a channel transistor or a drain voltage of the N channel transistor into a digital value by the A / D converter, calculating and storing the digital value, and an output of the threshold value calculator And a control circuit that receives a decoding result of the decoder circuit and controls a current value thereof.

Further, the adjustment section of the automatic adjustment circuit for CMOS circuit characteristics of the present invention may be configured to include the n-bit data generation circuit and a timing generation circuit for controlling the timing of the changeover switch.

Further, according to the method for adjusting a CMOS circuit characteristic automatic adjustment circuit of the present invention, a first step of setting an initial value of 0 to a counter value of an internal counter of the timing generation circuit; A second step of generating first data, a third step of D / A-converting the first data into first analog data, and a step of converting the first analog data to the Pch transistor. A fourth step in which the drain voltage of the Pch transistor is subjected to A / D conversion as a result of applying the first analog data to the gate electrode; S5 and a sixth step S6 in which the converted data is held in the threshold value calculator.

That is, the circuit of the present invention is a CMOS LS
I, a circuit for calculating the threshold voltage of the transistor is provided in the LSI, and the L level is set in accordance with the calculated result.
It is characterized by controlling circuit characteristics in the SI.

When the transistor operates in the saturation region,
The threshold voltage can be calculated from a binary gate voltage and a binary source-drain current flowing as a result of applying the gate voltage. The circuit of the present invention calculates the threshold voltage by digitizing the voltage value applied to the gate electrode and the output source-drain current, and changes the control parameters of the circuit in the LSI according to the calculation result. To decide. Thus, there is an effect that stable circuit characteristics independent of threshold voltage fluctuation can be obtained.

[0016]

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit for automatically adjusting the characteristics of a CMOS circuit according to the first embodiment of the present invention.

Referring to FIG. 1, an adjusting unit 10 of an automatic CMOS circuit characteristic adjusting circuit 100 according to a first embodiment of the present invention includes an n-bit data generating circuit 20 for generating four n-bit data, Pch transistor 1, Nch transistor 2, resistance elements (3, 4), signal line changeover switches (7, 8), and threshold calculator 22 for calculating thresholds of Pch transistor 1 and Nch transistor 2. And a decoder circuit 23.

Further, the CM according to the first embodiment of the present invention
The adjustment unit 10 of the automatic adjustment circuit 100 for OS circuit characteristics
Bit data generation circuit 20, signal line changeover switches (7, 8), and threshold calculator 2 for calculating threshold
And a timing generation circuit 21 for generating operation timings of the respective circuits.

The CM according to the first embodiment of the present invention
The OS circuit characteristic automatic adjustment circuit 100 includes an adjustment unit 10,
A well-known n-bit A / D converter 50, an n-bit D / A converter 40, a selector circuit 60 that receives a decoding result 61 of the decoder circuit 23, and control in which the current is controlled by a control parameter of the selector circuit 60. And the target circuit 30.

The output of the n-bit data generation circuit 20 is D
The signal is converted into an analog signal by the / A converter 40 and applied to the gate electrodes of the Pch transistor 1 and the Nch transistor 2.

A high potential power supply VDD is connected to the source electrode side of the Pch transistor 1, and a resistor 3 whose one end is grounded to a ground line is connected to the drain electrode side.

A ground line is connected to the source electrode side of the Nch transistor 2, and a resistor 4 having one end connected to the high power supply VDD is connected to the drain electrode.

The switches (7, 8) connect either the drain electrode of the Pch transistor 1 or the drain electrode of the Nch transistor 2 to the input of the n-bit A / D converter 50. The drain voltage converted into n bits by the A / D converter 50 is held in the threshold calculator 22.

The n-bit data generating circuit 20 generates a total of four n-bit data, two each for the gate applied voltage of the Pch transistor 1 and two for the gate applied voltage of the Nch transistor 2, and the threshold calculator 22 And a total of four n-bit data as the drain voltage of both transistors with respect to this applied voltage.

Based on the quaternary drain voltage and the quaternary gate applied voltage generated by the data generation circuit (20), the threshold calculator 22 calculates the Pch transistor (1) and the Nc
The threshold value of the h transistor (2) is calculated as n-bit data.

The calculation method and calculation formula are shown below.

The operation of the MOS device in the saturation region is as follows: Ids = (β / 2) × (Vgs−Vt) ² ... [Equation 1] 0 <| Vgs−Vt | <| Vds |. Can be represented by Where Ids is the drain-source current, Vgs is the gate-source voltage, Vt is the threshold voltage of the transistor, Vds is the drain-source voltage,
β is a gain coefficient of the MOS transistor.

[Equation 2] is a condition under which the transistor operates in the saturation region. Here, β depends on the parameters of the process and the transistor size, and is given by β = (με / tox) × (W / L) (Equation 3). μ is the effective mobility of electrons in the channel, ε
Is the dielectric constant of the gate insulator, tox is the thickness of the gate insulator, W is the channel width, and L is the channel length.

A transistor having a channel width W1, a channel length L1, and a threshold value Vt is provided with a transistor which operates in a saturation region.
Applying gate-source voltages Vgs1 and Vgs2 at the points;
The drain-source current at that time is represented by Ids1 and Ids1, respectively.
ds2 and the drain-source voltage are Vds1 and Vds, respectively.
Assuming that ds2, from [Equation 1] and [Equation 2], Ids1 = (β / 2) × (Vgs1−Vt) ² ... [Equation 4] 0 <| Vgs1−Vt | <| Vds1 | [Equation 5] Ids2 = (β / 2) × (Vgs2-Vt) ² ... [Equation 6] 0 <| Vgs2-Vt | <| Vds2 |. ] / [Equation 6] and solving for Vt, the following equation holds. Vt = (αVgs2−Vgs1) / (α−1) (8) where α = (Ids1 / Ids2) ^{1/2 In the} circuit of the present invention, Ids1 and Ids2 are determined by the resistance element R on the source electrode side. In the case of a Pch transistor, Ids1 = Vds1 / R, Ids2 = Vds2 / R... [Equation 9] In the case of an Nch transistor, Ids1 = (VDD−Vds1) / R, Ids2 = (VDD−Vds2) / R · .. [Equation 10] holds.

By substituting [Equation 9] and [Equation 10] into [Equation 8], the threshold value Vt of the Pch transistor is obtained.
p and the threshold value Vtn of the Nch transistor are as follows: Vtp = (γpVgs2-Vgs1) / (γp-1) [Equation 11] where γp = (Vds1 / Vds2) ^1/2 Vtn = (γnVgs2-Vgs1) ) / (Γn−1) (Expression 12) where γn = {(VDD−Vds1) / (VDD−Vds2)} ^1/2 .

As described above, the threshold value Vt can be calculated from the binary gate-source voltage and the binary drain-source voltage output as a result, and the threshold value calculator 22 provided in the circuit of the present invention uses [ The threshold voltage is calculated based on [Equation 11] and [Equation 12].

The calculated threshold voltage is input to the decoder circuit 23, and the variation range of the threshold with respect to the target value,
The control parameters of the circuits in the LSI are determined based on the direction of the change.

The timing generation circuit 21 generates the gate voltage generation timing, the threshold calculation timing, the control parameter update timing, and controls the switches 7 and 8.

Next, the CMO of the first embodiment of the present invention will be described.
The operation of the automatic adjustment circuit for the S circuit characteristics will be described.

FIG. 2 is a flowchart of the operation of the automatic adjustment circuit for CMOS circuit characteristics according to the first embodiment of the present invention.
FIG. 3 shows a timing chart.

First, the operation of the Pch transistor drain voltage measurement 1 will be described.

First, a counter value I of an internal counter (not shown) of the timing generation circuit 21 is initialized to an initial value = 0.
Is set (step S1).

At this time, the switch 7 is turned on and the switch 8 is turned on.
Is turned off, and Pc is input to the input of the A / D converter 50.
The drain electrode of the h transistor 1 is connected. Here, the n-bit data generation circuit 20 outputs the first data Dgs
p1 is generated (in step S2, the operation of the internal counter of FIG. 3 with the counter value I = 0).

Next, the n-bit data Dgsp1 is D / A
Converted (step S3), the Pch transistor 1 and N
A voltage is applied to the gate electrode of the channel transistor 2 (step S4).

Here, the n-bit data Dgsp1 is
/ A converted voltage Vgsp1 is the Pch transistor 1
Is set to operate in the saturation region.

Next, as a result of applying the voltage Vgsp1 to the gate electrode, the output drain voltage Vdsp1 of the Pch transistor 1 is A / D converted (step S5),
The converted data Ddsp1 is held in the threshold calculator 22 (step S6).

Next, the operation of the Pch transistor drain voltage measurement 2 will be described.

The counter value I of the internal counter of the timing generation circuit 21 is compared (step S7). Since the counter value I is 0, the process returns to step S2.

At this time, while the switches 7 and 8 remain in the previous state, the n-bit data generation circuit 20 generates the second data Dgsp2 (the operation of the internal counter = 1 in FIG. 3).

Here, the n-bit data Dgsp2 is
gsp1 and a voltage Vgsp after D / A conversion
2 is a value set so that the Pch transistor (1) operates in the saturation region.

As a result of the voltage Vgsp2 being applied to the gate electrode, the output drain voltage Vdsp2 of the Pch transistor 1 is A / D converted and the converted data Ddsp
2 is held in the threshold calculator 22.

Next, at the time of the Nch transistor drain voltage measurement 1, the counter value I of the internal counter of the timing generation circuit 21 is compared (step S7). Since the counter value I is 1, the process returns to step S2.

At this time, the switch 7 is turned off and the switch 8
Is turned on, and the drain electrode of the Nch transistor 2 is connected to the input of the A / D converter. Here, the n-bit data generation circuit 20 generates the third data Dgsn1 (the operation of the internal counter = 2 in FIG. 3).

The n-bit data Dgsn1 is D / A converted, and the Pch transistor 1 and the Nch transistor (2)
Is applied to the gate electrode. Here, n-bit data D
gsn1 indicates that the voltage Vgsn1 obtained by the D / A conversion is Nch
This is a value set so that the transistor 2 operates in the saturation region.

The drain voltage V of the Nch transistor 2 output as a result of applying the voltage Vgsn1 to the gate electrode
dsn1 is A / D converted, and the converted data Ddsn1
Is stored in the threshold calculator 22.

Next, the operation shifts to the time 2 of the Nch transistor drain voltage measurement. The counter value I of the internal counter of the timing generation circuit 21 is compared (step S7). Since the counter value I is 2, the process returns to step S2.

At this time, while the switches 7 and 8 remain in the previous state, the n-bit data generation circuit 20 generates the fourth data Dgsn2 (the operation of the internal counter = 3 in FIG. 3).

Here, the n-bit data Dgsn2 is
gsn1 and a voltage Vgsn after D / A conversion
2 is a value set to operate the Nch transistor 2 in the saturation region.

As a result of applying the voltage Vgsn2 to the gate electrode, the output drain voltage Vdsn2 of the Nch transistor 2 is A / D converted, and the converted data Ddsn
2 is held in the threshold calculator 22.

Next, the counter value I of the internal counter of the timing generation circuit 21 is compared (step S7). Since the counter value I is 3, the flow proceeds to step S8.

The threshold calculator 22 calculates the gate application data Dgsp1, generated by the n-bit data generation circuit 20,
Dgsp2, Dgsn1, Dgsn2, and the resulting drain voltage Ddsp held as n-bit data
1, Ddsp2, Ddsn1, Ddsn2, [Equation 1
1] and [Equation 12], the threshold value Vtp of the Pch transistor 1 and the threshold value Vtn of the Nch transistor 2 are calculated (step S8).

The gate-source voltages (Vgs1, Vgs2) in [Equation 11] and [Equation 12] are replaced by gate application data voltages Dgsp1, Dgsp2, Dgsn1, Dgsn2, and drain-source voltages (Vds1, Vd2).
s2) with the drain voltages Ddsp1, Ddsp2, Dds
n1 and Ddsn2, [Equation 13], [Equation 1]
4] holds.

However, the gate voltage D of the Pch transistor
gsp1 and Dgsp2 are Vgs1 and Vg of [Equation 11].
The polarity is reversed with respect to s2. Vtp = − (γpDgsp2-Dgsp1) / (γp-1) (Equation 13) where γp = (Ddsp1 / Ddsp2) ^1/2 Vtn = (γnDgsn2-Dgsn1) / (γn−1). Equation 14] Here, γn = {(VDD−Ddsn1) / (VDD−Ddsn2)} ^1/2 where VDD is a value obtained by converting the high-potential power supply value into n bits.

The decoding circuit 23 determines the control parameters of both transistors from the variation rate and the variation direction of the calculated threshold value with respect to the target threshold value. Each bit of the control parameter controls on / off of each transistor of the control circuit 30. 0 is off and 1 is on.

The current capability of the control target circuit 30 is adjusted by adjusting the number of transistors to be operated. By setting the control parameters so as to suppress the decrease and increase in the current capability of the transistor due to the threshold value variation, the current capability of the control target circuit 30 becomes substantially constant without depending on the threshold value variation.

In FIG. 1, each of the Pch transistor and the Nch transistor is provided with 4 bits of control parameters and 4 control transistors, but the numbers are arbitrary.

By changing the number of bits of the control parameter, the number of transistors of the control target circuit 30, and the size of the transistors (31 to 38) of the control target circuit 30, the adjustment range of the current capability or the resolution of the adjustable current can be increased. It is determined.

For example, the Nch of the control target circuit 30 in FIG.
Considering four transistors, when the channel length L is L1 (same size) and the channel width W is W1, 2 × W1, 4 × W1, and 8 × W1, respectively, the output current of the four transistors is the transistor having the channel width W1. Is defined as the minimum resolution source-drain current (Imin) that flows when
It can be adjusted in the range of １５15 × Imin.

The adjustment range and the minimum resolution are determined by the control target circuit 3
0 can be determined by the size and combination of transistors (31 to 38) and the number of transistors.

Next, the CMO of the second embodiment of the present invention will be described.
A circuit for automatically adjusting the S-circuit characteristics and its method will be described.

FIG. 4 shows a CM according to the second embodiment of the present invention.
FIG. 2 is a block diagram of an automatic adjustment circuit for OS circuit characteristics.

The result of the threshold value calculation by the automatic adjustment circuit for CMOS circuit characteristics according to the second embodiment of the present invention is affected by the characteristic fluctuation of the A / D converter and the D / A converter. Strictly speaking, the calculation of the threshold value includes the influence of the drain voltage, and the calculation result may be different from the expected result.

As a countermeasure, the adjusting unit 1 of the automatic CMOS circuit characteristic adjusting circuit 400 according to the second embodiment of the present invention.
1 designates a circuit A (1) for the adjustment unit 10 of the automatic adjustment circuit 100 for CMOS circuit characteristics according to the first embodiment of the present invention.
2), a circuit B (13) and a circuit C (14) are added, and LS
In order to reduce the current consumption of I, switches (5) and (6) are provided so as not to activate the adjusting unit 11, both switches (5, 6) are connected to the B side, and the high power supply potential of the Pch transistor 1 Is connected to the gate electrode of the ground line of the Nch transistor, and the other components are the same as those of the CMOS circuit automatic adjustment circuit 100 according to the first embodiment of the present invention. Have the same reference numerals.

The circuit A (12) adjusts the offset and gain errors of the D / A converter 40, and the circuit B (13) adjusts the offset and gain errors of the A / D converter 50. The circuit C (14) is a circuit for giving an offset to the output result of the threshold value calculator 22.

The circuit A (12), the circuit B (13),
The circuit C (14) can reduce the measurement error of the threshold value calculator 22 itself and provide a more accurate adjustment function.

The Pch transistor 1 shown in FIG.
The output of the D / A converter 40 is always connected to the gate electrode of the Nch transistor 2 and the gate electrode of the Nch transistor 2. A current is generated between them.

Therefore, in order to reduce the current consumption of the LSI, switches (5) and (6) are
Is not activated, both switches (5, 6) are connected to the B side. In the case of the Pch transistor 1, the high power supply potential is
In the case of the Nch transistor 2, the ground line is connected to the gate electrode.

As a result, both transistors (1, 2) are turned off, and the current between the drain and source is cut off.

Next, the CMO of the third embodiment of the present invention will be described.
A circuit for automatically adjusting the S-circuit characteristics and its method will be described.

FIG. 5 shows a CM according to the third embodiment of the present invention.
FIG. 2 is a block diagram of an automatic adjustment circuit for OS circuit characteristics.

Referring to FIG. 5, an automatic adjustment circuit 500 for CMOS circuit characteristics according to the third embodiment of the present invention is controlled by an automatic adjustment circuit 100 for CMOS circuit characteristics according to the first embodiment of the present invention. Instead of the circuit 30, a circuit to be controlled (501), a circuit to be controlled (502), a circuit to be controlled (503), and a circuit to be controlled (504) are provided. The same components as those of the automatic adjustment circuit 100 for CMOS circuit characteristics of the embodiment are denoted by the same reference numerals.

Each of the control target circuit (501), the control target circuit (502), the control target circuit (503) and the control target circuit (504) is a circuit having the same function and different capabilities.

As described above, the CMOS circuit characteristic automatic adjustment circuit 500 according to the third embodiment of the present invention selects an optimum circuit to be started from the calculated threshold value.

As the configuration of the circuit to be controlled becomes more complicated, it becomes difficult to keep the mutual relationship between a plurality of transistors constant. However, as shown in the example of FIG. As a result, stable circuit characteristics can be assured with respect to fluctuations in the threshold value.

[0081]

As described above, since the circuit characteristics are kept constant with respect to the fluctuation of the threshold value of the transistor, a more accurate circuit can be provided.

By measuring the threshold value and setting parameters at certain intervals during the LSI operation, circuit characteristics independent of the threshold value change due to a temperature change can be obtained.

Since the current capacity can always be set to the optimum value, it is possible to reduce the power consumption of the circuit without flowing an unnecessary current.

[Brief description of the drawings]

FIG. 1 is a block diagram of a circuit for automatically adjusting CMOS circuit characteristics according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of adjusting a CMOS circuit characteristic automatic adjustment circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the automatic adjustment circuit for CMOS circuit characteristics shown in FIG. 1;

FIG. 4 is a block diagram of a circuit for automatically adjusting CMOS circuit characteristics according to a second embodiment of the present invention;

FIG. 5 is a block diagram of a circuit for automatically adjusting CMOS circuit characteristics according to a third embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 Pch transistor 2 Nch transistor 3, 4 Resistance 5, 6, 7, 8 Switch 10, 11 Adjustment unit 20 n-bit data generation circuit 21 Timing generation circuit 22 Threshold calculator 23 Decoder circuit 30, 501, 502, 503 504 Control target circuit 31 to 38 MOS transistor 40 D / A converter 50 A / D converter 60 Control parameter selector circuit 61, 62 Decoding result 100, 400, 500 Automatic adjustment circuit for CMOS circuit characteristics 201 Control parameter S1 to S8 Step

Claims (9)

[Claims] An n-bit (n is a positive integer) bit data is generated, and the n-bit data is D / A converted.
The converted data is received at the gate of the field effect transistor, a drain voltage of the field effect transistor is generated, the drain voltage is A / D converted, and a threshold of the field effect transistor is determined based on the A / D converted data. Calculating a value, decoding the threshold value, and controlling the circuit current with the decoded value.
Automatic adjustment circuit for circuit characteristics. 2. An n-bit (n is a positive integer) bit data is
A D / A converter for performing A / A conversion, an A / D conversion for performing A / D conversion on analog data, an n-bit data generation circuit for generating a plurality of the n-bit data, and an output of the n-bit data generation circuit Is converted to an analog value by the D / A converter, and a Pch transistor and an Nch transistor receiving the analog value at the gate thereof; a changeover switch for switching a drain voltage of the Pch transistor or a drain voltage of the Nch transistor; A threshold voltage calculator for converting the drain voltage of the transistor or the drain voltage of the Nch transistor into a digital value by the A / D converter, calculating and storing the digital value, and an output of the threshold value calculator. An adjusting unit comprising a decoder circuit for decoding; Receiving, characterized in that it comprises a control target circuit to control the current value C
Automatic adjustment circuit for MOS circuit characteristics. 3. The CMOS according to claim 2, wherein the adjustment unit includes a timing generation circuit that controls timing of the n-bit data generation circuit and the changeover switch.
Automatic adjustment circuit for circuit characteristics. 4. The CMOS circuit characteristic according to claim 2, wherein the control target circuit includes a plurality of field effect transistors having the same characteristic, and receives the output of the decoder circuit at a gate of the field effect transistor having the same characteristic. Automatic adjustment circuit. 5. The CMOS circuit characteristic according to claim 2, wherein the control target circuit includes a plurality of weighted field effect transistors, and a gate of the weighted field effect transistor receives an output of the decoder circuit. Automatic adjustment circuit. 5. The automatic circuit for adjusting CMOS circuit characteristics according to claim 3 or 4. 6. The circuit for automatically adjusting CMOS circuit characteristics according to claim 2, further comprising a circuit for adjusting an offset and a gain error of said D / A converter. 7. A circuit for adjusting an offset and a gain error of the A / D converter.
7. An automatic adjustment circuit for CMOS circuit characteristics according to 5 or 6. 8. A circuit for providing an offset to an output result of the threshold value calculator.
8. A circuit and method for automatically adjusting CMOS circuit characteristics according to 6 or 7. 9. A first step of setting an initial value of a counter value of an internal counter of the timing generation circuit to 0, a second step of generating the first data by the n-bit data generation circuit, A third step in which the first data is D / A converted into first analog data; and a fourth step in which the first analog data is applied to gate electrodes of the Pch transistor and the Nch transistor.
And a fifth step S5 in which the output of the drain voltage of the Pch transistor is A / D converted as a result of the first analog data being applied to the gate electrode. 9. The automatic adjustment method for an automatic adjustment circuit for CMOS circuit characteristics according to claim 2, further comprising a sixth step S6 held in a threshold value calculator.