JP2007258230A - Semiconductor substrate and semiconductor device - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 8
- 238000003475 lamination Methods 0.000 claims description 7
- 238000002441 X-ray diffraction Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 229910002601 GaN Inorganic materials 0.000 description 27
- 150000004767 nitrides Chemical class 0.000 description 11
- 239000000463 material Substances 0.000 description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- FFBGYFUYJVKRNV-UHFFFAOYSA-N boranylidynephosphane Chemical compound P#B FFBGYFUYJVKRNV-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
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Abstract
Description
本発明は、シリコン基材上にIII族窒化物層を形成した半導体基板及びこれを用いた半導体装置に関する。特に本発明は、Si基材上に成膜したIII族窒化物の結晶性が向上した半導体基板及びこれを用いた半導体装置に関する。 The present invention relates to a semiconductor substrate having a group III nitride layer formed on a silicon substrate and a semiconductor device using the same. In particular, the present invention relates to a semiconductor substrate in which the crystallinity of a group III nitride formed on a Si substrate is improved and a semiconductor device using the same.
III族窒化物系の半導体、例えば窒化ガリウム系の半導体は、バンドギャップがシリコン及びGaAsと比べて広い。このため、III族窒化物層を半導体装置の基板として用いると、優れた特性の半導体装置を形成することができる。 Group III nitride semiconductors, such as gallium nitride semiconductors, have a wider band gap than silicon and GaAs. For this reason, when a group III nitride layer is used as a substrate of a semiconductor device, a semiconductor device having excellent characteristics can be formed.
従来のIII族窒化物基板は、サファイア基材上に、緩衝膜を介してIII族窒化物層を形成した構造を有している。しかし、サファイア基材は絶縁物であるため、電極構造が複雑になる。またサファイア基材は生産性が低く、価格が高く、かつ放熱性がよくない。そこで、生産性が高く、低価格であり、かつ放熱性が良いSi(シリコン)を基材としてIII族窒化物層を形成する技術が望まれている。 A conventional group III nitride substrate has a structure in which a group III nitride layer is formed on a sapphire substrate via a buffer film. However, since the sapphire substrate is an insulator, the electrode structure is complicated. Moreover, the sapphire substrate has low productivity, high price, and poor heat dissipation. Therefore, a technique for forming a group III nitride layer using Si (silicon) as a base material having high productivity, low cost and good heat dissipation is desired.
しかし、Si結晶とIII族窒化物層の間には大きな格子不整合(例えばGaNの場合は約14%)があり、かつ熱膨張率にも差がある。このため、Si基材上に直接良質のIII族窒化物層を形成することは難しい。これを解決する技術の一つとして、Si基材とGaN層の間に、AlN層から始まる複数のAlN/GaNの多層緩衝層を挿入する技術がある。これにより、Si基材に比較的厚いGaN層を形成することができる。しかし本技術によっても、GaN層を必要な厚さにすると、GaN層にクラックが発生してしまう。 However, there is a large lattice mismatch (for example, about 14% in the case of GaN) between the Si crystal and the group III nitride layer, and the coefficient of thermal expansion is also different. For this reason, it is difficult to form a high-quality group III nitride layer directly on the Si substrate. One technique for solving this is a technique in which a plurality of AlN / GaN multilayer buffer layers starting from an AlN layer are inserted between a Si substrate and a GaN layer. Thereby, a relatively thick GaN layer can be formed on the Si substrate. However, even with this technique, if the GaN layer has a required thickness, cracks occur in the GaN layer.
これを解決する技術の一つとして、特許文献1に記載の技術がある。この技術はSi基材上にBP(リン化ボロン)をバッファー層として形成し、その上にAlN/GaNからなる超格子バッファー結晶層を10層形成し、その上にGaN層を形成する技術である。
しかし特許文献1に記載の技術では、Si基材とBP層の界面に応力が生じ、その結果、GaN基板に反りが生じる。GaN基板に反りが生じるとその応力を緩和するためにGaN層に欠陥が導入され、基板の品質が低下してしまう(例えば特許文献1の第10段落)。これを解決する手法として、特許文献1の第11,12段落には、半導体素子の動作層として必要な部分にのみGaN層を成長させる技術が開示されている。しかしこのような手法をとると工程数が増加する。 However, in the technique described in Patent Document 1, stress is generated at the interface between the Si base and the BP layer, and as a result, the GaN substrate is warped. When the GaN substrate warps, defects are introduced into the GaN layer in order to relieve the stress, and the quality of the substrate deteriorates (for example, the 10th paragraph of Patent Document 1). As a technique for solving this, the 11th and 12th paragraphs of Patent Document 1 disclose a technique for growing a GaN layer only in a portion necessary as an operation layer of a semiconductor element. However, the number of processes increases when such a method is adopted.
本発明は上記のような事情を考慮してなされたものであり、その目的は、製造に必要な工程数を増加させることなく、III族窒化物層の結晶性が向上した半導体基板及びこれを用いた半導体装置を提供することにある。 The present invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor substrate having improved group III nitride layer crystallinity without increasing the number of steps required for production, and a semiconductor substrate thereof. It is to provide a semiconductor device used.
本発明者が鋭意検討を重ねた結果、Si基材上に適切なバッファー層を形成し、その上にAleGafIn1-e-fNx(0≦e≦1、0≦f≦1、かつ0≦e+f≦1)層と、AlgGahIn1-g-hNy(0≦g≦1、0≦h≦1、かつ0≦g+h≦1)層を、適正な層数ほど交互に積層し、さらにその上に基板として用いるAliGajIn1-i-jNz(0≦i≦1、0≦j≦1、かつ0≦i+j≦1)層を形成することにより、化合物半導体基板において、製造に必要な工程数を増加させることなく、化合物半導体層の結晶性を向上できることが見出された。 The inventors of the present inventors have intensive studies to form the appropriate buffer layer on a Si substrate, Al e Ga f In 1- ef N x (0 ≦ e ≦ 1,0 ≦ f ≦ 1 thereon, And 0 ≦ e + f ≦ 1) layers and Al g Ga h In 1-gh N y (0 ≦ g ≦ 1, 0 ≦ h ≦ 1 and 0 ≦ g + h ≦ 1) layers alternately in an appropriate number of layers. A compound semiconductor substrate is formed by stacking and further forming an Al i Ga j In 1-ij N z (0 ≦ i ≦ 1, 0 ≦ j ≦ 1, and 0 ≦ i + j ≦ 1) layer thereon as a substrate. Thus, it has been found that the crystallinity of the compound semiconductor layer can be improved without increasing the number of steps required for production.
すなわち本発明に係る半導体基板は、Si基材上に形成された第1のAlaGabIn1-a-bNv(0≦a≦1、0≦b≦1、かつ0≦a+b≦1)層と、
前記第1のAlaGabIn1-a-bNv層上に形成された第2のAlcGadIn1-c-dNw(0≦c≦1、0≦d≦1、かつ0≦c+d≦1)層と、
前記第2のAlcGadIn1-c-dNw層上に位置し、第3のAleGafIn1-e-fNx(0≦e≦1、0≦f≦1、かつ0≦e+f≦1)層及び第4のAlgGahIn1-g-hNy(0≦g≦1、0≦h≦1、かつ0≦g+h≦1)層を交互に積層した多層膜と、
前記多層膜上に形成された第5のAliGajIn1-i-jNz(0≦i≦1、0≦j≦1、かつ0≦i+j≦1)層と、
を具備し、前記多層膜における前記第3のAleGafIn1-e-fNx層と前記第4のAlgGahIn1-g-hNy層の積層数は160層以下であることを特徴とする。ただし、v、w、x、y、zは正数である。
That is, the semiconductor substrate according to the present invention includes a first Al a Ga b In 1-ab N v (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, and 0 ≦ a + b ≦ 1) formed on a Si base. Layers,
Second Al c Ga d In 1-cd N w (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, and 0 ≦ c + d) formed on the first Al a Ga b In 1-ab Nv layer ≦ 1) layer,
Located on the second Al c Ga d In 1-cd N w layer, the third Al e Ga f In 1-ef N x (0 ≦ e ≦ 1,0 ≦ f ≦ 1, and 0 ≦ e + f ≦ 1) a multilayer film in which layers and fourth Al g Ga h In 1-gh N y (0 ≦ g ≦ 1, 0 ≦ h ≦ 1, and 0 ≦ g + h ≦ 1) layers are alternately stacked;
A fifth Al i Ga j In 1-ij N z (0 ≦ i ≦ 1, 0 ≦ j ≦ 1, and 0 ≦ i + j ≦ 1) layer formed on the multilayer film;
Comprising a, the number of laminations of the third Al e Ga f In 1-ef N x layer and the fourth Al g Ga h In 1-gh N y layer in the multilayer film is less than 160 layers Features. However, v, w, x, y, and z are positive numbers.
前記多層膜が有する前記第3のAleGafIn1-e-fNx層と前記第4のAlgGahIn1-g-hNy層の積層数は40層以上、好ましくは60層以上であるのが好ましい。また、本発明において、二結晶X線回折法における前記第5のAliGajIn1-i-jNx層の(0004)面の回折ピークのロッキングカーブの半値幅を、800arcsec以下にすることができる。 In the said third Al e Ga f In 1-ef N x layer and the fourth Al g Ga h In 1-gh number of stacked N y layer is 40 or more layers multilayer film has preferably 60 or more layers Preferably there is. In the present invention, the half width of the rocking curve of the diffraction peak of the (0004) plane of the fifth Al i Ga j In 1-ij N x layer in the double crystal X-ray diffraction method may be 800 arcsec or less. it can.
本発明に係る半導体装置は、Si基材上に形成された第1のAlaGabIn1-a-bNv(0≦a≦1、0≦b≦1、かつ0≦a+b≦1)層と、
前記第1のAlaGabIn1-a-bNv層上に形成された第2のAlcGadIn1-c-dNw(0≦c≦1、0≦d≦1、かつ0≦c+d≦1)層と、
前記第2のAlcGadIn1-c-dNw層上に位置し、第3のAleGafIn1-e-fNx(0≦e≦1、0≦f≦1、かつ0≦e+f≦1)層と、第4のAlgGahIn1-g-hNy(0≦g≦1、0≦h≦1、かつ0≦g+h≦1)層を交互に積層した多層膜と、
前記多層膜上に形成された第5のAliGajIn1-i-jNz(0≦i≦1、0≦j≦1、かつ0≦i+j≦1)層と、
前記第5のAliGajIn1-i-jNz層を用いて形成された半導体素子と、
を具備し、前記多層膜における前記第3のAleGafIn1-e-fNx層と前記第4のAlgGahIn1-g-hNy層の積層数の積層数は160層以下であることを特徴とする。
この場合、前記半導体素子の表面のピット密度を1.3×1010cm-2にすることができる。
A semiconductor device according to the present invention includes a first Al a Ga b In 1-ab N v (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, and 0 ≦ a + b ≦ 1) layer formed on a Si substrate. When,
Second Al c Ga d In 1-cd N w (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, and 0 ≦ c + d) formed on the first Al a Ga b In 1-ab Nv layer ≦ 1) layer,
Located on the second Al c Ga d In 1-cd N w layer, the third Al e Ga f In 1-ef N x (0 ≦ e ≦ 1,0 ≦ f ≦ 1, and 0 ≦ e + f ≦ 1) and the layer, and the multilayer film and the fourth Al g Ga h in 1-gh N y (0 ≦ g ≦ 1,0 ≦ h ≦ 1, and 0 ≦ g + h ≦ 1) layer are alternately stacked,
A fifth Al i Ga j In 1-ij N z (0 ≦ i ≦ 1, 0 ≦ j ≦ 1, and 0 ≦ i + j ≦ 1) layer formed on the multilayer film;
A semiconductor element formed using the fifth Al i Ga j In 1-ij N z layer;
Comprising a number of stacked lamination number of the third Al e Ga f In 1-ef N x layer and the fourth Al g Ga h In 1-gh N y layer in the multilayer film is below 160 layers It is characterized by being.
In this case, the pit density on the surface of the semiconductor element can be 1.3 × 10 10 cm −2 .
本発明によれば、半導体基板及び半導体装置において、製造に必要な工程数を増加させることなく、Si基材上に成膜したIII族窒化物層の結晶性を向上させることができる。 According to the present invention, in the semiconductor substrate and the semiconductor device, the crystallinity of the group III nitride layer formed on the Si base can be improved without increasing the number of steps required for manufacturing.
以下、図1を参照して本発明の実施形態に係る半導体装置について説明する。この半導体装置において、表面が(111)面である第1導電型(例えばn型)のSi基材1にアンドープの第5のAliGajIn1-i-jNz(0≦i≦1、0≦j≦1、かつ0≦i+j≦1)層5を形成したものが、土台層として使用されている。Si基材1と第5のAliGajIn1-i-jNz層5の間には、バッファー層としての第1のAlaGabIn1-a-bNv(0≦a≦1、0≦b≦1、かつ0≦a+b≦1)層2(AlN層であってもよい)、第2のAlcGadIn1-c-dNw(0≦c≦1、0≦d≦1、かつ0≦c+d≦1)層3、及び、第3のAleGafIn1-e-fNx(0≦e≦1、0≦f≦1、かつ0≦e+f≦1)層(AlN層であっても良い)と、第4のAlgGahIn1-g-hNy(0≦g≦1、0≦h≦1、かつ0≦g+h≦1)層(GaN層であっても良い)を交互に積層した多層膜4が、この順に積層されている。なお、v、w、x、y、zは正数である。 A semiconductor device according to an embodiment of the present invention will be described below with reference to FIG. In this semiconductor device, an undoped fifth Al i Ga j In 1-ij N z (0 ≦ i ≦ 1, with a first conductivity type (for example, n-type) Si substrate 1 having a (111) surface on the surface. (0 ≦ j ≦ 1 and 0 ≦ i + j ≦ 1) The layer 5 is used as the base layer. Si substrate 1 and between the fifth Al i Ga j In 1-ij N z layer 5, the first as a buffer layer Al a Ga b In 1-ab N v (0 ≦ a ≦ 1,0 ≦ b ≦ 1 and 0 ≦ a + b ≦ 1) Layer 2 (may be an AlN layer), second Al c Ga d In 1-cd N w (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, and 0 ≦ c + d ≦ 1) layer 3, and, in the third Al e Ga f in 1-ef N x (0 ≦ e ≦ 1,0 ≦ f ≦ 1, and 0 ≦ e + f ≦ 1) layer (AlN layer And a fourth Al g Ga h In 1 -gh N y (0 ≦ g ≦ 1, 0 ≦ h ≦ 1, and 0 ≦ g + h ≦ 1) layer (may be a GaN layer) Are stacked in this order. Note that v, w, x, y, and z are positive numbers.
第1のAlaGabIn1-a-bNv層2の厚さは200nm以上、500nm以下であることが好ましい。200nm未満の場合はバッファー層としての機能が不十分であり、また500nm超とした場合、膜にクラックが生じ、上層に成長した膜の結晶性を劣化させてしまう。また、第2のAlcGadIn1-c-dNw層3の厚さは、クラックを抑制するという観点から、2μm以下とするのが好ましい。また、多層膜4において、第3のAleGafIn1-e-fNx層及び第4のAlgGahIn1-g-hNy層それぞれの厚さは、クラックを抑制するという観点から、5〜40nm及び2.5〜20nmとするのが好ましい。また、第3のAleGafIn1-e-fNx層及び第4のAlgGahIn1-g-hNy層の積層数が増加すると第5のAliGajIn1-i-jNz層5の結晶性がよくなるため、積層数の下限値は合計で40層以上、好ましくは合計で60層超とする。一方、第3のAleGafIn1-e-fNx層及び第4のAlgGahIn1-g-hNy層の積層数が増加するにつれて多層膜4に生じる応力が増大し、その結果第5のAliGajIn1-i-jNz層5にクラックが入って結晶性が必要な状態以下になるため、上限を合計で160層とする。 The thickness of the first Al a Ga b In 1-ab Nv layer 2 is preferably 200 nm or more and 500 nm or less. If it is less than 200 nm, the function as a buffer layer is insufficient, and if it exceeds 500 nm, cracks occur in the film and the crystallinity of the film grown on the upper layer is deteriorated. The thickness of the second Al c Ga d In 1 -cd N w layer 3 is preferably 2 μm or less from the viewpoint of suppressing cracks. Further, in the multilayer film 4, the third Al e Ga f In 1-ef N x layer and the fourth Al g Ga h In 1-gh N y layer each having a thickness of, from the viewpoint of suppressing cracks, It is preferable to set it as 5-40 nm and 2.5-20 nm. The third Al e Ga f In 1-ef N x layer and the fourth Al g Ga h In 1-gh when the number of stacked N y layer increases fifth Al i Ga j In 1-ij N z Since the crystallinity of the layer 5 is improved, the lower limit of the number of stacked layers is 40 or more in total, preferably 60 or more in total. Meanwhile, the stress generated in the multilayer film 4 as the number of stacked third Al e Ga f In 1-ef N x layer and the fourth Al g Ga h In 1-gh N y layer increases is increased, as a result Since the fifth Al i Ga j In 1-ij Nz layer 5 cracks and falls below the state where crystallinity is required, the upper limit is 160 layers in total.
バッファー層の構造を上記した構造にすることにより、製造に必要な工程数を増加させることなく、第5のAliGajIn1-i-jNz層5及びこれより上の層の結晶性を向上させることができる。
また、第5のAliGajIn1-i-jNz層5及びこれより上の層の結晶性が向上するため、発光素子の基板として用いた場合に、垂直共振器構造などの光反射鏡を有する構造を作製することもできる。
By making the structure of the buffer layer as described above, the crystallinity of the fifth Al i Ga j In 1-ij N z layer 5 and the layers above it can be increased without increasing the number of steps required for manufacturing. Can be improved.
Moreover, since the crystallinity of the fifth Al i Ga j In 1-ij N z layer 5 and the layer above the this is improved, when used as a substrate of a light emitting element, a light reflector, such as a vertical cavity structure It is also possible to produce a structure having
この基板(すなわち第5のAliGajIn1-i-jNz層5より下の層)を用いて作成した素子について、HEMTを例に説明する。第5のAliGajIn1-i-jNz層5上にはAlN層6を介して半導体層10が形成されている。半導体層10は、バリア層7(例えばAltGa1−tN(0<t<1)層)、第1導電型(例えばn型)のキャリア供給層8(例えばAltGa1−tN層)、及びキャップ層9(例えばAltGa1−tN層)をこの順に積層した構造を有している。半導体層10は、バンドギャップが第5のAliGajIn1-i-jNz層5よりも大きくなるように成分が設定されている。このため、半導体層10のキャリア供給層8から供給されたキャリアは、第5のAliGajIn1-i-jNz層5及びAlN層6の界面に蓄積され、これにより2次元電子ガスが形成され、高い移動度を示すことができる。 An element formed using this substrate (that is, a layer below the fifth Al i Ga j In 1-ij Nz layer 5) will be described by taking HEMT as an example. A semiconductor layer 10 is formed on the fifth Al i Ga j In 1-ij Nz layer 5 via an AlN layer 6. The semiconductor layer 10 includes a barrier layer 7 (for example, Al t Ga 1-t N (0 <t <1) layer), a first conductivity type (for example, n-type) carrier supply layer 8 (for example, Al t Ga 1-t N). Layer), and a cap layer 9 (for example, an Al t Ga 1-t N layer) are stacked in this order. The component of the semiconductor layer 10 is set so that the band gap is larger than that of the fifth Al i Ga j In 1-ij Nz layer 5. For this reason, the carriers supplied from the carrier supply layer 8 of the semiconductor layer 10 are accumulated at the interface between the fifth Al i Ga j In 1-ij N z layer 5 and the AlN layer 6, and thereby two-dimensional electron gas is generated. Formed and can exhibit high mobility.
次に、図1に示した半導体装置の製造方法について説明する。まずトリメチルアルミニウム(TMA)、トリメチルガリウム(TMG)、トリメチルインジウム(TMI)、及びNH3を原料ガスとしたMOCVD法により、第1のAlaGabIn1-a-bNv層2、第2のAlcGadIn1-c-dNw層3、多層膜4、及び第5のAliGajIn1-i-jNz層5を形成する。 Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, the first Al a Ga b In 1-ab N v layer 2, the second Al 2 Ga 2 In 2 -ab N v layer 2 are formed by MOCVD using trimethylaluminum (TMA), trimethylgallium (TMG), trimethylindium (TMI), and NH 3 as source gases. An Al c Ga d In 1 -cd N w layer 3, a multilayer film 4, and a fifth Al i Ga j In 1 -ij N z layer 5 are formed.
Si基材1と多層膜4の間のバッファー層が熱分解しやすい場合、多層膜4の形成工程においてバッファー層が熱分解してSi基材1と反応し、結果として上層の半導体層が多結晶構造になる(例えば特開2000−277441号公報の第6及び7段落参照)。これに対し、本発明では、バッファー層となる第1のAlaGabIn1-a-bNv層2及び第2のAlcGadIn1-c-dNw層3の融点が高い。従って、多層膜4及び第5のAliGajIn1-i-jNz層5の結晶性がよくなる。なお、第1のAlaGabIn1-a-bNv層2をAlN層とした場合、熱分解抑制効果が更に高くなる。ここで、AlN層の成長温度を1100℃以上にすることが好ましい。このようにすることでAlN層は高融点の半導体層になり、結晶化を施す為の熱処理が不要になり、生産効率が高くなる。 When the buffer layer between the Si base material 1 and the multilayer film 4 is likely to be thermally decomposed, the buffer layer is thermally decomposed and reacts with the Si base material 1 in the formation process of the multilayer film 4, resulting in a large number of upper semiconductor layers. It becomes a crystal structure (see, for example, paragraphs 6 and 7 of JP-A-2000-277441). On the other hand, in the present invention, the melting points of the first Al a Ga b In 1 -ab Nv layer 2 and the second Al c Ga d In 1 -cd N w layer 3 which are buffer layers are high. Therefore, the crystallinity of the multilayer film 4 and the fifth Al i Ga j In 1-ij Nz layer 5 is improved. When the first Al a Ga b In 1 -ab Nv layer 2 is an AlN layer, the effect of suppressing thermal decomposition is further increased. Here, the growth temperature of the AlN layer is preferably set to 1100 ° C. or higher. By doing so, the AlN layer becomes a high melting point semiconductor layer, heat treatment for crystallization is unnecessary, and the production efficiency is increased.
その後、TMA及びNH3を原料ガスとしたMOCVD法によりAlN層6を形成し、さらにTMG、TMA、及びNH3を原料ガスとしたMOCVD法により半導体層10を形成する。これらの工程は、同一の半導体製造装置内で連続して行うことができる。 Thereafter, the AlN layer 6 is formed by MOCVD using TMA and NH 3 as source gases, and further the semiconductor layer 10 is formed by MOCVD using TMG, TMA, and NH 3 as source gases. These steps can be performed continuously in the same semiconductor manufacturing apparatus.
上記した工程において、Si基材1の温度を900℃以上にするのが好ましい。
なお、Si基材1の温度を900℃以上にしても、上記したようにSi基材1の上には第1のAlaGabIn1-a-bNv層2及び第2のAlcGadIn1-c-dNw層3が形成されているため、これらより上に位置する各層とSi基材1が反応することを防止できる。このため、第5のAliGajIn1-i-jNz層5の結晶性及び平坦性が向上する。
In the above-described steps, it is preferable that the temperature of the Si base material 1 is 900 ° C. or higher.
Even when the temperature of the Si substrate 1 is 900 ° C. or higher, the first Al a Ga b In 1 -ab Nv layer 2 and the second Al c Ga are formed on the Si substrate 1 as described above. Since the d In 1 -cd N w layer 3 is formed, it is possible to prevent the Si base material 1 from reacting with each layer positioned above these layers. For this reason, the crystallinity and flatness of the fifth Al i Ga j In 1-ij N z layer 5 are improved.
上記した方法により、図1に示した構造を有しており、かつ多層膜4の積層数が互いに異なる5つの半導体装置を形成した。各半導体装置において、第1のAlaGabIn1-a-bNv層2はAlN層であり、その成長温度及び厚さは1000℃及び100nmである。AlcGadIn1-c-dNw層3は40nmのAl0.26Ga0.74N層であり、多層膜4はGaN(20nm)層とAlN(5nm)層を交互に900℃で積層したものである。多層膜4におけるGaN層とAlN層の積層数は、40層、60層、100層、140層、又は200層である。第5のAliGajIn1-i-jNz層5はGaN層で1μmであり、AlN層6は1nmである。半導体層10のバリア層7、キャリア供給層8、及びキャップ層9は、それぞれ7nmのAl0.26Ga0.74N層、15nmのn型Al0.26Ga0.74N層、及び3nmのAl0.26Ga0.74N層である。 By the method described above, five semiconductor devices having the structure shown in FIG. 1 and different in the number of stacked multilayer films 4 were formed. In each semiconductor device, the first Al a Ga b In 1 -ab Nv layer 2 is an AlN layer, and its growth temperature and thickness are 1000 ° C. and 100 nm. The Al c Ga d In 1 -cd N w layer 3 is an Al 0.26 Ga 0.74 N layer having a thickness of 40 nm, and the multilayer film 4 is formed by alternately laminating GaN (20 nm) layers and AlN (5 nm) layers at 900 ° C. . The number of stacked GaN layers and AlN layers in the multilayer film 4 is 40 layers, 60 layers, 100 layers, 140 layers, or 200 layers. The fifth Al i Ga j In 1-ij Nz layer 5 is a GaN layer of 1 μm, and the AlN layer 6 is 1 nm. The barrier layer 7, the carrier supply layer 8, and the cap layer 9 of the semiconductor layer 10 are respectively 7 nm Al 0.26 Ga 0.74 N layer, 15 nm n-type Al 0.26 Ga 0.74 N layer, and 3 nm. Al 0.26 Ga 0.74 N layer.
図2の各図は、各試料におけるGaN層5の表面SEM写真である。多層膜4における積層数が140層以下の場合は、GaN層5にクラックが入っていないが、積層数が200層の場合は、GaN層5にクラックが入っていたため、後述する各種特性の測定が不可能だった。また、多層膜4の積層数が60層以上になると、GaN層5のピット数が減少し、平坦性が十分に向上した。このため、多層膜4の積層数は60層以上が好ましいと判断できる。 Each drawing in FIG. 2 is a surface SEM photograph of the GaN layer 5 in each sample. When the number of stacked layers in the multilayer film 4 is 140 or less, the GaN layer 5 is not cracked. However, when the number of stacked layers is 200, the GaN layer 5 was cracked. Was impossible. Further, when the number of laminated multilayer films 4 was 60 or more, the number of pits in the GaN layer 5 was reduced, and the flatness was sufficiently improved. For this reason, it can be judged that the number of laminated multilayer films 4 is preferably 60 or more.
図3は、多層膜4の積層数と基板の反り(基板中心部と縁部の高さの差:μm)の関係を示すグラフである。多層膜4の積層数が増加するにつれて、基板の反りは73μmから148μmへ直線的に増加した。
本図及び図2で説明した結果より、多層膜4における積層数が160層以上になるとGaN層5にクラックが生じて必要な特性を有さなくなると判断できる。
FIG. 3 is a graph showing the relationship between the number of stacked multilayer films 4 and the warpage of the substrate (the difference between the height of the substrate center and the edge: μm). As the number of laminated multilayer films 4 increased, the warpage of the substrate increased linearly from 73 μm to 148 μm.
From the results described with reference to FIGS. 2 and 2, it can be determined that if the number of stacked layers in the multilayer film 4 is 160 or more, the GaN layer 5 is cracked and does not have the necessary characteristics.
図4は、二結晶X線回折法における、GaN層5の(0004)面及び(2024)面それぞれからの回折ピークのロッキングカーブの半値幅と、多層膜4の積層数の関係を示すグラフである。(0004)面及び(2024)面それぞれからの回折ピークの半値幅は、多層膜4の積層数が40層の場合は770arcsec,1589arcsecであるのに対し、積層数が140層の場合は688arcsec,1118arcsecであった。このことから、多層膜4の積層数が増加するにつれて第5のAliGajIn1-i-jNz層5の結晶性がよくなることが分かった。特に積層数を60層以上にすると、(0004)面及び(2024)面それぞれからの回折ピークの半値幅は715arcsec以下及び1490arcsec以下となり、結晶性を十分高くできることが分かった。 FIG. 4 is a graph showing the relationship between the full width at half maximum of the rocking curve of the diffraction peak from each of the (0004) plane and the (2024) plane of the GaN layer 5 and the number of stacked multilayer films 4 in the double crystal X-ray diffraction method. is there. The half width of the diffraction peak from each of the (0004) plane and the (2024) plane is 770 arcsec and 1589 arcsec when the number of stacked multilayer films 4 is 40 layers, whereas it is 688 arcsec when the number of stacked layers is 140 layers. 1118 arcsec. From this, it was found that the crystallinity of the fifth Al i Ga j In 1-ij Nz layer 5 improved as the number of multilayer films 4 stacked increased. In particular, when the number of stacked layers is 60 or more, the half-value widths of the diffraction peaks from the (0004) plane and the (2024) plane are 715 arcsec or less and 1490 arcsec or less, respectively, and it has been found that the crystallinity can be sufficiently increased.
図5(A)〜(E)それぞれは、多層膜4の積層数が40層、60層、100層、140層、及び200層の場合のGaN層5の表面の原子間力顕微鏡(AFM)写真であり、図6はGaN層5表面のピット密度を多層膜4の積層数別に示す図表である。これらの写真及び図表から、多層膜4の積層数が増えるにつれて第5のAliGajIn1-i-jNz層5表面のピット密度が1.3×1010(cm-2)、1.1×1010(cm-2)、7.3×109(cm-2)、3.8×109(cm-2)、及び3.1×109(cm-2)と低下していることが分かった。ただし、上記したように積層数が200層の場合はクラックが発生した。 5A to 5E respectively show an atomic force microscope (AFM) on the surface of the GaN layer 5 when the number of stacked multilayer films 4 is 40, 60, 100, 140, and 200. FIG. 6 is a chart showing the pit density on the surface of the GaN layer 5 according to the number of stacked multilayer films 4. From these photographs and diagrams, the pit density on the surface of the fifth Al i Ga j In 1-ij N z layer 5 is 1.3 × 10 10 (cm −2 ) as the number of stacked multilayer films 4 increases. 1 × 10 10 (cm −2 ), 7.3 × 10 9 (cm −2 ), 3.8 × 10 9 (cm −2 ), and 3.1 × 10 9 (cm −2 ) I found out. However, cracks occurred when the number of laminated layers was 200 as described above.
図7は、多層膜4の積層数が40層、100層、及び140層の半導体装置における、2次元電子ガスによるキャリア(電子)の移動度及びキャリア密度の温度依存性を示すグラフである。なお、このキャリアはGaN層5及びAlN層6の界面に蓄積したものである。本グラフにおいて横軸は温度である。また図8は多層膜4の積層数と半導体装置のシート抵抗の関係を示すグラフである。 FIG. 7 is a graph showing the temperature dependence of carrier (electron) mobility and carrier density due to a two-dimensional electron gas in a semiconductor device in which the number of stacked multilayer films 4 is 40 layers, 100 layers, and 140 layers. The carriers are accumulated at the interface between the GaN layer 5 and the AlN layer 6. In this graph, the horizontal axis is temperature. FIG. 8 is a graph showing the relationship between the number of stacked multilayer films 4 and the sheet resistance of the semiconductor device.
キャリア移動度は、多層膜4の積層数が増加するにつれて、いずれの温度においても上昇した。具体的な値を示すと、77K及び室温におけるキャリアの移動度は、多層膜4の積層数が40層の場合は6227cm2/Vs、1414cm2/Vsであったが、多層膜4の積層数が140層の場合は10958cm2/Vs、1524cm2/Vsであった。電子の移動度がこのような傾向を示したのは、多層膜4の積層数が増えることで多層膜4より上の各層の結晶性が向上し、結晶欠陥による散乱が減少していることに起因すると考えられる。 The carrier mobility increased at any temperature as the number of stacked multilayer films 4 increased. When showing a specific value, the mobility of carriers in the 77K and room temperature, 6227cm 2 / Vs when the number of laminated multi-layer film 4 is 40 layers, but was 1414cm 2 / Vs, the number of laminated multi-layer film 4 Of 140 layers were 10958 cm 2 / Vs and 1524 cm 2 / Vs. The electron mobility showed this tendency because the crystallinity of each layer above the multilayer film 4 was improved and the scattering due to crystal defects was reduced by increasing the number of multilayer films 4 stacked. It is thought to be caused.
以上の結果より、多層膜4の積層数が40層以上(好ましくは60層以上)160層以下の場合に、第5のAliGajIn1-i-jNz層5及びその上の各層の結晶性がよくなり、かつ第5のAliGajIn1-i-jNz層5を用いて形成した半導体装置の特性も向上することが分かった。 From the above results, when the number of stacked multilayer films 4 is 40 layers or more (preferably 60 layers or more) and 160 layers or less, the fifth Al i Ga j In 1-ij N z layer 5 and each layer on the fifth Al i Ga j In 1-ij N z layer 5 It has been found that the crystallinity is improved and the characteristics of the semiconductor device formed using the fifth Al i Ga j In 1-ij Nz layer 5 are also improved.
尚、本発明は上述した実施形態又は実施例に限定されるものではなく、本発明の主旨を逸脱しない範囲内で種々変更して実施することが可能である。 Note that the present invention is not limited to the above-described embodiments or examples, and various modifications can be made without departing from the spirit of the present invention.
1…Si基材、2…第1のAlaGabIn1-a-bNv層、3…第2のAlcGadIn1-c-dNw層、4…多層膜、5…第5のAliGajIn1-i-jNz層、6…AlN層、7…バリア層、8…キャリア供給層、9…キャップ層、10…半導体層 1 ... Si substrate, 2 ... first Al a Ga b In 1-ab N v layer, 3 ... second Al c Ga d In 1-cd N w layer, 4 ... multilayer film, 5 ... fifth al i Ga j In 1-ij N z layer, 6 ... AlN layer, 7 ... barrier layer, 8 ... carrier supply layer, 9 ... cap layer, 10 ... semiconductor layer
Claims (5)
前記第1のAlaGabIn1-a-bNv層上に形成された第2のAlcGadIn1-c-dNw(0≦c≦1、0≦d≦1、かつ0≦c+d≦1)層と、
前記第2のAlcGadIn1-c-dNw層上に位置し、第3のAleGafIn1-e-fNx(0≦e≦1、0≦f≦1、かつ0≦e+f≦1)層及び第4のAlgGahIn1-g-hNy(0≦g≦1、0≦h≦1、かつ0≦g+h≦1)層を交互に積層した多層膜と、
前記多層膜上に形成された第5のAliGajIn1-i-jNz(0≦i≦1、0≦j≦1、かつ0≦i+j≦1)層と、
を具備し、前記多層膜における前記第3のAleGafIn1-e-fNx層と前記第4のAlgGahIn1-g-hNy層の積層数は160層以下であることを特徴とする半導体基板。
ただし、v、w、x、y、zは正数である。 A first Al a Ga b In 1-ab N v (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, and 0 ≦ a + b ≦ 1) layer formed on a Si substrate;
Second Al c Ga d In 1-cd N w (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, and 0 ≦ c + d) formed on the first Al a Ga b In 1-ab Nv layer ≦ 1) layer,
Located on the second Al c Ga d In 1-cd N w layer, the third Al e Ga f In 1-ef N x (0 ≦ e ≦ 1,0 ≦ f ≦ 1, and 0 ≦ e + f ≦ 1) a multilayer film in which layers and fourth Al g Ga h In 1-gh N y (0 ≦ g ≦ 1, 0 ≦ h ≦ 1, and 0 ≦ g + h ≦ 1) layers are alternately stacked;
A fifth Al i Ga j In 1-ij N z (0 ≦ i ≦ 1, 0 ≦ j ≦ 1, and 0 ≦ i + j ≦ 1) layer formed on the multilayer film;
Comprising a, the number of laminations of the third Al e Ga f In 1-ef N x layer and the fourth Al g Ga h In 1-gh N y layer in the multilayer film is less than 160 layers A characteristic semiconductor substrate.
However, v, w, x, y, and z are positive numbers.
前記第1のAlaGabIn1-a-bNv層上に形成された第2のAlcGadIn1-c-dNw(0≦c≦1、0≦d≦1、かつ0≦c+d≦1)層と、
前記第2のAlcGadIn1-c-dNw層上に位置し、第3のAleGafIn1-e-fNx(0≦e≦1、0≦f≦1、かつ0≦e+f≦1)層及び第4のAlgGahIn1-g-hNy(0≦g≦1、0≦h≦1、かつ0≦g+h≦1)層を交互に積層した多層膜と、
前記多層膜上に形成された第5のAliGajIn1-i-jNz(0≦i≦1、0≦j≦1、かつ0≦i+j≦1)層と、
前記第5のAliGajIn1-i-jNz層を用いて形成された半導体素子と、
を具備し、前記多層膜における前記第3のAleGafIn1-e-fNx層と前記第4のAlgGahIn1-g-hNy層の積層数の積層数は160層以下であることを特徴とする半導体装置。 A first Al a Ga b In 1-ab N v (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, and 0 ≦ a + b ≦ 1) layer formed on a Si substrate;
Second Al c Ga d In 1-cd N w (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, and 0 ≦ c + d) formed on the first Al a Ga b In 1-ab Nv layer ≦ 1) layer,
Located on the second Al c Ga d In 1-cd N w layer, the third Al e Ga f In 1-ef N x (0 ≦ e ≦ 1,0 ≦ f ≦ 1, and 0 ≦ e + f ≦ 1) a multilayer film in which layers and fourth Al g Ga h In 1-gh N y (0 ≦ g ≦ 1, 0 ≦ h ≦ 1, and 0 ≦ g + h ≦ 1) layers are alternately stacked;
A fifth Al i Ga j In 1-ij N z (0 ≦ i ≦ 1, 0 ≦ j ≦ 1, and 0 ≦ i + j ≦ 1) layer formed on the multilayer film;
A semiconductor element formed using the fifth Al i Ga j In 1-ij N z layer;
Comprising a number of stacked lamination number of the third Al e Ga f In 1-ef N x layer and the fourth Al g Ga h In 1-gh N y layer in the multilayer film is below 160 layers There is a semiconductor device.
The semiconductor device according to claim 4, wherein a pit density on the surface of the semiconductor element is 1.3 × 10 10 cm −2 or less.
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