JP2007241306A - Driving circuit for display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control the number of colors displayed on a panel type display device which controls display luminance by an applied voltage, and to reduce the power consumption. <P>SOLUTION: A driving circuit for the display device includes; a frame memory 105 wherein original image data inputted from a host device 102 through an interface 103 is stored; a color reduction processing means 104 which reduces the amount of information of the number of colors which gradation data of an original image has, in accordance with color reduction rate data inputted by transfer from the host device 102 or inputted by using an operation switch or a manual setting means of terminal setting or the like and uses only the reduced number of colors to artificially express the number of colors of the original image; a timing generation part 106; a gray scale voltage generation part 107; and a gray scale voltage selector 108 which stops a part of operations of the driving circuit in accordance with the color reduction rate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a panel-type display device that controls display luminance by an applied voltage, and more particularly to a technology for a display device drive circuit that realizes low power consumption by controlling the number of colors to be displayed.

  As a technology for reducing the power consumption of a display device that controls display brightness by applying voltage, there are display devices described in “Asia Display / IDW'01” published by ITE / SID, and Proceedings P1583 to 1586. This display device performs color reduction processing by dithering the input gradation data, and expresses the actual number of colors with a smaller number of colors than the original number of colors (hereinafter also referred to as the actual number of colors). To do. Thereby, compared with the case where the actual color number is displayed as it is, low power consumption can be achieved.

  Generally, in color reduction processing such as dithering, the ratio of the number of color reductions to the actual number of colors (hereinafter referred to as the color reduction rate) can be selected. The smaller the color reduction rate (closer to the actual color number), the less the image quality degradation and the larger As a result, the image quality deteriorates. On the other hand, in a display device, the circuit operation can generally be reduced as the number of colors to be displayed is reduced, so that power consumption can be reduced.

  Thus, depending on the purpose of use of the display device, high-quality display with a low color reduction rate and low power operation with a high color reduction rate can be considered. However, the color reduction rate described in the prior art is constant (260,000 colors are reduced to 4096 colors), and the above-described usage pattern has not been considered.

  An object of the present invention is to provide a display device that reduces the number of colors of an original image input from a host device and suppresses power consumption according to the reduction, and realizes a long-time operation, and a driving circuit thereof. is there.

  In order to solve the above problems, the display device of the present invention can display an image with a plurality of color reduction ratios, and can perform color reduction using transfer from a host device (for example, CPU) or manual setting means such as operation switches and terminal settings. It was also possible to switch the rate from the outside. In realizing this function, the display device of the present invention reduces the amount of color information included in the gradation data of the original image according to the color reduction rate data specifying the color reduction rate, and uses only the reduced number of colors. Thus, a color reduction processing means for representing the number of colors of the original image in a pseudo manner and a means for partially stopping the operation of the drive circuit in accordance with the color reduction rate are newly provided for the conventional display device.

  According to the present invention, in a display device that controls display luminance by an applied voltage and a drive circuit for the display device, color reduction rate data is input from the outside, and the number of colors to be displayed on the display is switched according to the color reduction rate data. At the same time, by providing a function of stopping unnecessary drive circuits in accordance with the number of colors to be displayed, the power consumption of the display device can be reduced. Further, since a high image quality mode with a small number of color reductions and a low power consumption mode with a large number of color reductions can be switched according to the color reduction rate data, a display device with improved usability can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings of the examples. First, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram illustrating a display device driving circuit according to a first embodiment of a display device according to the present invention. In FIG. 1, reference numeral 101 is a data line driving unit, 102 is a CPU, 103 is an interface, 104 is a dither processing unit, 105 is a frame memory, 106 is a timing generation unit, 107 is a gradation voltage generation unit, and 108 is a gradation. A voltage selector 109 is a pixel portion. FIG. 2 is an explanatory diagram of the interface input signal according to the first embodiment of the present invention, and FIG. 3 is a timing chart showing the operation of the interface input signal according to the first embodiment of the present invention.

  In the embodiment of the present invention, the pixel unit 109 is, for example, a TFT liquid crystal, and the data line driving unit 101 outputs a gradation voltage of a level corresponding to the gradation data to the pixel unit 109, thereby displaying a multicolor display. Shall be performed. In this embodiment, the gradation data input to the display device is 6-bit digital data for each of R (red), G (green), and B (blue), and 262,144 colors per pixel. Information shall be included.

  First, the operation of the data line driving unit 101 will be described. A signal related to display is given from the CPU 102 to the data line driving unit 101. This signal includes gradation data indicating the degree of color shading, an address indicating the display position, and color reduction rate data, which is a feature of the present invention. Further, as shown in FIG. 2, signals from the CPU 102 and the interface 103 are an RS signal for selecting address / gradation data, a WR signal for instructing start of writing, and an actual value of address / gradation data D Consists of signals.

  These signal groups have a cycle for designating an address and a cycle for writing gradation data, as shown in FIG. For example, in the addressing cycle, the operation is executed when the RS signal is set to “low”, the D signal is set to a predetermined address value, and then the WR signal is set to “low”. On the other hand, in the gradation data writing cycle, the operation is executed when the RS signal is set to “high”, the signal is set to predetermined gradation data, and then the WR signal is set to “low”. These operations are programmed in advance by an operating system and application software for controlling the entire apparatus. Next, the breakdown of the D signal is shown in FIG.

  FIG. 4 is an explanatory diagram of interface input signals according to the first embodiment of the present invention. As shown in FIG. 4, the D signal, which is the actual value of the address / gradation data, is 18 bits. This D signal is composed of horizontal and vertical addresses (8 bits each) in the addressing cycle, and RGB gradation data (6 bits each) in the gradation data writing cycle. FIG. 5 is an explanatory diagram of the interface input signal according to the first embodiment of the present invention, and shows an example of the interface transfer. The interface 103 decodes the display signal transferred from the CPU, separates it into an address and gradation data, and outputs it.

  FIG. 6 is an explanatory diagram of the color reduction rate data according to the first embodiment of the present invention. The dither processing unit 104 shown in FIG. 1 receives gradation data, address, and color reduction rate data, reduces the gradation data by dithering, and outputs the result as reduced gradation data. Here, the color reduction rate data is 2-bit data for instructing three types of color reduction rates. As shown in FIG. 6, how many bits are added to the input RGB gradation data (each 6 bits). Indicates whether to dither.

  FIG. 7 is a diagram illustrating the principle of the dithering method according to the first embodiment of the present invention. Dither processing is a technique for spatially combining existing colors to generate intermediate colors, and FIG. 7 shows an example of processing for each color reduction rate. Next, the configuration and operation of the dither processing unit 104 will be described with reference to FIGS.

  FIG. 8 is a block diagram showing the configuration of the dither processing unit according to the first embodiment of the present invention, and FIG. 9 is an operation explanatory diagram of the dither signal generation unit according to the first embodiment of the present invention. In FIG. 8, the dither processing unit 104 includes a dither signal generation unit 801 and data conversion units 802, 803, and 804 for R, G, and B, respectively. As shown in FIG. 9, the dither signal generation unit 801 generates four types of dither signals A to D corresponding to the value of the least significant bit in the horizontal direction and the vertical direction of the input address.

  FIG. 10 is a diagram for explaining the operation of the dither signal generator according to the first embodiment of the present invention. FIG. 10 shows the dither signal value for the actual screen, which is equivalent to the existing color combination pattern shown in FIG. FIG. 11 is a block diagram showing the configuration of the data conversion unit according to the first embodiment of the present invention. As shown in FIG. 11, the data converter 802 includes a dither signal selector 1101, a bit operation unit A1102, a subtractor 1103, and a bit operation unit B1104. In FIG. 11, bit operation A and bit operation B are simply described.

  FIG. 12 is a diagram for explaining the operation of the dither signal selector according to the first embodiment of the present invention. The dither signal selector 1101 in FIG. 11 selects and outputs one type from the dither signals A to D according to the lower 2 bits of the 6-bit gradation data. Here, the selected dither signal differs depending on the color reduction rate data. This relationship is shown in FIG.

  FIG. 13 is an explanatory diagram of the operation of the bit operation unit A according to the first embodiment of the present invention. The bit operation unit A1102 adds “0” to the selected dither signal to make it 6 bits, and to which bit “0” is added depends on the color reduction rate data. This relationship is shown in FIG. The purpose of this bit operation is to facilitate the subsequent subtraction operation. The reason why the output value of the bit operation unit A is changed according to the value of the upper bit of the gradation data is to avoid the subtraction result from becoming negative.

  FIG. 14 is an explanatory diagram of the operation of the bit operation unit B according to the first embodiment of the present invention. FIG. 15 is a diagram for explaining the operation of the dither processing unit according to the first embodiment of the present invention. The subtractor 1103 subtracts the output of the bit operation unit A from the gradation data and outputs the result. Then, as shown in FIG. 14, the bit operation unit B1104 rearranges the gradation data bits according to the subtraction rate data, and outputs the result as subtractive gradation data.

  By the dither processing described above, the input gradation data is converted to the subtractive gradation data shown in FIG. In FIG. 15, the shaded portion means that two types of gradation data are mixed depending on the display position. For example, 12 and 14 are assigned gradation data of 12 and 14 depending on the display position. Next, a specific example assuming an actual screen of the dither processing will be described.

  FIG. 16 is a diagram for explaining the operation of the dither processing unit according to the first embodiment of the present invention. As shown in FIG. 16, it can be seen that the conversion operation from gradation data to subtractive gradation data is equivalent to a color reduction process by dithering in units of 2 × 2 pixels. An error diffusion method is well known as another method of color reduction processing, but it is of course possible to apply this method. The error diffusion method can reduce the image quality to a higher image quality than dithering, but the circuit scale becomes large, so it is desirable to use it properly according to the application.

  Next, the frame memory 105 stores the subtractive color gradation data at a predetermined address according to the address transferred from the interface 103. The frame memory 105 can be composed of a general SRAM. The timing generation unit 106 generates a timing signal group described later and outputs it to the frame memory 105 and the gradation voltage selector 108. The timing signal includes a frame memory read control signal. By this control signal, the color-reduced gradation data is read from the frame memory 105 one line at a time in order from the first line of the screen. Return to and repeat this operation. Note that the read line switching timing is synchronized with the line signal supplied from the timing generation unit 106, and the timing for selecting the first word line is synchronized with the frame signal supplied from the timing generation unit 107. These specific timings are shown in FIG.

  FIG. 17 is a circuit diagram illustrating the configuration of the grayscale voltage generator according to the first embodiment of the present invention. The gradation voltage generation unit 107 is a block for generating a gradation voltage group necessary for converting gradation data into a voltage level, and FIG. 17 shows an internal structure thereof. In FIG. 17, reference numerals VDH and VDD are respectively given from the outside, VDH is a reference voltage for generating a gradation voltage, and VDD is a power supply voltage of the operational amplifier.

  First, 64 kinds of gradation voltages V0 to V63 are generated by resistance-dividing the reference voltage VDH, and each gradation voltage is buffered by an operational amplifier of a voltage follower circuit. Here, as shown in FIG. 17, the power supply of the operational amplifier is controlled by switches 1701 and 1702 using the color reduction rate data as control signals.

  FIG. 18 is a diagram for explaining the operation of the gradation voltage generator according to the first embodiment of the present invention, and shows the power supply state of the operational amplifier at each color reduction rate. In FIG. 18, the shaded portion is an operational amplifier with power supply OFF, and the other power supply ON. Here, when attention is focused on a group of operational amplifiers in which power supply is turned on for each color reduction rate, the numbers of gradation voltages buffered by these are equal to the group of color reduction gradation data shown in FIG. This is because the subtractive gradation data and the gradation voltage number are intentionally matched. As a result, it is possible to supply power only to the operational amplifier to be used. Further, paying attention to FIG. 15, it can be seen that the gradation voltages V0 and V63 are all used at the color reduction rate, and the other gradation voltages used are at a level obtained by dividing V0 and V63 as evenly as possible. This is to maximize the display contrast (dynamic range) in any color reduction rate mode. The gradation voltage selector 108 is a block that selects and outputs one level from a plurality of gradation voltages according to the subtractive gradation data.

  FIG. 19 is a block diagram showing the configuration of the gradation voltage selector according to the first embodiment of the present invention. FIG. 20 is a timing chart for explaining the operation of the gradation voltage selector according to the first embodiment of the present invention. FIG. 21 is a diagram for explaining the operation of the selector according to the first embodiment of the present invention. The gradation voltage selector includes a latch unit 1901 and a selector 1902. The latch unit 1901 takes in the color-reduced gradation data for one line output from the frame memory 105 in synchronization with the line signal and outputs it to the selector 1902. A selector 1902 selects one level from a plurality of gradation voltages in accordance with the subtractive gradation data and the AC signal.

  FIG. 22 is an equivalent circuit diagram showing the configuration of the pixel portion according to the first embodiment of the present invention. The pixel portion 109 includes a three-terminal thin film transistor TFT element, a liquid crystal layer, and a storage capacitor. The drain terminal of the thin film transistor TFT element is connected to the data line, the gate terminal is connected to the scanning line, and the source terminal is connected to the liquid crystal cell and the storage capacitor. . A common counter electrode is provided on the opposite side of the liquid crystal layer, and is electrically connected to the liquid crystal layer. Further, the other terminal of the storage capacitor is connected to the preceding scanning line. In order to realize this configuration, for example, data lines and scanning lines are formed in a matrix on one inner surface of two transparent substrates sandwiching liquid crystal, and a counter electrode is formed in a solid shape on the other inner surface. Note that the circuit configuration of the pixel in this embodiment is a so-called Cadd structure, but it can also be applied to a so-called Cst structure in which a terminal of a storage capacitor is connected to a storage line.

  Here, the display device driving circuit 101 of the present invention is connected to the data lines of the pixel portion 109 described above, and outputs a desired gradation voltage to each data line. In order to realize an actual display device, a scanning line driving unit and a power supply circuit are necessary, and existing circuits can be used for these. This will be described with reference to FIG.

  FIG. 23 is a timing chart showing the operation of the peripheral circuit according to the first embodiment of the present invention. For example, as shown in FIG. 23, the scanning line driving unit applies a “high voltage” to the first scanning line in synchronization with the frame signal, and then sequentially applies the “high voltage” in synchronization with the line signal. Apply to scan line. Here, the timing of switching from the “high voltage” to the “low voltage” is immediately before the switching timing of the gradation voltage, and the gradation voltage at this time becomes a level corresponding to the gradation data on the scanning line. Further, the scan line driver can be easily realized by applying a shift register circuit.

  On the other hand, the counter voltage, which is a voltage applied to the counter electrode, has a waveform synchronized with the AC signal, and this can be realized by a circuit that adjusts the amplitude of the AC signal. Note that the polarity of the liquid crystal application voltage can be considered as the polarity of the gradation voltage as viewed from the counter voltage, and the polarity of the liquid crystal application voltage is inverted in conjunction with the AC signal. This operation is equivalent to so-called common inversion driving. Although the common inversion drive is taken as an example in the first embodiment of the present invention, the present invention is not limited to this, and so-called dot inversion drive or column-by-column inversion drive that does not amplitude the counter voltage is easy. It is applicable to. In this embodiment, the type of display has been described as a thin film transistor TFT type liquid crystal display device. However, the present invention is not limited to this, and other displays that control display luminance at a voltage level, such as organic EL displays. The present invention can also be applied. Note that the data line driving unit of the first embodiment of the present invention is desirably integrated by LSI.

  The first embodiment of the present invention described above has the function of switching the number of colors displayed on the display in accordance with the color reduction rate data and stopping unnecessary drive circuits in accordance with the number of colors to be displayed. Therefore, the power consumption of the display device can be reduced. In addition, ease of use is improved by enabling switching between a high image quality mode with less color reduction and a low power consumption mode with much color reduction. For example, by using the display device of the present invention and a display device driving circuit as a display device for a mobile phone, a low power consumption mode with a large number of color reductions during standby can be achieved. It is conceivable to apply a few high image quality modes. This switching may be performed automatically, for example, by the CPU of the terminal device monitoring the operating state, or manually by the user by means of manual setting, terminal setting, or the like.

  Next, a second embodiment of the present invention will be described with reference to FIGS. In the above-described first embodiment of the present invention, the dithering method is applied to the color reduction processing. In contrast, the second embodiment of the present invention applies the FRC method to the color reduction processing method. The FRC method is an abbreviation for frame rate control. As shown in FIG. 25, this FRC method is a technique for generating an intermediate color by combining existing colors spatially and temporally. Compared with the above-described dithering, the intermediate color is not sacrificed in resolution. Characterized by the point that can be expressed.

  FIG. 24 is a block diagram showing a configuration of a display device driving circuit according to the second embodiment of the display device of the present invention. FIG. 25 is a diagram for explaining the principle of the FRC method according to the second embodiment of the present invention. FIG. 26 is an explanatory diagram of color reduction rate data according to the second embodiment of the present invention. In FIG. 24, reference numeral 2401 denotes a data line driving circuit, and 2402 denotes an FRC processing unit. The other blocks are the same as those in the first embodiment of the present invention described above, and are denoted by the same numbers. The data line driving circuit 2401 in this embodiment is greatly different from the data line driving circuit 101 in the first embodiment of the present invention in that an FRC processing unit 2402 is provided in the subsequent stage of the frame memory 105. This is because in the FRC method, the display image is switched every frame period, which is the scanning time for one screen, so that the reading operation of the frame memory 105 needs to be synchronized with the color reduction processing.

  Accordingly, the FRC processing unit 2402 performs FRC processing corresponding to the input color reduction rate data on all the gradation data for one line sequentially read from the frame memory 105 and outputs the result to the gradation voltage selector 108. In this embodiment, the color reduction rate data is 1-bit data that designates two types of color reduction rates, and as shown in FIG. 26, how many bits of FRC the RGB grayscale data (each 6 bits) is FRC. Instruct whether to process.

  FIG. 27 is a block diagram showing the configuration of the FRC processing unit according to the second embodiment of the present invention. 28 is a block diagram showing the configuration of the FRC signal generator according to the second embodiment of the present invention, FIG. 29 is a timing chart showing the operation of the FRC signal generator according to the second embodiment of the present invention, and FIG. FIG. 31 is an operation explanatory diagram of the FRC signal generation unit according to the second embodiment of the present invention, and FIG. 31 is a block diagram showing the configuration of the data conversion unit according to the second embodiment of the present invention. In FIG. 27, reference numeral 2701 is an FRC signal generator, and 2702 is a data converter. As shown in FIG. 28, the FRC signal generation unit 2701 generates two types of FRC signals from the frame signal and the line signal transferred from the timing generation unit 106. These timing charts are shown in FIG.

  The two types of FRC signals are alternately connected to the respective data conversion units as shown in FIG. Thereby, the value of the FRC signal with respect to an actual screen becomes the arrangement shown in FIG. This is equivalent to the existing color combination pattern shown in FIG. Next, the data conversion unit 2702 includes a bit operation unit A 3101, a subtracter 3102, and a bit operation unit B 3103 as shown in FIG. The bit operation unit A 3101 adds “0” to the FRC signal to make it 6 bits, and which bit is added “0” differs depending on the color reduction rate data.

  FIG. 32 is an operation explanatory diagram of the bit operation unit A according to the second embodiment of the present invention, and FIG. 33 is an operation explanatory diagram of the bit operation unit B according to the second embodiment of the present invention. FIG. 32 shows a relationship in which “0” is added to the above FRC signal to form 6 bits. The purpose of this bit operation is to facilitate the subtraction operation of the next stage, and the reason for changing the output value of the bit operation unit A according to the value of the upper bit of the gradation data is that the subtraction result is negative. This is to avoid becoming.

  Next, the subtractor 3102 subtracts the output of the bit operation unit A from the gradation data and outputs the result. Then, as shown in FIG. 33, the bit operation unit B3103 rearranges the gradation data bits according to the subtraction rate data, and outputs the result as subtractive gradation data.

  By performing the FRC process described above on all the gradation data for one line at the same time, it is possible to realize a color reduction process by the FRC method in units of 2 × 2 pixels. In this embodiment, the example in which the FRC process is performed on the least significant bit in the 6-bit gradation data is shown. However, the present invention is not limited to this, and the FRC process is performed on the lower 2 bits. Of course it is also possible.

  The other blocks execute the same functions as the blocks shown in the first embodiment of the present invention, and thus the description thereof is omitted.

  In the second embodiment of the present invention described above, the number of colors to be displayed on the display is switched according to the color reduction rate data, and is not necessary according to the number of colors to be displayed, as in the first embodiment of the present invention. Since the driver circuit has a function of stopping, the power consumption of the display device can be reduced. In addition, it is possible to switch between a high image quality mode with a small number of color reductions and a low power consumption mode with a large number of color reductions, which improves usability. Furthermore, since the FRC method is used for the color reduction processing, it is possible to express intermediate colors without sacrificing resolution.

  FIG. 34 is a block diagram showing a configuration of a display device drive circuit according to the second embodiment of the present invention. As shown in FIG. 34, a display device drive circuit including both dither processing and FRC processing can be realized. In this case, either the dither processing or the FRC processing may be operated, or both may be operated in combination. This can be realized by separately providing the color reduction rate data for dither processing and FRC processing. Further, the color reduction rate data is not limited to transfer from the CPU, but may be realized by terminal setting. Furthermore, as shown in FIG. 35, CPU transfer and terminal setting may be switched and used.

  Next, a third embodiment of the present invention will be described with reference to FIGS. In the first and second embodiments of the present invention, a display signal is transferred from a CPU, and a frame memory is built in a display device drive circuit. This configuration is often used for small displays centering on mobile phones. ing. On the other hand, the third embodiment of the present invention described below is a type in which a display signal is transferred from a dedicated graphic controller and the display device drive circuit does not have a frame memory. Often used in

  FIG. 36 is a block diagram showing a configuration of a display device driving circuit according to the third embodiment of the display device of the present invention, and FIG. 37 is a timing chart of input signals according to the third embodiment of the present invention. In FIG. 36, reference numeral 3601 denotes a data line driving unit, 3602 denotes a graphic controller, 3603 denotes a dither processing unit, and 3604 denotes a gradation voltage selector. The gradation voltage generation unit 107 is the same as the gradation voltage generation unit in the first and second embodiments of the present invention.

  The graphic controller 3602 outputs a display synchronization signal group and gradation data shown in FIG. 37 as a so-called raster scan display signal group. The dither processing unit 3603 receives these display synchronization signal group, gradation data, and color reduction rate data, performs color reduction processing on the gradation data using dither processing, and outputs the data as color reduction gradation data. Here, several means such as a method of giving the color reduction rate data from an external CPU, a method of setting a terminal, or a method of setting a manual switch provided in the apparatus can be considered.

  FIG. 38 is a block diagram showing the configuration of the dither processing unit according to the third embodiment of the present invention. FIG. 39 is a block diagram showing the configuration of the dither signal generator according to the third embodiment of the present invention. In FIG. 38, reference numeral 3801 is a dither signal generator, and 802 to 804 are data converters equivalent to those in the first embodiment of the present invention. As shown in FIG. 39, the dither signal generation unit 3801 includes a vertical position counter 3901, a horizontal position counter 3902, and a decoder 3903. The vertical position counter 3901 is cleared during the “high” period of the frame signal and counts up in synchronization with the rising edge of the valid period signal. The horizontal position counter 3902 is cleared during the “high” period of the line signal, and counts up in synchronization with the rising edge of the dot clock while the valid period signal is “high”.

  By this operation, the output of each counter becomes equivalent to the vertical address and horizontal address shown in FIG. Further, the next stage decoder 3903 generates the four types of dither signals shown in FIG. 9 from the input count value. Furthermore, since the data conversion unit is equivalent to that of the first embodiment of the present invention, the dither processing unit 3603 outputs subtractive color gradation data equivalent to that of the first embodiment of the present invention. Since the gradation voltage generation unit 107 has the same configuration and the same operation as those of the first embodiment of the present invention, the description thereof is omitted.

  FIG. 40 is a block diagram showing the configuration of the gradation voltage selector according to the third embodiment of the present invention. FIG. 41 is a timing chart showing the operation of the gradation voltage selector according to the third embodiment of the present invention. In FIG. 40, a gradation voltage selector 3604 is a block that takes in and synchronizes subtractive gradation data transferred for each pixel of RGB, and selects and outputs one level from a plurality of gradation voltages according to gradation data. It is. As shown in FIG. 40, the latch includes a fetch latch unit 4001, a synchronization latch unit 4002, and a selector 4003.

  The capture latch unit 4001 is cleared at the fall of the line signal, and sequentially captures one row of the subtractive gradation data in synchronism with the fall of the dot clock while the valid period signal is “high”. The synchronization latch unit 4002 captures the color-reduced gradation data output from the capture latch unit 4001 in synchronization with the rising edge of the line signal, and outputs it to the selector 4003. The selector 4003 selects one level from a plurality of gradation voltages according to the subtractive gradation data and the AC signal. The operation of the selector 4003 is the same as that of the selector 1902 according to the first embodiment of the present invention. FIG. 41 shows the operation timing of the gradation voltage selector 3604.

  In the third embodiment of the present invention described above, as in the first embodiment of the present invention, the number of colors displayed on the display is switched in accordance with the color reduction rate data, and the number of colors to be displayed is adjusted to be unnecessary. With the function of stopping the drive circuit, low power consumption can be achieved. In addition, it is possible to switch between a high image quality mode with little color reduction and a low power consumption mode with much color reduction, improving usability. Further, the present invention can be applied to a configuration in which a display device is connected to a graphic controller and a raster scan signal is input to the display device. In the third embodiment of the present invention, the dither process is taken as an example. However, the present invention is not limited to this. Needless to say, the dither process can also be realized by using the FRC process.

  Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the fourth embodiment of the present invention, the display device driving circuit described in the first to third embodiments of the present invention is applied to a display device. FIGS. 42 and 43 show a frame memory in the display device driving circuit. FIG. 44 shows a configuration in which the display device drive circuit does not have a frame memory.

  That is, FIG. 42 is a block diagram showing the configuration of the display device according to the fourth embodiment of the present invention, FIG. 43 is a block diagram showing the configuration of the display device according to the fourth embodiment of the present invention, and FIG. It is a block diagram which shows the structure of the display apparatus which concerns on 4th Example.

  In FIG. 42, reference numeral 4201 denotes a display device, which is roughly composed of a data line driving unit 4202, a scanning line driving unit 4203, a power supply unit 4204, and a pixel unit 109. The data line driving unit 4202 is substantially the same as the data line driving unit 101 of the first embodiment of the present invention except that a data register 4205 is provided. The data register 4205 is a part that stores various drive parameters transferred from the CPU, and stores the parameter information in each block.

  Examples of the above parameters include the number of drive lines, the frame frequency, and the like, and the color reduction rate data, which is a feature of the present invention, is included in this. As a transfer method from the CPU, for example, if an unused bit (for example, D17) in the addressing cycle shown in FIG. 4 is used as an identification bit of the frame memory and the data register, the transfer method shown in FIG. 3 is used. The frame memory and the data register can be shared.

  The scanning line driving unit 4203 is a block for driving the scanning lines of the pixel unit 109, and the output signal waveform is the same as the scanning voltage shown in FIG. In addition to outputting the counter voltage shown in FIG. 23, the power supply unit 4204 generates a power supply voltage necessary for the display device of the present invention and outputs it to each block. This operation can be realized by means for boosting the system power supplied from the outside and means for adjusting the boosted voltage. Note that control information such as voltage adjustment is transferred from the data register 4205. Since the pixel portion 109 has the same configuration and the same operation as those of the first embodiment of the present invention, description thereof will be omitted.

  As described above, FIG. 43 shows a configuration in which an FRC processing unit is added to the data line driving circuit of the display device, and FIG. 44 shows a configuration in which the data line driving circuit does not have a frame memory. Since these operations are obtained by adding a scanning line driving circuit and a power supply unit to the data line driving circuit shown in FIGS. 42 and 36, detailed description thereof will be omitted.

  In the fourth embodiment of the present invention described above, as in the first to third embodiments of the present invention, the number of colors to be displayed on the display is switched according to the color reduction rate data, and the number of colors to be displayed is adjusted. Since it has a function of stopping an unnecessary drive circuit, the power consumption of the display device can be reduced. Further, it is possible to switch between a high image quality mode with a small number of color reductions and a low power consumption mode with a large number of color reductions, which improves the usability of the display device.

  The present invention is not limited to the configurations described in the claims and the configurations described in the above embodiments, and various modifications can be made without departing from the technical idea of the present invention. Needless to say.

1 is a block diagram illustrating a display device driving circuit according to a first embodiment of a display device according to the present invention; It is explanatory drawing of the interface input signal which concerns on 1st Example of this invention. It is a timing chart which shows the operation | movement of the interface input signal which concerns on 1st Example of this invention. It is explanatory drawing of the interface input signal which concerns on 1st Example of this invention. It is explanatory drawing of the interface input signal which concerns on 1st Example of this invention. It is explanatory drawing of the color reduction rate data which concern on 1st Example of this invention. It is principle explanatory drawing of the dithering system based on 1st Example of this invention. It is a block diagram which shows the structure of the dither processing part which concerns on 1st Example of this invention. It is operation | movement explanatory drawing of the dither signal generation part which concerns on 1st Example of this invention. It is operation | movement explanatory drawing of the dither signal generation part which concerns on 1st Example of this invention. It is a block diagram which shows the structure of the data converter which concerns on 1st Example of this invention. It is operation | movement explanatory drawing of the dither signal selector which concerns on 1st Example of this invention. It is operation | movement explanatory drawing of the bit operation part A which concerns on 1st Example of this invention. It is operation | movement explanatory drawing of the bit operation part B which concerns on 1st Example of this invention. It is operation | movement explanatory drawing of the dither processing part which concerns on 1st Example of this invention. It is operation | movement explanatory drawing of the dither processing part which concerns on 1st Example of this invention. FIG. 3 is a circuit diagram illustrating a configuration of a gradation voltage generation unit according to the first embodiment of the present invention. It is operation | movement explanatory drawing of the gradation voltage generation part which concerns on 1st Example of this invention. FIG. 3 is a block diagram showing a configuration of a gradation voltage selector according to the first embodiment of the present invention. 3 is a timing chart for explaining the operation of the gradation voltage selector according to the first embodiment of the present invention. It is operation | movement explanatory drawing of the selector which concerns on 1st Example of this invention. FIG. 3 is an equivalent circuit diagram illustrating a configuration of a pixel unit according to the first example of the present invention. 3 is a timing chart showing the operation of the peripheral circuit according to the first example of the present invention. It is a block diagram which shows the structure of the drive circuit for display apparatuses which concerns on 2nd Example of the display apparatus by this invention. It is principle explanatory drawing of the FRC system which concerns on 2nd Example of this invention. It is explanatory drawing of the color reduction rate data which concern on 2nd Example of this invention. It is a block diagram which shows the structure of the FRC process part which concerns on 2nd Example of this invention. It is a block diagram which shows the structure of the FRC signal generation part which concerns on 2nd Example of this invention. It is a timing chart which shows operation | movement of the FRC signal generation part which concerns on 2nd Example of this invention. It is operation | movement explanatory drawing of the FRC signal generation part which concerns on 2nd Example of this invention. It is a block diagram which shows the structure of the data converter which concerns on 2nd Example of this invention. It is operation | movement explanatory drawing of the bit operation part A which concerns on 2nd Example of this invention. It is operation | movement explanatory drawing of the bit operation part B which concerns on 2nd Example of this invention. It is a block diagram which shows the structure of the drive circuit for display apparatuses which concerns on 2nd Example of this invention. It is a block diagram which shows the structure of the drive circuit for display apparatuses which concerns on 2nd Example of this invention. It is a block diagram which shows the structure of the drive circuit for display apparatuses which concerns on 3rd Example of the display apparatus of this invention. It is a timing chart of the input signal which concerns on 3rd Example of this invention. It is a block diagram which shows the structure of the dither processing part which concerns on 3rd Example of this invention. It is a block diagram which shows the structure of the dither signal generation part which concerns on 3rd Example of this invention. It is a block diagram which shows the structure of the gradation voltage selector which concerns on 3rd Example of this invention. It is a timing chart which shows the operation | movement of the gradation voltage selector which concerns on 3rd Example of this invention. It is a block diagram which shows the structure of the display apparatus which concerns on 4th Example of this invention. It is a block diagram which shows the structure of the display apparatus which concerns on 4th Example of this invention. It is a block diagram which shows the structure of the display apparatus which concerns on 4th Example of this invention.

Explanation of symbols

101 Data line driving unit 102 CPU
103 interface 104 dither processing unit 105 frame memory 106 timing generation unit 107 grayscale voltage generation unit 108 grayscale voltage selector 109 pixel unit 2402 FRC processing unit 3602 graphic controller

Claims (6)

In a display device driving circuit that outputs a gradation voltage corresponding to gradation data from the outside to a pixel portion,
A generation circuit for generating a plurality of levels of gradation voltages from a reference voltage;
A selector for selecting a gradation voltage at a level corresponding to the gradation data from the plurality of gradation voltages;
The gradation data includes multiple bits for each color of RGB,
The generation circuit controls the output number of gradation voltages at each level according to data indicating a color reduction mode from the outside,
The generation circuit outputs a plurality of gradation voltages including the highest gradation voltage and the lowest level when color reduction is not performed.
The generation circuit outputs the highest level gradation voltage and the lowest level gradation voltage among the plurality of gradation voltages when the color is reduced according to the data indicating the external color reduction mode, and performs color reduction. A drive circuit for a display device, wherein output of a gray scale voltage at a level unnecessary for display is stopped. The generation circuit includes a resistor that divides the reference voltage, and an operation that buffers the divided voltage.
2. The display device according to claim 1, wherein the generation circuit stops output of a gradation voltage at a level that is unnecessary for display due to the color reduction by stopping power supplied to the operational amplifier. Drive circuit. The plurality of levels of gradation voltages are 64 levels of gradation voltages V0 to V63,
The highest level gradation voltage is V63,
The display device driving circuit according to claim 1, wherein the lowest level gradation voltage is V0. In a display device driving circuit that outputs a gradation voltage corresponding to gradation data from the outside to the pixel portion,
An interface for inputting gradation data given from the outside;
A memory for storing the gradation data;
A timing generation circuit for generating a display synchronization signal based on the control data given from the outside;
A generation circuit for generating a plurality of levels of gradation voltages from a reference voltage;
A gradation voltage having a level corresponding to gradation data read from the memory is selected from the plurality of gradation voltages generated by the generation circuit, and the selected gradation voltage is selected according to the display synchronization signal. A selector that outputs to the pixel portion,
The gradation data includes multiple bits for each color of RGB,
The generation circuit controls the number of gradation voltages output at each level according to data indicating color reduction from the outside,
The generation circuit outputs a plurality of gradation voltages including the highest gradation voltage and the lowest level when color reduction is not performed.
The generation circuit outputs the highest level gradation voltage and the lowest level gradation voltage among the multiple levels of gradation voltage in accordance with the data indicating the color reduction from the outside, and displays the result by color reduction. The display device driving circuit is characterized in that the output of the grayscale voltage at a level which is unnecessary for the display device is stopped. In a display device driving circuit that outputs a gradation voltage corresponding to gradation data from the outside to a pixel portion,
A generation circuit for generating a plurality of levels of gradation voltages from a reference voltage;
A selector for selecting a gradation voltage at a level corresponding to the gradation data from the plurality of gradation voltages;
The display device driving circuit has a first display mode and a second display mode having a smaller number of colors than the first display mode,
The gradation data includes multiple bits for each color of RGB,
The generation circuit includes a resistor that divides the reference voltage and an operational amplifier that buffers the divided voltage.
The generation circuit outputs a plurality of levels of gradation voltages including a highest level gradation voltage and a lowest level gradation voltage in the first display mode,
In the second display mode, the generation circuit outputs the highest gradation voltage and the lowest gradation voltage among the plurality of gradation voltages, and further supplies the gradation voltage to the operational amplifier. A drive circuit for a display device, characterized by stopping output of a gradation voltage at a level that is unnecessary for display due to color reduction by stopping power. In a display device driving circuit that outputs a gradation voltage corresponding to gradation data from the outside to the pixel portion,
A generation circuit for generating 64 levels of gradation voltages from V0 to V63 from a reference voltage;
A selector for selecting a gradation voltage of a level corresponding to the gradation data from the 64 levels of gradation voltages;
The display device driving circuit has a first display mode and a second display mode having a smaller number of colors than the first display mode.
The gradation data includes 6 bits for each color of RGB,
The generating circuit outputs gradation voltages of 64 levels from V0 to V63 in the first mode.
The generation circuit outputs a gradation voltage of VO and a gradation voltage of V63 in the combination of the second mode, and at least one level other than the gradation voltage of VO and the gradation voltage of V63. A drive circuit for a display device, wherein output of the regulated voltage is stopped.

Images