JP2007240632A - Source driver, electro-optical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a source driver capable of reducing a circuit scale by improving layout efficiency and improving an operability just after power-on, and to provide an electro-optical device and an electronic apparatus. <P>SOLUTION: The source driver 30 includes a memory access circuit for reading out first and second setting information of a setting information memory, a first control register to which a first supply voltage in a first supply voltage range is supplied, a second control register to which a second supply voltage in a second supply voltage range is supplied, a display memory to which the first supply voltage is supplied and in which gray scale data and the second setting information are stored, and a driving part which drives a source line on the basis of gray scale data from the display memory. The second setting information is stored in the display memory, and then is stored in the second control register on condition that the second supply voltage can be obtained by raising the first supply voltage. The driving part supplies a driving voltage corresponding to the second setting information to the source line at a display timing corresponding to the first setting information. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a source driver, an electro-optical device, and an electronic apparatus.

  By mounting the liquid crystal system on an electronic device such as a mobile phone, the electronic device can be reduced in size. Further, by further finely controlling the drive by the drive circuit (source driver, gate driver) that drives the liquid crystal panel that constitutes the liquid crystal system, further reduction in power consumption can be realized.

  A control register is provided in such a drive circuit. By setting setting information in this control register, driving control corresponding to the setting information is enabled, and finer driving control can be realized. For example, there is a control register for performing display drive timing, setting of a region to be displayed, selection of a data line to be driven, selection of a shift direction of supplied display data, and the like.

  For example, in Patent Document 1, setting information is stored in advance in an EEPROM (Electrically Erasable Programmable Read Only Memory) provided outside the driving circuit, and the setting information is read from the EEPROM at power-on or initialization. A technique for setting a control register is disclosed. In this case, the drive circuit generates a control signal corresponding to the setting information and performs drive control based on the control signal.

By adopting such a configuration, the drive circuit can be mass-produced as a general-purpose product, and on the other hand, optimal control can be performed for the environment of the user who uses the drive circuit.
JP 2005-38346 A

  By the way, the drive circuit includes a logic block, a display memory block, a drive block, and the like, and each block is supplied with power in different power supply voltage ranges depending on the number of elements and functions to be realized. For example, in a logic block, a power supply voltage of 3 volts is supplied to a gate array that increases the degree of integration and realizes high speed. The display memory block is also supplied with a 3 volt power supply voltage having a high degree of integration. On the other hand, the drive block is supplied with a 5-volt power supply voltage required for driving the source lines of the liquid crystal display panel.

  As described above, the drive circuit generally includes a plurality of blocks to which different types of power supply voltages are supplied. The high power supply voltage is generated by a booster circuit provided inside or outside the drive circuit. Therefore, the control registers of the drive circuit are also prepared with different power supply voltage ranges.

  Here, it is conceivable to unify the control register to one of the power supply system registers. For example, if the control registers are unified as a 5-volt system register, the circuit scale of the drive circuit increases as the number of registers increases. On the other hand, when the control register is unified as a 3 volt system register, it is difficult to wire a control signal for controlling a 5 volt system circuit using the setting information of the 3 volt system register, and the layout efficiency is lowered. In addition, a large number of level shifters for converting the voltage level are required, which also increases the circuit scale. Therefore, it is desirable to prepare a control register for each different power supply voltage range.

  However, paying attention to the 5 volt system power supply voltage, since the booster circuit is generated using a low voltage power supply such as 3 volts immediately after the power is turned on, the use start time of the 5 volt system circuit is delayed. Therefore, there is a problem that it takes time to write the setting information in the control register of 5 volts system. This means that for the user who controls the drive circuit, the initialization operation time immediately after power-on of the electronic device incorporating the drive circuit becomes long, and the usability deteriorates.

  The present invention has been made in view of the technical problems as described above. The object of the present invention is to reduce the circuit scale by improving the layout efficiency and improve the usability immediately after the power is turned on. A driver, an electro-optical device, and an electronic apparatus are provided.

In order to solve the above problems, the present invention
A source driver for driving a source line of an electro-optical device,
A memory access circuit for reading out the first and second setting information stored in the setting information memory from the setting information memory;
A first control register to which a first power supply voltage in a first power supply voltage range based on a reference potential is supplied;
A second control register to which a second power supply voltage in a second power supply voltage range based on the reference potential wider than the first power supply voltage range is supplied;
A display memory that is supplied with the first power supply voltage and stores gradation data and the second setting information;
A drive unit for driving the source line based on the gradation data read from the display memory;
The second setting information read by the memory access circuit is temporarily stored in the display memory, and then the first power supply voltage is boosted to obtain the second power supply voltage. Reading the second setting information from the display memory and storing it in the second control register;
The drive unit is
The present invention relates to a source driver that supplies a drive voltage generated based on the second control register to the source line at a display timing corresponding to setting information set in the first control register.

  In the present invention, a control register is provided for each type of power supply voltage by providing a first control register to which a first power supply voltage is supplied and a second control register to which a second power supply voltage is supplied. It has been. Therefore, the circuit scale can be reduced as compared with the case where a control register for controlling the source driver is provided as a control register to which a higher power supply voltage is supplied. On the other hand, compared to the case where the control register for controlling the source driver is provided as a control register to which a lower power supply voltage is supplied, the wiring of the control signal for controlling the circuit to which the second power supply voltage is supplied is reduced. It is possible to avoid a situation where layout becomes difficult and layout efficiency is lowered, and a large number of level shifters for converting the voltage level are required and the circuit scale is increased.

  Furthermore, since the second setting information is temporarily stored in the display memory of the source driver, the time for reading data from the setting information memory can be shortened. Therefore, it is possible for the user to shorten the initialization operation time immediately after the power is turned on and to improve usability.

In the source driver according to the present invention,
A serial transfer circuit that reads out the second setting information from the display memory and transfers it to the second control register on the condition that the first power supply voltage is boosted to obtain the second power supply voltage. When,
A level shifter that converts a voltage level of the signal of the second setting information transferred by the serial transfer circuit.

  According to the present invention, in order to set the second setting information in the second control register, a large number of level shifters for converting the voltage level of the signal of each bit of the setting information becomes unnecessary, and the number of level shifters is minimized. To the limit.

In the source driver according to the present invention,
A storage area in which the second setting information is stored in the display memory,
The display memory may be shared with a storage area for storing the gradation data.

  According to the present invention, setting information set in the second control register can be temporarily stored without increasing the capacity of the display memory.

In the source driver according to the present invention,
A storage area in which the second setting information is stored in the display memory,
The display memory may be provided separately from a storage area in which the gradation data is stored.

  According to the present invention, the second control is performed not only immediately after the power is turned on, in which the gradation data is not stored in the display memory, but also immediately after the boosting operation is resumed even during the display period based on the gradation data. Even when the register cannot be used, the second setting information can be temporarily stored. As a result, the setting information reading time can be shortened.

In the source driver according to the present invention,
A booster circuit for generating the second power supply voltage obtained by boosting the voltage level of the first power supply voltage;
A boosted voltage monitoring circuit for monitoring a level of a second power supply voltage boosted by the boosting circuit;
When the boosted voltage monitoring circuit detects that the second power supply voltage has reached a predetermined voltage level, reading of the second setting information from the display memory may be started.

In the source driver according to the present invention,
A reference voltage generating circuit for generating a plurality of reference voltages within the second power supply voltage range;
A voltage selection circuit that selects a reference voltage corresponding to gradation data from the plurality of reference voltages;
The drive unit is
The source line can be driven using the reference voltage selected by the voltage selection circuit as the drive voltage.

In the source driver according to the present invention,
The reference voltage generating circuit is
At least one reference voltage among the plurality of reference voltages may be changed based on the second setting information.

In the source driver according to the present invention,
The setting information memory is
It may be a non-volatile memory.

In the source driver according to the present invention,
The setting information memory is
It may be an EEPROM (Electrically Erasable Programmable Read Only Memory).

In the source driver according to the present invention,
The setting information memory may be included.

The present invention also provides
Multiple gate lines,
Multiple source lines,
A plurality of pixels each connected to each gate line of the plurality of gate lines and each source line of the plurality of source lines;
A gate driver that scans the plurality of gate lines;
The present invention relates to an electro-optical device including any one of the source drivers described above that drives the plurality of source lines.

  According to the present invention, it is possible to provide an electro-optical device including a source driver that reduces the circuit scale by improving layout efficiency and improves usability immediately after power-on.

The present invention also provides
The present invention relates to an electronic device including any of the source drivers described above.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

  According to any one of the above-described inventions, it is possible to provide an electronic device that realizes cost reduction by improving the layout efficiency and reducing the circuit scale and improving the usability immediately after the power is turned on.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. FIG. 1 shows an outline of the configuration of an active matrix liquid crystal display device according to this embodiment. In FIG. 1, a liquid crystal display device using an active matrix liquid crystal display panel as an electro-optical device will be described. However, a liquid crystal display device using a passive matrix liquid crystal display panel may be used. Further, the electro-optical device according to the present invention is not limited to the liquid crystal display panel.

  The liquid crystal display device 10 includes a liquid crystal display panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The liquid crystal display panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a source line arranged in the X direction and extending in the Y direction, respectively. (Data lines) SL1 to SLN (N is an integer of 2 or more) are arranged. The pixel region corresponds to the intersection position of the gate line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the source line SLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region.

  The gate of the TFT 22mn is connected to the gate line GLn. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal (electro-optical material in a broad sense) is sealed between the pixel electrode 26 mn and a counter electrode 28 mn facing the pixel electrode 26 mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24 mn. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage Vcom is supplied to the counter electrode 28mn.

  Such a liquid crystal display panel 20 includes, for example, a first substrate on which a pixel electrode and a TFT are formed and a second substrate on which a counter electrode is formed, and a liquid crystal as an electro-optical material between the two substrates. It is formed by enclosing.

  The liquid crystal display device 10 includes a source driver (data driver) 30. The source driver 30 drives the source lines SL1 to SLN of the liquid crystal display panel 20 based on the gradation data (display data).

  The liquid crystal display device 10 can include a gate driver (scan driver) 32. The gate driver 32 sequentially drives (scans) the gate lines GL1 to GLM of the liquid crystal display panel 20 within one vertical scanning period.

  The liquid crystal display device 10 includes a power supply circuit 100. The power supply circuit 100 generates voltages necessary for driving the source lines and supplies them to the source driver 30. The power supply circuit 100 generates a voltage necessary for scanning the gate line and supplies it to the gate driver 32.

  Furthermore, the power supply circuit 100 includes a common electrode voltage supply circuit, and the common electrode voltage supply circuit generates the common electrode voltage Vcom. That is, the power supply circuit 100 generates the common electrode voltage Vcom that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML in accordance with the timing of the polarity inversion signal POL generated by the source driver 30. Output to the counter electrode.

  The liquid crystal display device 10 can include a display controller 38. The display controller 38 controls the source driver 30, the gate driver 32, and the power supply circuit 100 in accordance with contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). For example, the display controller 38 performs operation mode setting, polarity inversion drive setting, polarity inversion timing setting, supply of internally generated vertical synchronization signal and horizontal synchronization signal to the source driver 30 and the gate driver 32, and the like. . The display controller 38 or the host can be said to be a processing unit in a broad sense.

  The liquid crystal display device 10 includes an EEPROM (Electrically Erasable Programmable Read Only Memory) 200 (setting information memory in a broad sense) that can electrically rewrite data as a nonvolatile memory. The EEPROM 200 stores setting information for controlling the source driver 30. The source driver 30 takes in setting information from the EEPROM 200 during power-on, initialization, or display period, and sets the setting information in a built-in control register, thereby driving control based on a control signal corresponding to the setting information. I do. Such a source driver 30 may incorporate the EEPROM 200.

  In FIG. 1, the liquid crystal display device 10 is configured to include the power supply circuit 100 or the display controller 38, but at least one of these may be provided outside the liquid crystal display device 10. Good. Alternatively, the liquid crystal display device 10 may be configured to include a host.

  The source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 100 may be formed on the liquid crystal display panel 20. For example, in FIG. 2, a source driver 30 and a gate driver 32 are formed on the liquid crystal display panel 20. As described above, the liquid crystal display panel 20 includes a plurality of gate lines, a plurality of source lines, a pixel (pixel electrode) specified by one of the plurality of gate lines and one of the plurality of source lines, and a plurality of gate lines. And a source driver for driving a plurality of source lines. A plurality of pixels are formed in the pixel formation region 80 of the liquid crystal display panel 20.

2. Gate Driver FIG. 3 shows a configuration example of the gate driver 32 of FIG.

  The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

  The shift register 40 includes a plurality of flip-flops provided corresponding to the gate lines and sequentially connected. When the shift register 40 holds the start pulse signal STV in the flip-flop in synchronization with the clock signal CPV, the shift register 40 sequentially shifts the start pulse signal STV to the adjacent flip-flop in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

  The level shifter 42 shifts the voltage level from the shift register 40 to a voltage level corresponding to the liquid crystal element of the liquid crystal display panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output buffer 44 buffers the scanning voltage shifted by the level shifter 42 and outputs it to the gate line to drive the gate line.

3. Source Driver FIG. 4 shows a block diagram of a configuration example of the source driver 30 of FIG.

  The source driver 30 includes a data latch 120, a line latch 122, a display memory 130, a level shifter 132, a reference voltage generation circuit 134, a DAC (Digital-to-Analog Converter) (voltage selection circuit in a broad sense) 136, and a drive unit 138. .

  Further, the source driver 30 includes an EEPROM data reading circuit (memory access circuit) 150, a control register (first control register) 152, and a control circuit 160. The control circuit 160 includes a display timing control unit 162 and a display memory control unit 164.

  The source driver 30 further includes a booster circuit 170, a boosted voltage monitoring circuit 172, a gamma correction data register (second control register) 174, a level shifter 176, and a serial transfer circuit 178.

  Each circuit block of the source driver 30 is included in a low voltage block or a high voltage block.

  FIG. 5 is an explanatory diagram of power supply voltages supplied to the low voltage block and the high voltage block in the present embodiment.

  The low voltage block is supplied with a low voltage power supply voltage VDDL in a voltage range of 3 volts (first power supply voltage range) with respect to the ground power supply potential VSS (reference potential) of the source driver 30. That is, an LV (Low Voltage) power supply voltage is supplied to the low voltage block, and the transistors constituting the circuit of the low voltage block have a transistor structure manufactured by a low breakdown voltage manufacturing process.

  The high voltage block is supplied with a high voltage power supply voltage VDDH in a voltage range (second power supply voltage range) of 5 volts with respect to the ground power supply potential VSS of the source driver 30. That is, a MV (Middle Voltage) power supply voltage is supplied to the high voltage block, and the transistors constituting the circuit of the high voltage block have a transistor structure manufactured by a medium breakdown voltage (or high breakdown voltage) manufacturing process. .

  In FIG. 4, the portion surrounded by the wavy line is the high voltage block. The high voltage block includes a level shifter 132, a reference voltage generation circuit 134, a DAC 136, a drive unit 138, a booster circuit 170, a boosted voltage monitoring circuit 172, a gamma correction data register 174, and a level shifter 176. On the other hand, the low voltage block includes a data latch 120, a line latch 122, a display memory 130, an EEPROM data reading circuit 150, a control register 152, and a control circuit 160. In the high voltage block, since the voltage necessary for the drive control of the source line performed by the drive unit 138 is the MV system power supply voltage, the blocks necessary for the control are collected.

  Thus, by providing a control register in each block of the low voltage block and the high voltage block, the wiring straddling the low voltage block and the high voltage block can be greatly reduced, and the layout efficiency can be increased. The area can be reduced.

  In the present embodiment, the booster circuit 170 boosts the power supply voltage of 3 volts to generate the power supply voltage of 5 volts. The voltage boosted by the booster circuit 170 is supplied as the power supply voltage on the high potential side of each part of the high voltage block.

  Returning to FIG. 4, the operation of each part of the source driver 30 will be described.

  The data latch 120 of the source driver 30 receives the gradation data from the display controller 38. The display controller 38 supplies gradation data in units of dots (or pixels) constituting one pixel to the source driver 30 serially, and is sequentially taken into the data latch 120.

  The line latch 122 latches the gradation data fetched by the data latch 120 based on the horizontal synchronization signal Hsync.

  In the display memory 130, each memory cell includes a plurality of memory cells that hold data of each bit of grayscale data. Each memory cell is specified by a bit line and a word line, and data read from the memory cell is output via a display line. The display memory 130 has a storage capacity for holding gradation data of pixels for at least one vertical scan, and a partial storage area of the display memory 130 has a control register of the source driver 30 as described later. Setting information to be set is temporarily stored.

  The level shifter 132 converts the voltage level of each bit signal of the read data from the display memory 130 from the LV system to the MV system. That is, when the bit signal is 3 volts, the voltage level of the signal is converted to 5 volts.

  In the reference voltage generation circuit 134, each reference voltage generates a plurality of reference voltages corresponding to each gradation data. More specifically, the reference voltage generation circuit 134 generates a plurality of types of reference voltages obtained by resistance-dividing the high-voltage power supply voltage VDDH with the ground power supply potential VSS as a reference, and supplies the generated voltage to the DAC 136.

  The DAC 136 outputs a drive voltage (grayscale voltage) corresponding to the grayscale data from the level shifter 132 for each source line from among a plurality of reference voltages in which each reference voltage corresponds to the grayscale data. More specifically, the DAC 136 decodes gradation data for one dot from the level shifter 132 and selects one of a plurality of reference voltages based on the decoding result. The reference voltage selected by the DAC 136 is output to the drive unit 138 as a drive voltage.

  The drive unit 138 has a plurality of data output units, each data output unit being provided corresponding to each source line. Each data output unit of the drive unit 138 drives the source line based on the drive voltage from the DAC 136.

  The EEPROM data reading circuit 150 performs reading control of setting information of the source driver 30 from the EEPROM 200 by an initialization signal RST that becomes active at the time of initialization.

  FIG. 6 shows an outline of the configuration of the EEPROM 200.

  The EEPROM 200 is connected to an address / data division bus and a clock line. The address / data division bus and the clock line are connected to the source driver 30.

  FIG. 7 shows a timing chart of an example of the control of the EEPROM data reading circuit 150.

  The EEPROM data read circuit 150 can set the address data ADD in the EEPROM 200 by outputting the address data ADD to the address / data division bus and outputting one clock pulse to the clock line. The address data ADD is an address on the memory space of the EEPROM 200 in which setting information read by the EEPROM data reading circuit 150 is stored.

  The EEPROM data reading circuit 150 then sequentially supplies a clock to the clock line. In the EEPROM 200, the fetched address data ADD is incremented in synchronization with the clock. Then, storage data (setting information) corresponding to the address data ADD is output to the address / data division bus in synchronization with the clock of the clock line.

  FIG. 8 is an explanatory diagram of setting information stored in the EEPROM 200.

  For example, setting information (setting information for low voltage block, first setting information) set in the control register of the low voltage block is stored in the area starting with the address data ADD1 in the memory space of the EEPROM 200. For example, setting information (high voltage block setting information, second setting information) set in the control register of the high voltage block is stored in an area starting with the address data ADD2 in the memory space of the EEPROM 200.

  When the initialization signal RST becomes active, the EEPROM data reading circuit 150 sequentially reads the low voltage block setting information by designating the address data ADD1, and then designates the address data ADD2 and sequentially sets the high voltage block. Information can be read out. The low-voltage block setting information and the high-voltage block setting information may be stored in the same area. However, when the areas are divided, setting of the setting information reading path in the source driver 30 is performed. Can be simplified.

  In FIG. 4, among the setting information of the source driver 30 read by the EEPROM data reading circuit 150, the setting information (first setting information) of the control register provided in the low voltage block is set in the control register 152 as it is. Of the setting information of the source driver 30 read by the EEPROM data reading circuit 150, the setting information (second setting information) of the control register provided in the high voltage block is temporarily stored in a predetermined area of the display memory 130. To store.

  The control circuit 160 generates a control signal that controls each unit of the source driver 30. In particular, the display timing control unit 162 can generate a display timing based on setting information (first setting information) set in the control register 152, and can also generate a control signal corresponding to the display timing.

  FIG. 9 shows an example of display timing controlled based on setting information set in the control register 152.

  In the present embodiment, as shown in FIG. 9, a vertical synchronization signal Vsync defining one vertical scanning period is generated based on setting information set in the control register 152, and a horizontal synchronization signal Hsync defining one horizontal scanning period is generated. Is done. One vertical scanning period is defined by, for example, a falling edge period of the vertical synchronization signal Vsync. One horizontal scanning period is defined by, for example, a falling edge period of the horizontal synchronization signal Hsync.

That is, based on the setting information, the length of one vertical scanning period T _V is changed. Also based on the setting information, the length of one horizontal scanning period T _H is changed. The display timing control unit 162 can generate a control signal (for example, a latch timing signal of the line latch 122) corresponding to the display timing controlled in this way, and can control each unit of the source driver 30.

  In FIG. 4, the display memory control unit 164 performs control for designating a word line and a bit line for specifying a writing area and a reading area of the display memory 130 based on setting information set in the control register 152. Do. For example, the display memory control unit 164 performs control to specify a word line and a bit line corresponding to the writing area of the display memory 130 specified by the setting information set in the control register 152 and sets from the EEPROM data reading circuit 150. Control to write information (second setting information) or gradation data from the line latch 122 is performed. Alternatively, the display memory control unit 164 performs control to specify a word line and a bit line corresponding to the read area of the display memory 130 specified by the setting information set in the control register 152, and sets the setting information ( Second setting information) or gradation data is read out to a display line in the display memory 130.

  FIG. 10A and FIG. 10B are explanatory diagrams of a storage area for setting information stored in the display memory 130.

  For example, as shown in FIG. 10A, a storage area in which setting information is stored in the display memory 130 may be shared with a gradation data storage area GAR in which gradation data is stored in the display memory 130. In this way, setting information set in the control register of the high voltage block can be temporarily stored without increasing the capacity of the display memory 130.

  Alternatively, as shown in FIG. 10B, a setting information storage area SAR in which setting information is stored in the display memory 130 is provided separately from the gradation data storage area GAR in which gradation data is stored in the display memory 130. It may be done. In this way, not only immediately after the power is turned on, in which the gradation data is not stored in the display memory 130, but also during the display period based on the gradation data, immediately after the boosting operation is resumed, the high voltage block is controlled. Even when the register cannot be used, the setting information set in the control register of the high voltage block can be temporarily stored.

  In FIG. 4, the booster circuit 170 starts the boosting operation to boost the 3 volt power supply voltage to the 5 volt power supply voltage as described above in response to the initialization signal RST. The voltage boosted by the booster circuit 170 is supplied as the power supply voltage on the high potential side of the level shifter 132, the reference voltage generation circuit 134, the gamma correction data register 174, and the level shifter 176. Further, the voltage boosted by the booster circuit 170 is also supplied to the boosted voltage monitoring circuit 172.

  The boosted voltage monitoring circuit 172 can detect whether or not the voltage boosted by the boosting circuit 170 has reached a predetermined reference voltage Vref, and can output the detection result signal to the serial transfer circuit 178.

  FIG. 11 is a block diagram showing a configuration example of the booster circuit 170 and the boosted voltage monitoring circuit 172 shown in FIG.

  The step-up circuit 170 includes a step-up clock generation circuit 190, a charge pump circuit 192, and a regulator 194. The boosted voltage monitoring circuit 172 includes a comparator 196.

  The boost clock generation circuit 190 generates a boost clock when detecting the rising edge or the falling edge of the initialization signal RST.

  The charge pump circuit 192 boosts the low-voltage power supply voltage VDDL with reference to the ground power supply potential VSS by a charge pump operation synchronized with the boost clock. The regulator 194 adjusts the potential of the voltage boosted by the charge pump circuit 192 and outputs the adjusted voltage as the high-voltage power supply voltage VDDH. The configurations of the charge pump circuit 192 and the regulator 194 that perform such a charge pump operation are well-known and will not be described.

  The comparator 196 of the boosted voltage monitoring circuit 172 compares the voltage boosted by the charge pump circuit 192 with the reference voltage Vref. The comparator 196 changes the detection result signal when the voltage boosted by the charge pump circuit 192 exceeds the reference voltage Vref.

  Returning to FIG. 4, the description will be continued.

  In FIG. 4, the serial transfer circuit 178 transfers the setting information (second setting information) read from the display memory 130 to the level shifter 176 in units of 1 bit based on the detection result signal from the boost voltage monitoring circuit 172. Control. That is, the setting information is read from the display memory 130 and transferred to the gamma correction data register 174 on condition that the low-voltage power supply voltage VDDL is boosted to obtain the high-voltage power supply voltage VDDH.

  The serial transfer circuit 178 only needs to be able to transfer to the level shifter 176 in units of bits smaller than the number of bits of setting information read from the display memory 130.

  The level shifter 176 converts the voltage level of one bit signal transferred by the serial transfer circuit 178 from the LV system to the MV system in the same manner as the level shifter 132. That is, when the bit signal is 3 volts, the voltage level of the signal is converted to 5 volts. Each bit of the setting information whose voltage level is converted by the level shifter 176 is sequentially set in the gamma correction data register 174.

  In the gamma correction data register 174, data for changing the level of the reference voltage generated in the reference voltage generation circuit 134 is set. Therefore, the reference voltage generated by the reference voltage generation circuit 134 can be changed based on the setting information transferred by the serial transfer circuit 178, and so-called gamma correction can be realized.

  FIG. 12 is an explanatory diagram of the gamma characteristic.

  In FIG. 12, the horizontal axis represents a plurality of reference voltages generated by the reference voltage generation circuit 134, and the vertical axis represents the transmittance when the reference voltage is applied to the pixel. Therefore, the transmittance of the pixel can be changed by changing the voltage level of the reference voltage. Therefore, even with the same gradation data, it is possible to change the method of changing the transmittance by changing the voltage level of the reference voltage selected from a plurality of reference voltages.

  Therefore, the drive unit 138 in FIG. 4 can drive the source line based on the gradation data read from the display memory 130, but the drive timing is set information (first information) set in the control register 152. 1), and the drive voltage is generated based on the setting information (second setting information) set in the gamma correction data register 174.

  FIG. 13 shows a circuit diagram of a configuration example of the reference voltage generation circuit, the DAC, and the driving unit in FIG.

  FIG. 13 shows only the configuration of the output line OL-1 of the drive unit 138 connected to the source line SL1, but the same applies to the other output lines.

  In the reference voltage generation circuit 134, a resistance circuit is connected between the high-voltage power supply voltage VDDH and the power supply line to which the ground power supply potential VSS is supplied. This resistance circuit has a plurality of resistance division nodes, and the resistance value between the resistance division nodes is changed based on gamma correction data (control information) set in the gamma correction data register 174.

  Then, the reference voltage generation circuit 134 generates a plurality of divided voltages obtained by dividing the voltage of the high-voltage power supply voltage VDDH with the resistance circuit using the ground power supply potential VSS as reference voltages V0 to V63. In the case of polarity inversion driving, since the voltages are not actually symmetric between positive and negative polarities, a positive reference voltage and a negative reference voltage are generated. One of them is shown in FIG.

  The DAC 136-1 can be realized by a ROM decoder circuit. The DAC 136-1 selects any one of the reference voltages V <b> 0 to V <b> 63 based on, for example, 6-bit gradation data corresponding to the source line SL <b> 1 and outputs the selected voltage Vsel to the driving unit 138-1.

  The DAC 136-1 includes an inverting circuit 137-1. The inversion circuit 137-1 inverts each bit of the gradation data based on the polarity inversion signal POL. The DAC 136-1 receives 6-bit gradation data DR10 to DR15 and 6-bit inverted gradation data XDR10 to XDR15. The inverted gradation data XDR10 to XDR15 are obtained by bit-inverting the gradation data DR10 to DR17, respectively. In the DAC 136-1, any one of the multi-level reference voltages V0 to V63 generated by the reference voltage generation circuit 134 is selected based on the gradation data.

  For example, when the polarity inversion signal POL is at the H level, the reference voltage V2 is selected corresponding to “000010” (= 2) of the 6-bit gradation data DR10 to DR15. For example, when the polarity inversion signal POL is at the L level, the reference voltage is selected using the inverted gradation data XDR10 to XDR15 obtained by inverting the gradation data DR10 to DR15. That is, the inverted gradation data XDR10 to XDR15 are “111101” (= 61), and the reference voltage V61 is selected.

  The selection voltage Vsel selected by the DAC 136-1 in this way is supplied to the drive unit 138-1.

  The drive unit 138-1 includes an operational amplifier DRV-1 connected as a voltage follower. The operational amplifier DRV-1 drives the output line OL-1 based on the selection voltage Vsel. Further, as described above, the power supply circuit 100 changes the voltage of the counter electrode in synchronization with the polarity inversion signal POL. In this way, driving is performed with the polarity of the voltage applied to the liquid crystal reversed.

  As described above, the source driver 30 includes the EEPROM data reading circuit (nonvolatile memory access circuit) for reading the first and second setting information stored in the EEPROM (nonvolatile memory) 200 from the nonvolatile memory. ) 150, a control register 152 (first control register) to which a low-voltage power supply voltage VDDL (first power supply voltage in a first power supply voltage range with reference to the reference potential VSS) is supplied, and a high-voltage power supply A gamma correction data register (second control register) 174 to which a power supply voltage VDDH (a second power supply voltage in a second power supply voltage range that is wider than the first power supply voltage range and is based on a reference potential) is supplied; The display memory 130 to which the low-voltage power supply voltage VDDL is supplied and the gradation data and the second setting information are stored is read from the display memory 130 Was based on grayscale data, it may include a driving unit 138 that drives the source line. Then, after the setting information (second setting information) read by the EEPROM data reading circuit 150 is temporarily stored in the display memory 130, the low voltage power supply voltage VDDL is boosted to obtain the high voltage power supply voltage VDDH. Under the condition, the setting information (second setting information) is read from the display memory 130 and stored in the gamma correction data register 174. The drive unit 138 supplies the drive voltage generated based on the gamma correction data register 174 to the source line at a display timing corresponding to the setting information set in the control register 152.

  That is, in this embodiment, the setting information (second setting information) read by the EEPROM data reading circuit 150 is temporarily stored in the display memory 130. Thereafter, on the condition that the voltage boosted by the booster circuit 170 has reached the given reference voltage Vref by the boosted voltage monitoring circuit 172, setting information (second setting information) is displayed from the display memory 130. Are read out and set in the gamma correction data register 174. More specifically, when the boost voltage monitoring circuit 172 detects that the high-voltage power supply voltage VDDH has reached a predetermined voltage level, reading of setting information from the display memory 130 is started.

  Therefore, by providing the control registers in the high voltage block and the low voltage block, the circuit scale can be reduced as compared with the case where all the control registers are provided in the high voltage block. Also, compared to the case where all the control registers are provided in the low voltage block, wiring of control signals for controlling the circuit of the high voltage block becomes difficult, layout efficiency is lowered, and there are many level shifters for converting the voltage level. It is possible to avoid a situation where the circuit scale is increased when necessary.

  Furthermore, in order to set the setting information in the control register of the high voltage block, a large number of level shifters for converting the voltage level of the signal of each bit of the setting information are required, which further increases the circuit scale. In this regard, according to the present embodiment, the number of level shifters can be minimized by serial transfer.

  Compared with the case where the setting information is set in the control register for the control register of the high voltage block, for example, after the boosting operation is started after the power is turned on, the boosted voltage is generated and the setting information is set in the control register. The time for reading the setting information can be shortened.

  FIG. 14 is an explanatory diagram of the boosting operation period of the booster circuit 170.

  The booster circuit 170 requires a period T1 after the boosting operation is started by the initialization signal RST until the target power source of 5 volts is generated. Accordingly, during this period T1, the setting information cannot be written to the control register of the high voltage block. Generally, after this period T1, the setting information is set in the control register of the high voltage block.

  On the other hand, in the present embodiment, since the setting information is once stored in the display memory 130 which is a low voltage block of the source driver 30, the time for reading data from the EEPROM 200 can be shortened. For example, after the boost operation is started by the initialization signal RST, the setting information is read from the EEPROM 200 in a period T2 shorter than the period T1. Then, after the boosted voltage reaches the reference voltage Vref, the setting information is transferred to the control register of the high voltage block. Therefore, for the user, the initialization operation time immediately after the power is turned on can be shortened, and the usability can be improved.

  In addition, the circuit scale of the source driver 30 can be reduced as compared with the case where a save register is provided in the low voltage block in order to fetch the setting information from the EEPROM 200 as soon as possible and set the setting information in the control register of the high voltage block. Such a saving register is used only during the initialization operation, and thus becomes a useless circuit.

  As described above, according to the present embodiment, it is possible to provide a source driver that reduces the circuit scale by improving the layout efficiency and improves the usability immediately after the power is turned on.

4). Electronic Device FIG. 15 is a block diagram showing a configuration example of an electronic device according to this embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device. In FIG. 15, the same parts as those in FIG. 1 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 38 in the YUV format.

  The mobile phone 900 includes the liquid crystal display panel 20. The liquid crystal display panel 20 is driven by a source driver 30 and a gate driver 32. The liquid crystal display panel 20 includes a plurality of source lines, a plurality of gate lines, and a plurality of pixels. The source driver 30 reads the setting information from the EEPROM 200 immediately after the power is turned on, and performs drive control of the source line based on the setting information.

  The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies gradation data in RGB format to the source driver 30.

  The power supply circuit 100 is connected to the source driver 30 and the gate driver 32 and supplies a driving power supply voltage to each driver. The counter electrode voltage Vcom is supplied to the counter electrode of the liquid crystal display panel 20.

  The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. The host 940 can supply the gradation data received via the antenna 960 to the display controller 38 after demodulating the modulation / demodulation unit 950. The display controller 38 causes the source driver 30 and the gate driver 32 to display on the liquid crystal display panel 20 based on the gradation data.

  The host 940 can instruct transmission to another communication apparatus via the antenna 960 after the display data generated by the camera module 910 is modulated by the modem unit 950.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the liquid crystal display panel 20 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the present embodiment, the setting information memory is described as an example of an EEPROM which is a non-volatile memory. However, the setting information memory is not limited to an EEPROM. Further, a volatile memory may be adopted as the setting information memory.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a diagram illustrating an outline of a configuration of an active matrix liquid crystal display device according to an embodiment. The figure which shows the outline | summary of the other structure of the active matrix type liquid crystal display device in this embodiment. The block diagram which shows the structural example of the gate driver of FIG. FIG. 2 is a block diagram of a configuration example of a source driver in FIG. 1. Explanatory drawing of the power supply voltage supplied to the low voltage block and high voltage block in this embodiment. The figure which shows the outline | summary of a structure of EEPROM. The timing diagram of an example of control of an EEPROM data reading circuit. Explanatory drawing of the setting information memorize | stored in EEPROM. The figure which shows an example of the display timing controlled based on the setting information set to the control register. 10A and 10B are explanatory diagrams of a storage area for setting information stored in the display memory. FIG. 5 is a block diagram of a configuration example of a booster circuit and a boosted voltage monitoring circuit in FIG. 4. Explanatory drawing of a gamma characteristic. FIG. 5 is a circuit diagram of a configuration example of a reference voltage generation circuit, a DAC, and a drive unit in FIG. 4. Explanatory drawing of the boosting operation period of a booster circuit. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal display device, 20 liquid crystal display panel, 22mn TFT,
24 mn liquid crystal capacitance, 26 mn pixel electrode, 28 mn counter electrode,
30 source drivers, 32 gate drivers, 38 display controllers,
40 shift register, 42, 132, 176 level shifter,
44 output buffer, 100 power supply circuit, 120 data latch,
122 line latch, 130 display memory, 134 reference voltage generation circuit,
136 DAC, 138 driver, 150 EEPROM data reading circuit,
152 control register, 160 control circuit, 162 display timing control unit,
164 display memory control unit, 170 booster circuit, 172 boosted voltage monitoring circuit,
174 gamma correction data register, 178 serial transfer circuit,
200 EEPROM, SL1 to SLN source line, GL1 to GLM gate line

Claims (13)

A source driver for driving a source line of an electro-optical device,
A memory access circuit for reading out the first and second setting information stored in the setting information memory from the setting information memory;
A first control register to which a first power supply voltage in a first power supply voltage range based on a reference potential is supplied;
A second control register to which a second power supply voltage in a second power supply voltage range based on the reference potential wider than the first power supply voltage range is supplied;
A display memory that is supplied with the first power supply voltage and stores gradation data and the second setting information;
A drive unit for driving the source line based on the gradation data read from the display memory;
The second setting information read by the memory access circuit is temporarily stored in the display memory, and then the first power supply voltage is boosted to obtain the second power supply voltage. Reading the second setting information from the display memory and storing it in the second control register;
The drive unit is
A source driver, wherein a drive voltage generated based on the second control register is supplied to the source line at a display timing corresponding to setting information set in the first control register. In claim 1,
A serial transfer circuit that reads out the second setting information from the display memory and transfers it to the second control register on the condition that the first power supply voltage is boosted to obtain the second power supply voltage. When,
A source driver comprising: a level shifter for converting a voltage level of the signal of the second setting information transferred by the serial transfer circuit. In claim 1 or 2,
A storage area in which the second setting information is stored in the display memory,
A source driver characterized by being shared with a storage area in which the gradation data is stored in the display memory. In claim 1 or 2,
A storage area in which the second setting information is stored in the display memory,
A source driver, wherein the display memory is provided separately from a storage area for storing the gradation data. In any one of Claims 1 thru | or 4,
A booster circuit for generating the second power supply voltage obtained by boosting the voltage level of the first power supply voltage;
A boosted voltage monitoring circuit for monitoring a level of a second power supply voltage boosted by the boosting circuit;
A source driver characterized in that reading of the second setting information from the display memory is started when the boosted voltage monitoring circuit detects that the second power supply voltage has reached a predetermined voltage level. . In any one of Claims 1 thru | or 5,
A reference voltage generating circuit for generating a plurality of reference voltages within the second power supply voltage range;
A voltage selection circuit that selects a reference voltage corresponding to gradation data from the plurality of reference voltages;
The drive unit is
A source driver that drives the source line using the reference voltage selected by the voltage selection circuit as the drive voltage. In claim 6,
The reference voltage generating circuit is
A source driver, wherein at least one reference voltage among a plurality of reference voltages is changed based on the second setting information. In any one of Claims 1 thru | or 7,
The setting information memory is
A source driver characterized by being a non-volatile memory. In claim 8,
The setting information memory is
A source driver characterized by being an EEPROM (Electrically Erasable Programmable Read Only Memory). In any one of Claims 1 thru | or 9,
A source driver comprising the setting information memory. Multiple gate lines,
Multiple source lines,
A plurality of pixels each connected to each gate line of the plurality of gate lines and each source line of the plurality of source lines;
A gate driver that scans the plurality of gate lines;
An electro-optical device, comprising: the source driver according to claim 1 that drives the plurality of source lines.   An electronic device comprising the source driver according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 11.

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