JP2007235578A - Clock generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock generation circuit which can be commonly used in a plurality of different broadcasting systems and achieve simplification and miniaturization of a circuit composition. <P>SOLUTION: While using a voltage controlled oscillator 11 with a wide frequency variable range compared to a conventional voltage controlled crystal oscillator, using frequency dividers 12, 14 which can carry out variable setting of the division value, one set of the voltage controlled oscillator 11 can be commonly used for each broadcasting system by only reading out the respective dividing values of the frequency dividers 12, 14 from a frequency dividing value setting table 16 according to the broadcasting system of terrestrial digital broadcasting signals, and setting it. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock generation circuit that generates a clock signal corresponding to different broadcasting systems such as ISDB-T system and ATSC system DVB-T.

  In recent years, digital broadcasting has been started in a terrestrial broadcasting system. In this digital broadcasting, studio equipment that performs signal processing such as encoding and multiplexing of video signals is indispensable. In addition, digital broadcasting requires more precise and accurate processing than analog broadcasting.

Therefore, a highly stable reference frequency is obtained from the outside, and a PLL (Phase Locked Loop) is applied to the control input of the voltage controlled crystal oscillator (VCXO) using this reference frequency as a reference, so that a clock signal for high precision signal processing is obtained. It is considered to use a clock generation circuit for generating the signal (for example, Patent Document 1).
JP 2001-274678 A.

  By the way, in the terrestrial digital broadcasting, the ISDB-T system is determined in Japan. In countries other than Japan, the DVB-T system and the ATSC system are also used. Different broadcast systems have different clock frequencies used internally. For this reason, depending on the country or region in which the clock generation circuit is used, it is necessary to replace it with a dedicated VCXO corresponding to each method.

  Providing a dedicated clock generation circuit for each of the above methods leads to an increase in hardware scale.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a clock generation circuit that can be shared by a plurality of different broadcasting systems and that can simplify and reduce the circuit configuration.

In order to achieve the above object, the present invention is configured as follows.
An internal clock signal used to generate an input external clock signal as a reference clock signal, and to process the reference clock signal and a digital broadcast signal of a broadcast system specified from a plurality of broadcast systems in the signal processing unit In the clock generation circuit that controls the frequency of the internal clock signal so that the internal clock signal is phase-synchronized with the reference clock based on this phase difference. The reference clock signal is generated by dividing the external clock signal by a frequency dividing value according to the designated broadcasting system and an oscillator that generates the internal clock signal in a wider range than the variable range of the internal clock signal generation frequency. A first frequency divider, and a second frequency divider that divides the internal clock signal generated from the oscillator by a frequency-divided value corresponding to a designated broadcast system; A reference clock signal and the output signal of the second frequency divider and a phase comparator, in which as and a oscillation control means for controlling the generation frequency of the oscillator based on the phase comparison result.

  According to this configuration, an oscillator having a wide frequency variable range as compared with the conventional VCXO is used, and the first and second frequency dividers capable of variably setting the frequency division value are used, and the first and second frequency dividers are used. Only one setting is made according to the broadcast system of the digital broadcast signal that handles the divided values of the two frequency dividers, so that one oscillator can be shared by each broadcast system.

  Therefore, it is not necessary to change the time constant of the loop filter according to each broadcasting system, the accuracy of the frequency generated by the oscillator can be increased to the accuracy of the reference clock signal, and can be shared by a plurality of different broadcasting systems. Simplification and miniaturization of the circuit configuration can be realized.

  A storage means for storing a table indicating a correspondence relationship between a plurality of broadcasting systems and frequency division values to be set in the first and second frequency dividers, and a corresponding amount from the storage means in accordance with a designation input of the broadcasting system. Frequency division control means for reading the circumferential value and setting it in the first and second frequency dividers, respectively, is further provided.

  According to this configuration, the frequency dividing value for each broadcasting system stored and managed in the table is used, and the frequency dividing value is set in each of the first and second frequency dividers only by the designation input of the broadcasting system. Thus, an appropriate clock generation process can be performed with a simple procedure without manually adjusting the frequency dividing values of the first and second frequency dividers.

  As described above in detail, according to the present invention, it is possible to provide a clock generation circuit that can be shared by a plurality of different broadcasting systems and can be simplified and downsized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a clock generation circuit according to the present invention.

  In FIG. 1, reference numeral 11 denotes a voltage controlled oscillator (VCO) which generates a clock signal necessary for modulation processing of a terrestrial digital broadcast signal. The voltage controlled oscillator 11 has a frequency variable range wider than the frequency variable range of a normal voltage controlled crystal oscillator (VCXO). Further, in this embodiment, in order to stabilize the oscillation frequency of the voltage controlled oscillator 11, an external reference signal of 10 MHz is used.

  The external reference signal is frequency-divided by M (M is a natural number) by the frequency divider 12 and then input to the phase comparator (PD) 13. The clock signal output from the voltage controlled oscillator 11 is N-divided by the frequency divider 14 (N is a natural number) and then input to the phase comparator 13.

  The phase comparator 13 performs phase comparison between the output signal of the frequency divider 12 and the output signal of the frequency divider 13. The phase comparison result is converted into a control voltage of the voltage controlled oscillator 11 by the loop filter 15 and supplied to the voltage controlled oscillator 11. Then, the oscillation frequency of the voltage controlled oscillator 11 is controlled so that the generated clock signal is phase-synchronized with the external reference signal.

  In this embodiment, a frequency division value setting table 16 and a control unit 17 are provided. Of these, the frequency division value setting table 16 stores data representing the correspondence between the broadcast system and the frequency division values M and N set in the frequency dividers 12 and 14, respectively, as shown in FIG. .

  When the designation information designating the broadcasting system of the terrestrial digital broadcasting is input, the control unit 17 reads out the frequency division values M and N corresponding to the designated broadcasting system from the frequency division value setting table 16 and the frequency divider. Set to 12,14.

Next, operation in the above configuration will be described.
FIG. 3 is a block diagram showing a basic clock generation circuit. In FIG. 3, the same parts as those in FIG.

  Here, the external reference signal is common, the voltage controlled crystal oscillator (VCXO) 21 corresponding to each broadcasting system is selected, and the frequency dividers 22 and 23 are selected according to the output frequency.

  There are currently four types of digital terrestrial broadcasting broadcasting systems, and the clock frequencies used therein are different as follows (basic frequency [fs] is actually set to eight times the frequency for the sake of sampling). .

ISDB-T method: 512 / 63MHz
ATSC method: 4.5 * 684/286 MHz
DMB-T method: 7.56 MHz
DVB-T system [8 MHz band]: 64/7 MHz
DVB-T system [7 MHz band]: (64/7) * (7/8) MHz
DVB-T system [6 MHz band]: (64/7) * (6/8) MHz
By the way, if a circuit is configured for each broadcasting system, the number of systems corresponding to the circuit is required, which increases the hardware scale and is not practical.

  Therefore, in this embodiment, instead of the voltage controlled crystal oscillator 21, a voltage controlled oscillator 11 having a wide frequency variable range is used, and a PLD (Programmable Logic Device) or the like is used for the frequency dividers 12 and 14, The frequency division values M and N are changed according to the broadcasting system of the terrestrial digital broadcasting signal to be handled.

  In the phase comparator 13 and the loop filter 15, the phases of the output signals of the frequency dividers 12 and 14 are compared, and after passing through the loop filter 15, the control voltage of the voltage controlled oscillator 11 is obtained. The time constant of the loop filter 15 needs to be changed according to the comparison frequency of the phase comparator 13, but the values of the divided values M, N can be arbitrarily selected from twice, three times, and so on. By selecting a close value as the comparison frequency according to each broadcasting system, it is possible to realize without changing the time constant of the loop filter 15.

  Taking the ISDB-T method as an example, it is possible to realize the values of M and N as 310 and 2048, respectively, but by selecting 610 and 4096, the comparison frequency becomes 15.87 kHz, and the ATSC method is used. A value close to 13.99 kHz can be selected.

  As described above, in the above-described embodiment, the voltage controlled oscillator 11 having a wide frequency variable range as compared with the conventional voltage controlled crystal oscillator 21 is used, and the frequency divider 12 can variably set the divided values M and N. , 14 is used, and only one unit is read and set from the division value setting table 16 according to the broadcasting system of the digital terrestrial broadcasting signal that handles the division values M, N of the dividers 12, 14, respectively. The voltage-controlled oscillator 11 can be shared by each broadcasting system.

  Therefore, it is not necessary to change the time constant of the loop filter 15 in accordance with each broadcasting system, and the accuracy of the clock generation frequency of the voltage controlled oscillator 11 can be increased to the accuracy of the external reference signal. It can be shared by broadcasting systems, and the circuit configuration can be simplified and downsized.

  Further, in the above-described embodiment, the frequency dividers 12 and 14 are controlled by the control unit 17 using only the broadcast system designation input using the frequency division values M and N for each broadcast system accumulated and managed in the frequency division value setting table 16. The frequency dividing values M and N are respectively set to the respective clocks, so that an appropriate clock generation process can be performed by a simple procedure without manually adjusting the frequency dividing values M and N of the frequency dividers 12 and 14. It can be performed.

  The present invention is not limited to the above embodiment. For example, as shown in FIG. 4, the frequency division values M and N of the frequency dividers 12 and 14 may be set by other means without providing the frequency division value setting table 16 and the control unit 17. In this case, there is an advantage that the management of the divided values M and N for each broadcasting system can be simplified and the circuit configuration can be simplified.

  In the above embodiment, the present invention is applied to a digital terrestrial broadcast signal processing apparatus. However, the present invention can also be applied to clock generation in a signal processing apparatus of another communication system.

  In addition, the configuration of the clock generation circuit can be variously modified and implemented without departing from the gist of the present invention.

1 is a block diagram showing an embodiment of a clock generation circuit according to the present invention. The figure which shows an example of the memory content of the frequency division value setting table shown in FIG. The block diagram which shows a basic clock generation circuit. The block diagram which shows other embodiment of the clock generation circuit concerning this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Voltage controlled oscillator (VCO) 12, 14 ... Frequency divider, 13 ... Phase comparator (PD), 15 ... Loop filter, 16 ... Frequency division value setting table, 17 ... Control part, 21 ... Voltage controlled type Crystal oscillator (VCXO).

Claims (2)

An internal clock signal used to generate an input external clock signal as a reference clock signal, and to process the reference clock signal and a digital broadcast signal of a broadcast system specified from a plurality of broadcast systems in the signal processing unit In the clock generation circuit that controls the generation frequency of the internal clock signal so as to detect the phase difference by phase comparison with the reference clock and to synchronize the phase of the internal clock signal with the reference clock based on the phase difference.
An oscillator that is provided in the signal processing unit and generates an internal clock signal in a wider range than a variable range of the generation frequency of the internal clock signal;
A first frequency divider that divides the external clock signal by a frequency-divided value according to a designated broadcasting method to generate the reference clock signal;
A second frequency divider that divides the internal clock signal generated from the oscillator by a frequency-divided value corresponding to a designated broadcasting system;
A clock generation comprising: an oscillation control means for comparing the phase of the reference clock signal with the output signal of the second frequency divider and controlling the frequency generated by the oscillator based on the phase comparison result circuit. Storage means for storing a table showing a correspondence relationship between the plurality of broadcasting systems and the frequency division values to be set in the first and second frequency dividers;
Frequency division control means for reading out a corresponding frequency division value from the storage means and setting the frequency division values respectively in the first and second frequency dividers in response to the broadcast system designation input. The clock generation circuit according to claim 1.

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