JP2007234688A - Semiconductor device with overvoltage protection circuit - Google Patents

Semiconductor device with overvoltage protection circuit Download PDF

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JP2007234688A
JP2007234688A JP2006051468A JP2006051468A JP2007234688A JP 2007234688 A JP2007234688 A JP 2007234688A JP 2006051468 A JP2006051468 A JP 2006051468A JP 2006051468 A JP2006051468 A JP 2006051468A JP 2007234688 A JP2007234688 A JP 2007234688A
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overvoltage
protection circuit
circuit
integrated circuit
semiconductor integrated
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JP4904851B2 (en
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Masaru Nemoto
大 根本
Tomoyuki Uchiumi
智之 内海
Hiroyuki Hasegawa
裕之 長谷川
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Hitachi Ltd
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Hitachi Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with an overvoltage protection circuit that can avoid internal damage of an integrated circuit or secondary damage of an external circuit even if unexpected overvoltage is applied. <P>SOLUTION: The semiconductor device is provided with an overvoltage protection circuit to prevent damage among elements when overvoltage is applied among terminals of a circuit to be protected. The overvoltage protection circuit is provided with a first overvoltage protection circuit to operate protective action when overvoltage lower than a first preset voltage is applied, and a second protection circuit to shortcircuit among the terminals and avoid damage of the elements in the semiconductor integrated circuit when overvoltage higher than the first preset voltage is applied. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体集積回路を想定外の過電圧が印加された際に保護する過電圧保護回路と、この過電圧保護回路を備えた半導体装置に関する。   The present invention relates to an overvoltage protection circuit that protects a semiconductor integrated circuit when an unexpected overvoltage is applied, and a semiconductor device including the overvoltage protection circuit.

従来、半導体集積回路やその制御回路等の電気部品または電子部品は、電源電圧の変動に起因する過電圧や静電気に起因する誤動作や損傷を防止する為、過電圧保護回路を備えている。   2. Description of the Related Art Conventionally, an electrical component or an electronic component such as a semiconductor integrated circuit or its control circuit is provided with an overvoltage protection circuit in order to prevent malfunction or damage due to overvoltage or static electricity caused by fluctuations in power supply voltage.

このような過電圧保護回路の従来技術が特許文献1に開示されている。   The prior art of such an overvoltage protection circuit is disclosed in Patent Document 1.

特開平5−183109号公報(図1、図2と(0008)段落の記載。)Japanese Patent Laid-Open No. 5-183109 (Description of FIG. 1, FIG. 2 and paragraph (0008))

前記従来技術の過電圧保護回路では、想定内の過電圧に対しては、過電圧保護回路の許容電圧範囲内で回避できるが、想定外の過電圧が印加された際は、集積回路内部の損傷及び外部回路の2次的な損傷に至ることが考えられる。   In the overvoltage protection circuit of the prior art, an overvoltage within an assumption can be avoided within an allowable voltage range of the overvoltage protection circuit. However, when an unexpected overvoltage is applied, damage inside the integrated circuit and an external circuit It is thought that this leads to secondary damage.

本発明の目的は、想定外の過電圧が印加された場合でも集積回路内部の損傷や外部回路の2次的な損傷を回避できる過電圧保護回路を備えた半導体装置を提供することである。   An object of the present invention is to provide a semiconductor device including an overvoltage protection circuit capable of avoiding damage inside an integrated circuit and secondary damage to an external circuit even when an unexpected overvoltage is applied.

本発明の半導体装置は、過電圧保護回路に近接配置した低抵抗配線を備え、想定外の過電圧が印加された場合に近接配置した低抵抗線間を短絡させて被保護回路の損傷及び集積回路内部又は外部回路の2次損傷を回避する。   The semiconductor device of the present invention includes a low resistance wiring arranged close to the overvoltage protection circuit, and when an unexpected overvoltage is applied, the low resistance wires arranged close to each other are short-circuited to cause damage to the protected circuit and the inside of the integrated circuit. Alternatively, avoid secondary damage of external circuits.

本発明によれば、過電圧から保護することができると共に、想定外の過電圧が印加された場合にも、集積回路外部の回路の2次損傷を回避できる。   According to the present invention, it is possible to protect from overvoltage, and it is possible to avoid secondary damage of a circuit outside the integrated circuit even when an unexpected overvoltage is applied.

本発明の詳細を、図面と実施例とを用いて説明する。   The details of the present invention will be described with reference to the drawings and examples.

本実施例を、図1から図4を用いて説明する。図2は本実施例のインバータICを用いたモータ駆動装置の説明図である。図2の符号5はインバータIC、6はモータ、7は商用交流電源、8は整流平滑回路、9は制御部であるマイコン、10はモータの回転子の位置を検出する位置検出回路、11はインバータICに内蔵した駆動制御回路部、12は出カ段パワー素子部、Vsは出カ段パワー素子電源電圧、Vccは駆動制御回路電源電圧である。   This embodiment will be described with reference to FIGS. FIG. 2 is an explanatory diagram of a motor drive device using the inverter IC of this embodiment. 2 is an inverter IC, 6 is a motor, 7 is a commercial AC power supply, 8 is a rectifying and smoothing circuit, 9 is a microcomputer as a control unit, 10 is a position detection circuit for detecting the position of the rotor of the motor, and 11 is A drive control circuit unit built in the inverter IC, 12 is an output stage power element unit, Vs is an output stage power element power supply voltage, and Vcc is a drive control circuit power supply voltage.

本実施例のインバータIC5は、シリコン半導体基板に形成した、絶縁分離層で絶縁分離されたシリコン単結晶部を有する誘電体分離基板に前記出力段パワー素子部12と駆動制御回路部11とが配置されている。   In the inverter IC 5 of this embodiment, the output stage power element unit 12 and the drive control circuit unit 11 are arranged on a dielectric isolation substrate having a silicon single crystal portion insulated and separated by an insulation isolation layer formed on a silicon semiconductor substrate. Has been.

図2で、駆動制御回路部11は、図示しない駆動回路部と保護回路部とレベルシフト回路部とロジック回路部とを備えていて、マイコン9が発する制御信号を受けて出力段パワー素子部12に、例えば、パルス幅変調(PWM)したゲートドライブ信号を送る。なお、保護回路部は、過熱、過電流、低電圧等を検出し、検出信号をマイコン9や駆動制御回路部11の前記ロジック部に送り、出力段パワー素子部12の出力を制限する。   In FIG. 2, the drive control circuit unit 11 includes a drive circuit unit, a protection circuit unit, a level shift circuit unit, and a logic circuit unit (not shown), and receives an output signal from the microcomputer 9 to receive the output stage power element unit 12. For example, a gate drive signal subjected to pulse width modulation (PWM) is transmitted. The protection circuit unit detects overheating, overcurrent, low voltage, and the like, and sends a detection signal to the logic unit of the microcomputer 9 and the drive control circuit unit 11 to limit the output of the output stage power element unit 12.

出力段パワー素子部12は、上下それぞれのアームのパワー半導体素子であるIGBTあるいはパワーMOSFETをトーテムポール接続した上下アームを3つ備え、周波数可変のU相、V相、W相の3相交流を出カし、負荷のモータ6を駆動する。整流回路部8は、100V〜120Vあるいは、200V〜240Vの定格の商用交流電源7を整流し、出力段パワー素子部12に出力段パワー素子電源電圧Vsを供給する。駆動制御回路電源電圧Vccは本実施例では15Vであるが、この電圧には限らない。   The output stage power element section 12 includes three upper and lower arms each having a totem pole connection of IGBTs or power MOSFETs, which are power semiconductor elements of the upper and lower arms, and provides three-phase alternating currents of variable U phase, V phase, and W phase. The power is output and the load motor 6 is driven. The rectifier circuit unit 8 rectifies the commercial AC power supply 7 rated at 100 V to 120 V or 200 V to 240 V, and supplies the output stage power element power supply voltage Vs to the output stage power element unit 12. The drive control circuit power supply voltage Vcc is 15 V in this embodiment, but is not limited to this voltage.

図1は本実施例のインバータIC5の駆動制御回路部11の保護回路部が備える過電圧保護回路の回路図である。図1で、符号2はツェナーダイオード、3は抵抗体、4はNPNトランジスタ、Vccは駆動制御回路電源電圧である。ツェナーダイオード2のカソードは駆動制御回路電源電圧Vccに接続し、アノードは抵抗体3の一端とNPNトランジスタ4のべースとに接続される。さらに、NPNトランジスタ4のコレクタは駆動制御回路電源電圧Vccに接続されて、ツェナーダイオード2のカソードと同じ電位であり、NPNトランジスタ4のエミッタは抵抗体3の他端と接続され、図1では接地電位GLに接続されている。図1の符号1は駆動制御回路電源電圧Vccの電源電圧ライン(Vcc電源電圧ラインと略す。)と接地電位GLのライン(接地電位ラインと略す。)のAl配線領域1の概略を示しており、その形状の平面図を図3に、図3のI−I′の断面を図4に示す。図3、図4の斜線部A、Bは低抵抗配線であって、ここではAl配線とする。   FIG. 1 is a circuit diagram of an overvoltage protection circuit provided in the protection circuit unit of the drive control circuit unit 11 of the inverter IC 5 of this embodiment. In FIG. 1, reference numeral 2 is a Zener diode, 3 is a resistor, 4 is an NPN transistor, and Vcc is a drive control circuit power supply voltage. The cathode of the Zener diode 2 is connected to the drive control circuit power supply voltage Vcc, and the anode is connected to one end of the resistor 3 and the base of the NPN transistor 4. Further, the collector of the NPN transistor 4 is connected to the drive control circuit power supply voltage Vcc and is at the same potential as the cathode of the Zener diode 2, and the emitter of the NPN transistor 4 is connected to the other end of the resistor 3, and in FIG. It is connected to the potential GL. Reference numeral 1 in FIG. 1 shows an outline of the Al wiring region 1 of a power supply voltage line (abbreviated as a Vcc power supply voltage line) of the drive control circuit power supply voltage Vcc and a line of ground potential GL (abbreviated as ground potential line). FIG. 3 is a plan view of the shape, and FIG. 4 is a cross-sectional view taken along line II ′ of FIG. The hatched portions A and B in FIG. 3 and FIG. 4 are low resistance wirings, and are Al wirings here.

以下、図1に示す過電圧保護回路の動作を説明する。本実施例では、駆動制御回路電源電圧Vcc端子と接地電位GL端子との間(Vcc−GL間と略す。)のツェナーダイオード2のツェナー電圧を、端子間の最大定格電圧以上であって、かつ端子間の素子耐圧以下の電圧に設定する。過電圧等により、Vcc−GL間にツェナーダイオード2のツェナー電圧以上の電圧が印加されると、NPNトランジスタ4のべースに電流が流れ、NPNトランジスタ4がオンになる。この時、Vcc−GL間はツェナー電圧でクランプされる。   Hereinafter, the operation of the overvoltage protection circuit shown in FIG. 1 will be described. In this embodiment, the Zener voltage of the Zener diode 2 between the drive control circuit power supply voltage Vcc terminal and the ground potential GL terminal (abbreviated as Vcc-GL) is equal to or higher than the maximum rated voltage between the terminals, and Set the voltage below the element breakdown voltage between terminals. When a voltage equal to or higher than the Zener voltage of the Zener diode 2 is applied between Vcc and GL due to an overvoltage or the like, a current flows through the base of the NPN transistor 4 and the NPN transistor 4 is turned on. At this time, the voltage between Vcc and GL is clamped with a Zener voltage.

Vcc−GL間に前記端子間の素子耐圧以上である、想定外の高い過電圧が印加された際、被保護回路及び集積回路や基板内回路等の2次損傷を防止する方法を示す。図1に示すように、Al配線領域1を図3、図4に示すようにレイアウトする。Al配線領域1のAl配線は、過電流により融解して配線間が短絡するような配線幅、厚さ、配線間距離でレイアウトを施す。この場合、低抵抗配線Aと低抵抗配線Bとは絶縁体の上に対向して延在するように形成されており、低抵抗配線Aと低抵抗配線Bとは絶縁層で絶縁されている。   A method for preventing secondary damage to a protected circuit, an integrated circuit, an in-substrate circuit, and the like when an unexpectedly high overvoltage that is equal to or higher than the element breakdown voltage between the terminals is applied between Vcc and GL. As shown in FIG. 1, the Al wiring region 1 is laid out as shown in FIGS. The Al wiring in the Al wiring region 1 is laid out with a wiring width, a thickness, and a distance between the wirings that melt due to overcurrent and short-circuit between the wirings. In this case, the low resistance wiring A and the low resistance wiring B are formed so as to extend opposite to each other on the insulator, and the low resistance wiring A and the low resistance wiring B are insulated by an insulating layer. .

予め設定した素子耐圧以上の想定外の過電圧が印加された際、バイポーラトランジスタ4がオンし、Vcc−GL間に過電流が流れる。この時、過電流でAl配線が融解し、融解したAlによって配線間が短絡するよう所望のレイアウト構造にしているため、Vcc−GL間が短絡し端子間電圧が低下する。本実施例の駆動制御回路11は、図示しない低電圧保護回路を備えている為、Vcc−GL間電圧の低下により、駆動制御回路部11及び出力段パワー素子部12の2次損傷を防止することができ、これによりインバータIC5と接続されている外部素子及び回路の損傷を防止することが可能となる。   When an unexpected overvoltage exceeding the preset device breakdown voltage is applied, the bipolar transistor 4 is turned on, and an overcurrent flows between Vcc and GL. At this time, the Al wiring is melted by the overcurrent, and the desired layout structure is formed so that the wiring is short-circuited by the melted Al. Therefore, the Vcc-GL is short-circuited and the voltage between the terminals is lowered. Since the drive control circuit 11 of the present embodiment includes a low voltage protection circuit (not shown), secondary damage to the drive control circuit unit 11 and the output stage power element unit 12 is prevented by lowering the voltage between Vcc and GL. This can prevent damage to external elements and circuits connected to the inverter IC5.

本実施例では、ツェナーダイオード1個で構成しているが、端子間をクランプするツェナー電圧が、端子間の最大定格電圧以上、端子間耐圧未満の電圧となる素子数であれば良く、その数に制限はない。また、複数のツェナーダイオードを直列接続する場合に、各ツェナーダイオードのツェナー電圧は同じであっても異なっていてもよい。さらに、抵抗体及びNPNトランジスタの素子数に至っても同様に、その数に制限はない。   In this embodiment, a single Zener diode is used. However, the Zener voltage for clamping between terminals may be the number of elements that is not less than the maximum rated voltage between terminals and less than the withstand voltage between terminals. There is no limit. Further, when a plurality of Zener diodes are connected in series, the Zener voltage of each Zener diode may be the same or different. Furthermore, even if the number of elements of the resistor and the NPN transistor is reached, the number is not limited.

なお、本実施例では誘電体分離基板に形成したインバータIC5について説明したが、誘電体分離基板に代えて、絶縁分離層で絶縁分離されたシリコン単結晶部を備えたSOI半導体基板に形成したICであっても良い。   In this embodiment, the inverter IC 5 formed on the dielectric isolation substrate has been described. However, instead of the dielectric isolation substrate, the IC formed on the SOI semiconductor substrate including the silicon single crystal portion insulated and separated by the insulation isolation layer. It may be.

本実施例を、図5及び図6を用いて説明する。図5は図1のAl配線領域1の平面図、図6は図5のII−II′部分の断面図である。図5、図6の斜線部C、Dは低抵抗配線であり、ここではAl配線とする。低抵抗配線が多層配線であること以外は、実施例1と同様である。   This embodiment will be described with reference to FIGS. FIG. 5 is a plan view of the Al wiring region 1 of FIG. 1, and FIG. 6 is a cross-sectional view of the II-II ′ portion of FIG. The hatched portions C and D in FIG. 5 and FIG. 6 are low resistance wirings, and here are Al wirings. Example 1 is the same as Example 1 except that the low resistance wiring is a multilayer wiring.

本実施例では、低抵抗配線Cと低抵抗配線Dとは、絶縁層を介して図5、図6に示すように交差している。想定外の過電圧が印加された際、本実施例でも実施例1と同様に、予め設定した過電流でAl配線が融解し、融解したAlで配線間が短絡するよう所望のレイアウト構造にしている。   In this embodiment, the low resistance wiring C and the low resistance wiring D intersect with each other as shown in FIGS. 5 and 6 through an insulating layer. When an unexpected overvoltage is applied, in this embodiment as well as in the first embodiment, the Al wiring is melted by a preset overcurrent, and a desired layout structure is formed so that the wiring is short-circuited by the melted Al. .

本実施例を、図7を用いて説明する。本実施例では、実施例1と実施例2のインバータIC5に代えて、図7に示すように、プリドライバIC13と、出力段パワー素子14とを用いることが異なり、他は実施例1や実施例2と同様である。   This embodiment will be described with reference to FIG. In the present embodiment, instead of the inverter IC 5 of the first embodiment and the second embodiment, as shown in FIG. 7, a pre-driver IC 13 and an output stage power element 14 are used. Similar to Example 2.

プリドライバIC13は、誘電体分離基板に形成した駆動制御回路部11を備え、この駆動制御回路部11は、図示しない駆動回路部と保護回路部とレベルシフト回路部とロジック回路部とを備えていて、マイコン9が発する制御信号を受けて出力段パワー素子14に、例えば、パルス幅変調(PWM)したゲートドライブ信号を送る。なお、保護回路部は、過電流や過熱や低電圧等を検出し、検出信号をマイコン9や前記ロジック部に送り、出カ段パワー素子14の出力を制限する。   The pre-driver IC 13 includes a drive control circuit unit 11 formed on a dielectric isolation substrate. The drive control circuit unit 11 includes a drive circuit unit, a protection circuit unit, a level shift circuit unit, and a logic circuit unit (not shown). In response to the control signal generated by the microcomputer 9, for example, a pulse drive modulated (PWM) gate drive signal is sent to the output stage power element 14. The protection circuit unit detects overcurrent, overheat, low voltage, and the like, and sends a detection signal to the microcomputer 9 and the logic unit to limit the output of the output stage power element 14.

本実施例の出カ段パワー素子14は、上下のそれぞれのアームのIGBTあるいはパワーMOSFETをトーテムポール接続したアームを3つ備え、周波数可変のU相、V相、W相の3相交流を出力し、負荷のモータ6を駆動する。   The output stage power element 14 of the present embodiment has three arms in which the upper and lower arms IGBTs or power MOSFETs are connected by totem pole connection, and outputs a three-phase alternating current of U-phase, V-phase, and W-phase with variable frequency. Then, the load motor 6 is driven.

本実施例の整流回路部8は、100V〜120Vあるいは、200V〜240Vの定格の商用交流電源7を整流し、出力段パワー素子14に出カ段パワー素子電源電圧Vsを供給する。駆動制御回路電源電圧Vccは本実施例では15Vであるが、この電圧には限らない。   The rectifier circuit unit 8 of this embodiment rectifies the commercial AC power supply 7 rated at 100 V to 120 V or 200 V to 240 V, and supplies the output stage power element power supply voltage Vs to the output stage power element 14. The drive control circuit power supply voltage Vcc is 15 V in this embodiment, but is not limited to this voltage.

本実施例のプリドライバIC13も、駆動制御回路部11の保護回路部に実施例1の図1に示す過電圧保護回路を備え、さらに図示しない低電圧保護回路も備えている。プリドライバIC13に、Vcc−GL間に想定外の高い過電圧が印加された場合には、実施例1や実施例2と同様に、Al配線領域1のAl配線が融解し、融解したAlで配線間が短絡してVcc−GL間が短絡し端子間電圧を低下させる。   The pre-driver IC 13 of this embodiment also includes the overvoltage protection circuit shown in FIG. 1 of the first embodiment in the protection circuit section of the drive control circuit section 11, and further includes a low voltage protection circuit (not shown). When an unexpected high overvoltage is applied to the pre-driver IC 13 between Vcc and GL, the Al wiring in the Al wiring region 1 is melted and wiring is performed with the melted Al as in the first and second embodiments. A short circuit occurs between Vcc and GL, and a voltage between terminals decreases.

なお、本実施例では誘電体分離基板に形成したプリドライバIC13について説明したが、誘電体分離基板に代えて、絶縁分離層で絶縁分離されたシリコン単結晶部を備えたSOI半導体基板に形成したICであっても良い。   In this embodiment, the pre-driver IC 13 formed on the dielectric isolation substrate has been described. However, instead of the dielectric isolation substrate, the pre-driver IC 13 is formed on an SOI semiconductor substrate including a silicon single crystal portion that is insulated and separated by an insulating isolation layer. IC may be sufficient.

実施例1の過電圧保護回路の回路図。1 is a circuit diagram of an overvoltage protection circuit according to Embodiment 1. FIG. 実施例1のインバータICを有するモータ駆動装置の説明図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 実施例1の過電圧保護回路のAl配線領域の平面図。FIG. 3 is a plan view of an Al wiring region of the overvoltage protection circuit according to the first embodiment. 図3のI−I′部分の断面図。Sectional drawing of the II 'part of FIG. 実施例2の過電圧保護回路のAl配線領域の平面図。FIG. 6 is a plan view of an Al wiring region of the overvoltage protection circuit according to the second embodiment. 図5のII−II′部分の断面図。Sectional drawing of the II-II 'part of FIG. 実施例3のプリドライバICを有するモータ駆動装置の説明図。FIG. 6 is an explanatory diagram of a motor driving device having a pre-driver IC according to a third embodiment.

符号の説明Explanation of symbols

1…Al配線領域、2…ツェナーダイオード、3…抵抗体、4…NPNトランジスタ、5…インバータlC、6…モータ、7…商用交流電源、8…整流平滑回路、9…マイコン、10…位置検出回路、11…駆動制御回路部、12…出力段パワー素子部、13…プリドライバIC、14…出カ段パワー素子。
DESCRIPTION OF SYMBOLS 1 ... Al wiring area | region, 2 ... Zener diode, 3 ... Resistor, 4 ... NPN transistor, 5 ... Inverter IC, 6 ... Motor, 7 ... Commercial alternating current power supply, 8 ... Rectification smoothing circuit, 9 ... Microcomputer, 10 ... Position detection Reference numeral 11 is a drive control circuit section, 12 is an output stage power element section, 13 is a pre-driver IC, and 14 is an output stage power element.

Claims (13)

被保護回路の端子間に過電圧が印加された際、端子間の素子損傷を防止する過電圧保護回路を備えた半導体装置において、
前記過電圧保護回路が、第1の設定電圧より低い過電圧が印加された場合に保護動作する第1の過電圧保護回路と、
前記第1の設定電圧より高い過電圧が印加された場合に、前記端子間を短絡させ半導体集積回路内部の素子損傷を回避する第2の保護回路とを有することを特徴とした過電圧保護回路を備えた半導体装置。
When an overvoltage is applied between terminals of a protected circuit, in a semiconductor device provided with an overvoltage protection circuit that prevents element damage between terminals,
A first overvoltage protection circuit that performs a protection operation when an overvoltage lower than a first set voltage is applied;
An overvoltage protection circuit comprising: a second protection circuit for short-circuiting the terminals and avoiding element damage inside the semiconductor integrated circuit when an overvoltage higher than the first set voltage is applied. Semiconductor device.
請求項1に記載の保護回路を備えた半導体装置において、
前記第2の保護回路が、対向配置した配線を過電圧によって融解させて、端子間を短絡させることを特徴とした過電圧保護回路を備えた半導体装置。
A semiconductor device comprising the protection circuit according to claim 1.
A semiconductor device provided with an overvoltage protection circuit, wherein the second protection circuit melts wiring arranged opposite to each other by overvoltage to short-circuit between terminals.
請求項1に記載の保護回路を備えた半導体装置において、
前記第1の保護回路が、ツェナーダイオードと抵抗体とトランジスタとを備えていることを特徴とする過電圧保護回路を備えた半導体装置。
A semiconductor device comprising the protection circuit according to claim 1.
A semiconductor device having an overvoltage protection circuit, wherein the first protection circuit includes a Zener diode, a resistor, and a transistor.
請求項3に記載の保護回路を備えた半導体装置において、
前記ツェナーダイオードのツェナー電圧が、前記端子間の最大定格電圧以上、端子間の素子耐圧未満の電圧であることを特徴とする過電圧保護回路を備えた半導体装置。
A semiconductor device comprising the protection circuit according to claim 3.
A semiconductor device comprising an overvoltage protection circuit, wherein a Zener voltage of the Zener diode is a voltage that is greater than or equal to a maximum rated voltage between the terminals and less than an element breakdown voltage between the terminals.
請求項3に記載の過電圧保護回路を備えた半導体装置において、
前記第1の保護回路が、被保護回路の入力端にツェナーダイオードのカソードが接続し、前記ツェナーダイオードのアノードとバイポーラトランジスタのべースとが抵抗体の一端に接続し、前記バイポーラトランジスタのコレクタがツェナーダイオードのカソード接続して、前記抵抗体の他端と前記バイポーラトランジスタのエミッタとが共通電位に接続されたことを特徴とする過電圧保護回路を備えた半導体装置。
A semiconductor device comprising the overvoltage protection circuit according to claim 3.
In the first protection circuit, a cathode of a Zener diode is connected to an input terminal of the protected circuit, an anode of the Zener diode and a base of the bipolar transistor are connected to one end of a resistor, and a collector of the bipolar transistor A semiconductor device comprising an overvoltage protection circuit, wherein the cathode of a zener diode is connected, and the other end of the resistor and the emitter of the bipolar transistor are connected to a common potential.
出カ段パワー素子部と、該出力段パワー素子部を駆動する駆動制御回路部とを備えた半導体集積回路において、
前記出カ段パワー素子部が、パワー半導体素子をトーテムポール接続した3個のアームを備え、
前記駆動制御回路部が、駆動回路部とロジック回路部と保護回路部とを備え、
前記保護回路部が、被保護回路の入力端にツェナーダイオードのカソードが接続し、前記ツェナーダイオードのアノードとバイポーラトランジスタのべースとが抵抗体の一端に接続し、前記バイポーラトランジスタのコレクタがツェナーダイオードのカソード接続して、前記抵抗体の他端と前記バイポーラトランジスタのエミッタとが共通電位に接続された第1の設定電圧より低い過電圧が印加された場合に保護動作する第1の過電圧保護回路と、
前記第1の設定電圧より高い過電圧が印加された場合に、対向配置した配線を過電圧によって融解させて、前記端子間を短絡させて半導体集積回路内部の素子損傷を回避する第2の保護回路とを備えたことを特徴とする半導体集積回路。
In a semiconductor integrated circuit comprising an output stage power element section and a drive control circuit section for driving the output stage power element section,
The output stage power element portion includes three arms to which a power semiconductor element is connected to a totem pole,
The drive control circuit unit includes a drive circuit unit, a logic circuit unit, and a protection circuit unit,
The protection circuit unit includes a cathode of a Zener diode connected to an input terminal of the protected circuit, an anode of the Zener diode and a base of the bipolar transistor are connected to one end of a resistor, and a collector of the bipolar transistor is a Zener A first overvoltage protection circuit which performs a protection operation when an overvoltage lower than a first set voltage is applied, in which a cathode of a diode is connected and the other end of the resistor and the emitter of the bipolar transistor are connected to a common potential When,
A second protection circuit for avoiding element damage inside the semiconductor integrated circuit by melting the wiring arranged oppositely by overvoltage and short-circuiting the terminals when an overvoltage higher than the first set voltage is applied; A semiconductor integrated circuit comprising:
請求項6に記載の半導体集積回路において、
前記出カ段パワー素子部と駆動制御回路部とが、同じシリコン半導体基板に形成されていて、前記シリコン半導体基板が、絶縁分離層で絶縁分離されたシリコン単結晶部を備え、
前記シリコン単結晶部に前記出力段パワー素子部と駆動制御回路部とが配置されていることを特徴とする半導体集積回路。
The semiconductor integrated circuit according to claim 6,
The output power element portion and the drive control circuit portion are formed on the same silicon semiconductor substrate, and the silicon semiconductor substrate includes a silicon single crystal portion that is insulated and separated by an insulating separation layer,
A semiconductor integrated circuit, wherein the output stage power element portion and a drive control circuit portion are arranged in the silicon single crystal portion.
請求項6に記載の半導体集積回路において、
前記絶縁分離層で絶縁分離されたシリコン単結晶部を備えたシリコン半導体基板が誘電体分離半導体基板であることを特徴とする半導体集積回路。
The semiconductor integrated circuit according to claim 6,
A semiconductor integrated circuit, wherein a silicon semiconductor substrate having a silicon single crystal portion insulated and separated by the insulation separation layer is a dielectric separation semiconductor substrate.
請求項6に記載の半導体集積回路において、
前記絶縁分離層で絶縁分離されたシリコン単結晶部を備えたシリコン半導体基板がSOI半導体基板であることを特徴とする半導体集積回路。
The semiconductor integrated circuit according to claim 6,
A semiconductor integrated circuit, wherein a silicon semiconductor substrate having a silicon single crystal portion insulated and separated by the insulating separation layer is an SOI semiconductor substrate.
出力段パワー素子部を駆動する駆動制御回路部を備えた半導体集積回路において、
前記駆動制御回路部が、駆動回路部とロジック回路部と保護回路部とを備え、
前記保護回路部が、被保護回路の入力端にツェナーダイオードのカソードが接続し、前記ツェナーダイオードのアノードとバイポーラトランジスタのべースとが抵抗体の一端に接続し、前記バイポーラトランジスタのコレクタがツェナーダイオードのカソード接続して、前記抵抗体の他端と前記バイポーラトランジスタのエミッタとが共通電位に接続された第1の設定電圧より低い過電圧が印加された場合に保護動作する第1の過電圧保護回路と、
前記第1の設定電圧より高い過電圧が印加された場合に、対向配置した配線を過電圧によって融解させて、前記端子間を短絡させて半導体集積回路内部の素子損傷を回避する第2の保護回路とを備えたことを特徴とする半導体集積回路。
In a semiconductor integrated circuit including a drive control circuit unit for driving an output stage power element unit,
The drive control circuit unit includes a drive circuit unit, a logic circuit unit, and a protection circuit unit,
The protection circuit unit includes a cathode of a Zener diode connected to an input terminal of the protected circuit, an anode of the Zener diode and a base of the bipolar transistor are connected to one end of a resistor, and a collector of the bipolar transistor is a Zener A first overvoltage protection circuit which performs a protection operation when an overvoltage lower than a first set voltage is applied, in which a cathode of a diode is connected and the other end of the resistor and the emitter of the bipolar transistor are connected to a common potential When,
A second protection circuit for avoiding element damage inside the semiconductor integrated circuit by melting the wiring arranged oppositely by overvoltage and short-circuiting the terminals when an overvoltage higher than the first set voltage is applied; A semiconductor integrated circuit comprising:
請求項10に記載の半導体集積回路において、
前記駆動制御回路部が、シリコン半導体基板に形成されていて、前記シリコン半導体基板が、絶縁分離層で絶縁分離されたシリコン単結晶部を備え、
前記シリコン単結晶部に駆動制御回路部が配置されていることを特徴とする半導体集積回路。
The semiconductor integrated circuit according to claim 10,
The drive control circuit portion is formed on a silicon semiconductor substrate, and the silicon semiconductor substrate includes a silicon single crystal portion that is insulated and separated by an insulating separation layer;
A semiconductor integrated circuit, wherein a drive control circuit portion is disposed in the silicon single crystal portion.
請求項11に記載の半導体集積回路において、
前記絶縁分離層で絶縁分離されたシリコン単結晶部を備えたシリコン半導体基板が誘電体分離半導体基板であることを特徴とする半導体集積回路。
The semiconductor integrated circuit according to claim 11, wherein
A semiconductor integrated circuit, wherein a silicon semiconductor substrate having a silicon single crystal portion insulated and separated by the insulation separation layer is a dielectric separation semiconductor substrate.
請求項11に記載の半導体集積回路において、
前記絶縁分離層で絶縁分離されたシリコン単結晶部を備えたシリコン半導体基板がSOI半導体基板であることを特徴とする半導体集積回路。
The semiconductor integrated circuit according to claim 11, wherein
A semiconductor integrated circuit, wherein a silicon semiconductor substrate having a silicon single crystal portion insulated and separated by the insulating separation layer is an SOI semiconductor substrate.
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Cited By (2)

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Publication number Priority date Publication date Assignee Title
JP2017135852A (en) * 2016-01-27 2017-08-03 ミネベアミツミ株式会社 Motor drive controller and motor drive control method therefor
CN109950242A (en) * 2015-03-27 2019-06-28 亚德诺半导体集团 Electrical overstress record and/or acquisition

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JP2022148353A (en) 2021-03-24 2022-10-06 株式会社東芝 Semiconductor device

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JP2000050486A (en) * 1998-07-27 2000-02-18 Denso Corp Protection device for integrated circuit

Patent Citations (1)

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JP2000050486A (en) * 1998-07-27 2000-02-18 Denso Corp Protection device for integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950242A (en) * 2015-03-27 2019-06-28 亚德诺半导体集团 Electrical overstress record and/or acquisition
CN109950242B (en) * 2015-03-27 2023-09-01 亚德诺半导体国际无限责任公司 Electrical overstress recording and/or acquisition
JP2017135852A (en) * 2016-01-27 2017-08-03 ミネベアミツミ株式会社 Motor drive controller and motor drive control method therefor

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