JP2007228530A - Encoding apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an encoding apparatus capable of obtaining sufficient throughput by suppressing absolute delay and circuit scale in encoding operation. <P>SOLUTION: An entropy encoding apparatus 10 stores a quantized transform coefficient in a data register part 12 as data, reads this transform coefficient from the data register part 12 in the direction of columns, outputs data 24 eight by eight from a state output part 16 to an encoding operation part 20 in response to a state control signal 26 from a state output control part 18, and operates the data 24 in the encoding operation part 20 in the order of reading in a zigzag scan direction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an encoding device, and more particularly to an encoding device in which an entropy encoding unit for image compression and still image compression is reasonably implemented.

  Conventionally, still images have been compressed by an entropy encoding unit. At the time of compression, the entropy encoding unit reads the data string to be calculated one-dimensionally in the order according to the zigzag scan rule. However, note that this order is different from the operation data register number. The entropy coding unit performs an entropy coding by calculating based on each data read in one dimension.

  For example, consider an arithmetic data register storing 64 arithmetic data. For convenience, numbers of O to 63 are given to 8 × 8, a total of 64 cells, and each data is specified. As will be described later, not all data is prepared in the operation data register from the beginning. The data is supplied by dividing into eight states of 0 to 7, then 8 of 8 to 15,..., 56 to 63 and 8 sets, that is, 8 times or 8 rows. In this way, after the eighth data supply, all 64 data are collected.

  The calculation in the entropy encoding is performed using 64 pieces of data preceding the calculation data. Consecutive here means not the order of operation data register numbers, but the order given according to the zigzag scan rule starting from the upper left corner of the 64 cells. If all of them are not arranged in this order, the entropy encoding operation is not performed.

  Therefore, when there is no missing data in the order of calculation in entropy coding, there is a waiting time until the missing data is collected. As a result, the computation stops during the waiting time. Since the processing is executed based on all the collected data, an absolute delay occurs until the start of execution in order to perform calculation without delay. Also, if the data is aligned and entropy-coded for each data according to the order, the number of computation steps increases. This means that the calculation amount, that is, the throughput is small.

Contrary to the operation in the entropy encoding described above, there is a disclosure of a technique for converting data used in encoding into a zigzag rule and reading it out. Patent document 1 is an image coding system. This system uses a dual-port memory to realize raster scan and zigzag scan on one side of RAM (Random Access Memory), and the start address sending time of zigzag address is 29th to 34th from the start address sending of raster address. A delay unit is provided for delaying until the designated address set in the address is sent, and the quantization coefficient is written from the first port of the dual port, and the written quantization coefficient is read from the second port. This reduces the circuit scale of this system. Conventionally, since a zigzag scan is performed on a raster scan that has been completed, a circuit delay of 64 addresses has occurred, but the circuit delay can be reduced to half.
Japanese Patent Laid-Open No. 5-207289

  By the way, if the absolute delay is large as described above, a memory for storing delay data is used, which causes an increase in circuit scale. Furthermore, in recent years, real-time performance is required in each field, and it is desired that calculations be executed without delay. However, generally, when the circuit scale is reduced, the absolute delay required for the calculation increases and the calculation amount decreases.

  Further, Patent Document 1 merely describes a circuit configuration of data writing / reading processing in DCT (Discrete Cosine Transform) calculation in the previous stage for obtaining a quantization coefficient. Further, Patent Document 1 is characterized in that operation is performed so that writing and reading do not collide or overlap each other by reading within the 29th to 34th addresses from the time of sending the start address of the raster address, and the circuit delay is reduced by half. Have finished.

  However, as described above, entropy encoding is performed by reading data sequences in the order according to the zigzag scan rule. For this reason, even if Patent Document 1 is applied to the entropy encoding calculation, after all the data for 64 addresses are obtained, the calculation is performed in the order according to the zigzag scan rule. That is, the circuit delay for 64 addresses is not improved, and sufficient throughput cannot be obtained.

  An object of the present invention is to provide an encoding apparatus capable of solving such disadvantages of the prior art and suppressing the absolute delay and the circuit scale in encoding operations and obtaining a sufficient throughput. .

  In order to solve the above-described problem, the present invention calculates and encodes a quantized transform coefficient obtained by transforming supplied first data in the first direction as second data. In the encoding apparatus, the apparatus is a predetermined unit in which a plurality of second data read out in a second direction different from the first direction from the storage means for storing the second data is collected. Read control means for generating a read control signal to be read, output means for outputting second data in a predetermined unit according to the read control signal, and supplied second data are read in the first direction. And encoding means for calculating in order.

  According to the encoding apparatus of the present invention, the second data is stored in the storage means, the second data is read from the storage means in the second direction, and output in accordance with the read control signal from the read control means. By outputting the second data from the means to the encoding means in a predetermined unit, and calculating the second data in the order read in the first direction by the encoding means, the absolute delay and the encoding means Even if the circuit scale is suppressed, sufficient throughput can be obtained.

  Next, an embodiment of an encoding apparatus according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, an embodiment of an encoding apparatus according to the present invention stores quantized transform coefficients as data in a data register unit 12, reads the transform coefficients from the data register unit 12 in the column direction, and outputs a state output. In response to the state control signal 26 from the control unit 18, the state output unit 16 outputs the data 24 to the encoding operation unit 20 in units of 8, and the encoding operation unit 20 reads the data 24 in the zigzag scan direction. Even if the absolute delay and the circuit scale of the encoding means are suppressed by calculating in order, a sufficient throughput can be obtained.

  In this embodiment, the encoding apparatus of the present invention is applied to the entropy encoding apparatus 10. The illustration and description of parts not directly related to the present invention are omitted. In the following description, the signal is indicated by the reference number of the connecting line in which it appears.

  As shown in FIG. 1, the entropy encoding apparatus 10 includes a data register unit 12, a read control unit 14, a state output unit 16, a state output control unit 18, and an encoding operation unit 20. The data register unit 12 has a function of storing block data. In the present embodiment, the data register unit 12 stores data (numerical values or quantized transform coefficients) after orthogonal transform used for computation by the encoding computation unit 20. There are 8 × 8 = 64 pieces of block data to be stored. The data register unit 12 outputs the data stored in each register to the state output unit 16 in response to the read control signal 22 from the read control unit 14.

  The read control unit 14 has a function of reading from the data register of the data register unit 12. The read control unit 14 generates a read control signal 22 based on the above function and outputs data to the data register unit 12.

  The state output unit 16 has a function of handling and outputting, for example, eight quantized transform coefficients included in the state supplied from the data register unit 12 as a group. The state output unit 16 outputs the supplied state data 24 to the encoding operation unit 20. The state output control unit 18 has a function of generating a state control signal 26 for each state according to the order of block data. The state output control unit 18 outputs a state control signal 26 to the state output unit 16.

  The encoding calculation unit 20 has a function of entropy encoding by calculation based on supplied data (quantized transform coefficient) 24. In entropy coding, a short code is assigned to a quantized transform coefficient or symbol having a high appearance frequency by an operation, and a long code is assigned to a symbol having a low appearance frequency. Examples of this encoding include Huffman encoding and arithmetic encoding. The encoding calculation unit 20 includes a Huffman encoding unit that is entropy encoding of JPEG (Joint Photographic Experts Group). The encoding operation unit 20 is supplied with 64 data, for example, “0”, “0,1”, “0,1,2”, “0,1,2,3” ,... And “0, 1, 2, 3, 4,..., 61, 62, 63”, the entropy-encoded data 28 is output.

  Needless to say, the entropy encoding apparatus 10 not only includes the read control unit 14, but also includes a write control unit (not shown). The write control unit has a function of controlling writing of the quantized transform coefficient in the data register unit 12.

  Next, the operation of the entropy encoding device 10 will be described. There is an orthogonal transform unit (not shown) in the previous stage of the entropy encoding device 10. Since the entropy encoding device 10 handles data after computation in the orthogonal transform unit, the entropy encoding is greatly affected by the operation in this orthogonal transform.

  Here, the orthogonal transform unit uses discrete cosine transformation (DCT) in JPEG compression.

  2 and 3 correspond to the registers of the data register unit 12 shown in FIG. The numbers in the squares in FIG. 3 (a) indicate the register positions. The squares in FIG. 2 (a) and FIG. 3 (a) store data after orthogonal transformation, that is, quantized transform coefficients. The arrow 30 in FIG. 2 (b) indicates that data is written according to the zigzag scan rule. In such a data storage situation, the data is read in the column direction as indicated by the arrow 32 in FIG. However, entropy encoding is performed using data read according to a zigzag scan rule.

  Referring to FIG. 1, there are a total of 64 transform coefficients quantized in this way, but the data after orthogonal transform is read out to the state output unit 16. The state output unit 16 outputs the read data 24 by eight to the encoding operation unit 20. The encoding calculation unit 20 calculates and entropy-encodes the supplied data 24. At this time, entropy coding is calculated according to a zigzag scan rule depending on data calculation of orthogonal transform. However, the data 24 is supplied to the encoding operation unit 20 in a reading order different from the zigzag scanning rule. Therefore, the entropy encoding device 10 is required to rationally absorb and execute the difference in the calculation order based on the data supplied for each state and the data according to the zigzag scan rule.

  Next, these 64 quantized transform coefficients are simply referred to as data. A description will be given of how these data are calculated. Conventionally, in general, for the data array of FIG. 2 (a), from the rationality of the two-dimensional orthogonal transformation operation, a primary operation is performed in the direction of the arrow 34 in FIG. Next, a secondary calculation is performed in the direction of arrow 36 in FIG.

  In the case of the present embodiment, the data calculation after the orthogonal transformation shown in FIG. 4 will be described. In actual operation, data calculation is performed in the column direction shown in FIG. 4B as a secondary calculation in the two-dimensional orthogonal transformation. In this data calculation, since one column of data is supplied to the encoding calculation unit 20, the encoding calculation unit 20 has a structure in which one column of data is calculated in one step. In the data array of FIG. 2 (a), eight data units in the column direction are sent at a time in one step for use in the entropy coding operation of the next step. The entropy encoding device 10 operates, that is, calculates based on such a basic structure of the calculation system.

  By the way, as the data after the orthogonal transformation, eight data are prepared in order in the column direction, but as described above, the encoding calculation unit 20 performs the calculation according to the zigzag scan rule shown in FIG. Proceed. For this reason, when attention is focused on one point of data for entropy coding, data used for calculation within a certain step may not be complete.

  This case is expressed by the concept of a sequential circuit using a clock. The data used for the calculation is 8 in one state by the read control unit 14, and arbitrary data is input / output once per clock. That is, one state can be input / output in 8 clocks. Block data is read out at 64 clocks. This also means that an operation with an arbitrary number of clocks in a state is performed by dividing the number of clock steps. In other words, 8 data in 1 row are arranged in 1 state, and all 8 states and 64 data sets are sequentially repeated, thus completing one set. When this one set is completed, the second set is similarly started without a gap, and is repeated until the next set disappears continuously.

  In the present embodiment, the division by the clock is not described, and thus the description of this meaning is omitted. As described above, since the encoding calculation unit 20 uses the JPEG Huffman code, the entropy encoding is defined as a standard so that the calculation is performed in the order of the zigzag scan rule of FIG.

  Here, for the calculation of a certain square, the values of all the squares that are younger than the scanned square are used. More specifically, data of the cells of “1, 2” is used for the calculation of the third cell, and “17, 16,..., This means that the square data before 18 is used, such as “2,1”.

  In the calculation of a certain square, data before this square is aligned, but the state of reading data for the eighth square in the column direction in one state is sequentially repeated. However, in this read operation, data used for calculation of a certain square is not prepared. Specifically, FIG. 5 shows the relationship among the read state, the processing amount, and the processing amount when delayed by one state. In the first state (first state), as is clear from FIG. 2A, the cell numbers are “0, 2, 3, 9, 10, 20, 21, 33”. In this case, since there is no “1”, it can be seen that there is no square or data that can be entropy-coded. Therefore, the processing amount is zero. In the second state, the data of “1, 4, 8, 11, 19, 22, 34, 36” is available. At this time, “1, 2, 3, 4” are continuously arranged in the grid. Therefore, entropy coding can calculate each of four squares from 1 to 4. Sequentially, in this way, the data of “5, 7, 12, 18, 23, 33, 37, 48” is prepared in the third state. For the cells, “1,2,3,4,5” are continuously arranged, and the entropy coding can calculate the first cell in the third state. In the 4th state, “1 to 13” are continuously arranged. Entropy encoding can be performed for the eighth square (13- (4 + 1)).

  Similarly, in the fifth state, entropy encoding for the first square of “14” becomes possible. In the sixth state, entropy coding for the 12th cell from “15 to 26” can be calculated. In the seventh state, entropy coding for the first square of “27” becomes possible. Finally, entropy coding for the 37th cell including the DC component can be calculated in the 8th state. Thereby, entropy coding is calculated for all values.

  Here, as can be seen from the processing amount of FIG. 6, the encoding operation unit 20 is required to perform simultaneous calculation for the 37th cell in a maximum of one state. From the calculation processing amount described above, the encoding calculation unit 20 of this embodiment corresponds to a case where n = 37 encoding calculation circuits or calculation blocks are mounted.

  When there is an operation block that performs one operation in one state, 37 operation blocks are used in the eighth state in order to obtain a throughput equivalent to the input. In addition, 37 clocks are required to reduce the number of operation blocks to one. Using a large number of clocks divides the time of one state finely. As a result, the cycle of one clock is shortened. For this reason, the problem of improving the calculation speed of a calculation block also arises.

  In order to cope with such a situation, the entropy encoding device 10 is arranged as an encoding unit 38 as shown in FIG. The encoding unit 38 includes a plurality of encoding calculation units 20, 40, and 42. FIG. 6 shows that the data line corresponding to the number of the encoding operation units 20, 40 and 42 is connected from the state output unit 16 to the encoding unit 38. In this embodiment, three encoding operation units are also provided for the output 3 of the state output unit 16. When the calculation is performed with the same number of states as the number of states used for reading, the pipeline calculation can be performed even if the collected state data is passed to the encoding unit 38. As a result, there is no throughput problem.

  Here, the throughput problem occurs when the number of computation states is larger than the data read processing in a state where pipeline computation cannot be performed. More specifically, this means that the amount of calculation is increased for the portion that reads and calculates data sequentially from the operation register of the basic operation in the order of the zigzag scan rule. In other words, as a technique for improving the throughput, it can be said that a plurality of operation blocks are installed, and data stored in the operation registers is rationally sent to a plurality of operation blocks. The encoding unit 38 in FIG. 6 distributes the operation blocks to the encoding operation units 20, 40, and 42, but sets the total number of operation blocks in the encoding unit 38 to n = 37 as described above.

  Returning to FIG. 5 again, the delayed data transmission is proposed as one of the latter methods. In this embodiment, a delay circuit 44 having a function of shifting the operation state by one is arranged in the state output unit 16. According to this reading, the encoding operation unit 20 combines the data of the first and next states and performs the operation using two states. The number of possible operations is 0 in the first state, and 4 operations are possible in the next state.

  Here, in the shifted first state, four operations are equally divided to perform two operations, and two operations are performed in the next state. The number of operations is set to be equalized arbitrarily. When the process proceeds to the last state, in this embodiment, 19 operations are performed immediately before the last state, and 19 processes are performed even in the last state. In this case, the entropy encoding device 10 needs only to implement n = 19 arithmetic blocks in the encoding unit 38 at the maximum. As a result, the entropy encoding device 10 can reduce the size of the circuit configuration to almost half. The absolute delay in this case is for one state, but the circuit scale is reduced to half. Further, in the case of a two-state delay in which the delay circuit 44 delays another state, the entropy encoding device 10 can reduce the circuit scale to 1/3.

  Although the delay circuit 44 is disposed in the state output unit 16, the delay circuit 44 is not limited to this embodiment, and is not limited to the state output unit 16 and the encoding operation unit 20 or in the encoding operation unit 20. It may be arranged on the receiving side.

  The entropy encoding apparatus conventionally uses 64 calculation blocks in the encoding calculation unit 20 in order to accurately calculate 64 pieces of block data. However, the entropy encoding apparatus 10 to which the present invention is applied requires only 37 arithmetic blocks in the configuration of FIG. 1, and only 19 arithmetic blocks in the configuration of FIG. The entropy encoding device 10 is desirably designed by setting a delay and a circuit scale in accordance with the specifications of the device to be applied.

  By configuring as described above, it is possible to realize a desired throughput with a small absolute delay and an increase in circuit scale.

It is a block diagram which shows the schematic structure in the entropy encoding apparatus to which the encoding apparatus which concerns on this invention is applied. It is a figure explaining the order and direction which should read the data in the calculation in the encoding calculating part of FIG. It is a figure explaining the relationship between the register number of the data register part of FIG. 1, and the output from a state output part. It is a figure explaining the data reading direction in a primary and secondary calculation. It is a figure which shows the relationship between the reading of the state in the entropy encoding apparatus of FIG. 1, and a processing amount. It is a block diagram which shows the schematic structure which reduces the circuit scale of the entropy encoding apparatus shown in FIG.

Explanation of symbols

10 Entropy encoder
12 Data register
14 Read controller
16-state output section
18-state output controller
20 Encoding operation part

Claims (2)

In an encoding apparatus for calculating and encoding a quantized transform coefficient obtained by transforming supplied first data as second data in a first direction, the apparatus includes:
Storage means for accumulating second data;
A read control means for generating a read control signal for reading a plurality of second data read from the storage means in a second direction different from the first direction in a predetermined unit;
Output means for outputting second data in the predetermined unit in response to the read control signal;
An encoding device comprising: encoding means for calculating the supplied second data in the order read in the first direction. 2. The apparatus according to claim 1, wherein said apparatus includes delay means for delaying second data from said output means for a predetermined time,
The encoding device characterized in that the delay means is disposed between the output means or between the output means and the encoding means.

Images