JP5519951B2 - Array processor - Google Patents

Description

  The present invention relates to an array processor, and more specifically, processing elements that perform product-sum operation processing are arranged in each axial direction to form a conceptual three-dimensional arrangement state, and input terminals provided in each processing element; The present invention relates to an array processor in which output terminals provided in other adjacent processing elements are connected in a torus shape corresponding to the axial direction.

  Conventionally, two-dimensional orthogonal transformation processing is known as a processing method for converting an image from spatial coordinates to frequency coordinates. This two-dimensional orthogonal transformation process is a transformation process that is very frequently used in today's advanced digital technology. For example, it is often used in an image compression technique such as JPEG or a moving picture compression technique. Furthermore, considering the time axis, three-dimensional orthogonal transformation for converting three-dimensional data into frequency coordinates has also been considered for application to moving image compression.

The following formula (1) represents a mathematical formula used for general three-dimensional discrete orthogonal transform processing.

Here, n ₁ , n ₂ and n ₃ are integer values of 0 or more and n−1 or less (that is, 0 ≦ n ₁ ≦ n−1, 0 ≦ n ₂ ≦ n−1, 0 ≦ n ₃ ≦ n−). 1), and k ₁ , k ₂ , and k ₃ are integer values of 0 or more and n−1 or less (that is, 0 ≦ k ₁ ≦ n−1, 0 ≦ k ₂ ≦ n−1, 0 ≦ k ₃ ≦). n-1). C (n ₁ , k ₁ ), C (n ₂ , k ₂ ), and C (n ₃ , k ₃ ) indicate a two-dimensional coefficient matrix having a size of n × n, and X (n ₁ , n ₂ , n ₃ ) represents a three-dimensional input data matrix of size n × n × n, and Y (k ₁ , k ₂ , k ₃ ) is a matrix representing data after three-dimensional orthogonal transformation of size n × n × n. .

By changing the specific values recorded in C (n ₁ , k ₁ ), C (n ₂ , k ₂ ), C (n ₃ , k ₃ ) In addition to the discrete cosine transform (DCT: Discrete Cosine Transform) adopted in JPEG, for example, Walsh-Hadamard Transform (WHT), Discrete Fourier Transform (DFT) ) And discrete sine transform (DST: Discrete Sine Transform).

  When such a three-dimensional discrete orthogonal transformation process is performed using a computer, it is necessary to access the coefficient C and the input data X stored in the memory many times in an insecticidal manner, resulting in the occurrence of a huge amount of data access. Therefore, there is a problem that it is difficult to increase the processing speed. In order to avoid such a problem, a method has been proposed in which three one-dimensional discrete orthogonal transform dedicated circuits are used and connected to each other to realize three-dimensional discrete orthogonal transform processing (see, for example, Patent Document 1). ).

US Pat. No. 5,126,962

The method described in Patent Document 1 described above corresponds to a method in which calculation is advanced in order while changing only one of the variables n ₁ , n ₂ , and n ₃ shown in Equation (1). When this method is used, in order to perform the discrete orthogonal transform process in the next axial direction after the discrete orthogonal transform process in one axial direction is completed, the order in which data or coefficient data during calculation is input to the circuit is changed. It is necessary to adjust and perform multiplication processing of each data. For this reason, when the method shown in Patent Document 1 is used, it is necessary to provide a dedicated circuit for adjusting the order in which data during calculation or coefficient data is input to the circuit (see, for example, FIG. 5 of Patent Document 1). .) By providing a dedicated circuit for data adjustment in this way, it is possible to improve the processing speed in the discrete orthogonal transform process, but there is a problem that the circuit configuration of the array processor becomes complicated. .

  In addition, a method of performing a three-dimensional discrete orthogonal transform using an array processor composed of a plurality of processing elements is also considered, but the data and coefficient matrix elements stored inside the processing elements during the calculation of each dimension are considered. There is a problem that it is necessary to exchange the processing elements many times using a complicated wiring structure in which the processing elements are connected to each other.

  Moreover, since the exchange of matrix elements is not limited to between adjacent processing elements, if there is a restriction in the wiring structure between the processing elements, it is necessary to exchange data via several processing elements. As a result, there is a problem that the processing load in the arithmetic processing increases.

Furthermore, such a problem also occurs in the inverse transformation process (three-dimensional inverse discrete orthogonal transformation) of the three-dimensional discrete orthogonal transformation shown in Expression (2).

  The present invention has been made in view of the above problems, and without performing data replacement work in the middle of calculation or installing a dedicated circuit for the replacement work, three-dimensional orthogonal transformation and three-dimensional inverse orthogonal It is an object of the present invention to provide an array processor that can execute conversion quickly.

  In order to solve the above problems, an array processor according to the present invention forms a conceptual three-dimensional arrangement state by arranging n processing elements each having a product-sum operation function in three axial directions. For each processing element, three sets of input terminals and output terminals associated with the axial direction are provided in association with each axial direction, and the axial direction of one processing element arranged adjacently in the same axial direction By connecting the input terminal of the processing element and the output terminal of the other processing element in the axial direction, the three input terminals and the output terminal of each processing element are connected in a torus shape corresponding to the axial direction, and each processing element is connected. In the element, the calculation result obtained by performing the product-sum operation based on the product-sum operation function is processed in one axial direction. Output from the output terminal to the other processing element adjacent in the one axial direction, and the calculation data used when the product-sum operation is performed from the output terminal corresponding to the other axial direction to the other axial direction. For a processing element that is output to another adjacent processing element, and the calculation result and calculation data are acquired from other processing elements adjacent to each other in different axial directions, the product sum is obtained using the acquired calculation result and calculation data. By performing the calculation and outputting the calculation result based on the product-sum calculation and the calculation data to the other processing elements adjacent in the respective axial directions from the output terminals corresponding to the acquired input terminals, First in all processing elements connected in a torus in the axial direction The n times of the product-sum operation processes in the period are executed in synchronization with each other, and after each of the n times of the product-sum operation processes in the first period, each processing element has an axial direction of the output terminal that outputs the operation result And changing the axial direction of the output terminal that outputs the calculation data in response to the change in the axial direction, and executing n times of the product-sum calculation processes in the second period in synchronization with each other, After the nth product-sum operation processing in the second cycle, each processing element changes the axial direction of the output terminal that outputs the calculation result to a different axial direction from the first cycle and the second cycle. In addition, the axial direction of the output terminal that outputs the calculation data corresponding to the change in the axial direction is changed to an axial direction different from the first period and the second period, and the product of n times in the third period Execute sum calculation processing in synchronization with each other And performing a three-dimensional orthogonal transformation process.

  Thus, in the array processor according to the present invention, since the input / output terminals of the processing elements are connected in a torus shape corresponding to the axial direction, the operation result associated with the product-sum operation processing and the operation data used for the operation processing Are sequentially sent to other processing elements adjacent to each other in different axial directions (sequentially propagating like a relay), and each processing element can be individually operated. Therefore, n product-sum operations can be performed along the axial direction by performing the arithmetic processing n times while sending the calculation result in n processing elements arranged in the axial direction.

  In order to perform orthogonal transformation processing, it is necessary to perform calculation processing by adjusting the input order of calculation results, calculation data, and the like for convenience of data multiplication. The first cycle (first time) After the above calculation process is performed, the data input order can be easily changed by changing the axial direction in which the feed is performed. For this reason, there is no need to provide a dedicated circuit for adjusting the data input order as in a conventional array processor, and it is possible to perform orthogonal transform processing without directly performing data replacement work. It becomes.

  In particular, in the array processor according to the present invention, a conceptual three-dimensional arrangement state is formed by n processing elements arranged in three axial directions, and each processing element corresponds to each axial direction. Since three attached input / output terminals are provided, it is possible to perform n product-sum operation processing over three cycles. For this reason, it is possible to perform the three-dimensional orthogonal transformation process quickly, surely and simply without directly performing the above-described data replacement process.

  In the array processor according to the present invention, it is only necessary that the processing elements form a conceptual three-dimensional arrangement state, and therefore it is not always necessary to form a physical three-dimensional shape. For example, a conceptual three-dimensional arrangement state may be formed in a planar arrangement state by providing three axes in a planar shape.

  Further, in the array processor, each processing element has one operand value storage means for storing operand values used for the product-sum operation, and the calculation result or the calculation input via the input terminal. Three input information storage means for storing data, three constant value storage means for storing constant values determined in accordance with the calculation method by the product-sum calculation function, the calculation result, the calculation data, and the target An arithmetic processing means for performing a product-sum operation using either an arithmetic value or the constant value, and information input from any of the three input terminals is stored in the input information storage means or the operand value storage means. An input switch means for guiding to any one of the three output terminals, and the calculation data and the calculation result obtained by the product-sum calculation performed by the calculation processing means. Output switch means for outputting, selector means for reading three data from any one of the operand value storage means, the input information storage means, and the constant value storage means, and guiding the data to the arithmetic processing means; Control means for controlling the input switch means, the output switch means, and the selector means, and the control means controls the input switch means when the calculation result is input via the input terminal. Control to guide the calculation result to one of the input information storage means, control the selector means to guide the calculation result read from the input information storage means to the calculation processing means, and in one cycle If n times of arithmetic processing has not yet been performed, the output switch means is controlled to calculate the result of product-sum operation performed by the arithmetic processing means, When the calculation result is output from the axial output terminal corresponding to the input terminal and the nth calculation processing is performed in one cycle, the output switch means is controlled to control the calculation processing means. The calculation result obtained by the product-sum operation may be output from an output terminal in an axial direction different from the input terminal to which the calculation result is input.

  Thus, by providing the processing element with the input information storage means for recording the data acquired via the input terminal and the operation value storage means for storing the operation value, these storage means are In order to record data whose contents are changed in a different cycle, but not changed in the processing of the same period as the storage means (input information storage means) for storing data whose contents have been changed in n product-sum operations It can be used as a storage means. Therefore, the input switch means and the selector means can be controlled according to the control of the control means, and appropriate data can be stored (saved) in the storage means according to the processing process, and stored at an appropriate timing. The (saved) data can be used for product-sum operation processing. As a result, substantial data replacement processing can be performed without providing a dedicated circuit for adjusting the data input order, and orthogonal transformation processing can be performed quickly and easily.

  In addition, since constant value storage means for storing a constant value determined according to the calculation method is provided, various types of three-dimensional orthogonal transformation processing can be performed by changing the constant value according to the calculation method. Can be executed. By appropriately changing the constant value, for example, Walsh-Hadamard transform, discrete Fourier transform, discrete sine transform, etc. can be performed in addition to the discrete cosine transform described in the embodiments described later.

  Further, the control means appropriately controls the input switch means, the selector means, and the output switch means in accordance with the product-sum operation process, thereby appropriately performing n product-sum operation processes over three cycles. Therefore, the three-dimensional orthogonal transformation process can be performed quickly, surely and easily without directly performing the conventional data input order process.

  According to the array processor of the present invention, since the input / output terminals of the processing elements are connected in a torus shape corresponding to the axial direction, the calculation result associated with the product-sum calculation processing and the calculation data used for the calculation processing are obtained. While sequentially sending out to other processing elements adjacent to each other in different axial directions (sequentially propagating like a relay), it is possible to perform arithmetic processing individually in each processing element. Therefore, n product-sum operations can be performed along the axial direction by performing the arithmetic processing n times while sending the calculation result in n processing elements arranged in the axial direction.

  In order to perform orthogonal transformation processing, it is necessary to perform calculation processing by adjusting the input order of calculation results, calculation data, and the like for convenience of data multiplication. The first cycle (first time) After the calculation process is performed, it is possible to easily change the data input order in the second period and the third period by changing the axial direction in which the feeding is performed. Therefore, unlike the conventional array processor, it is not necessary to provide a dedicated circuit for adjusting the data input order, and it is possible to perform orthogonal transform processing without directly performing replacement work or the like.

It is the figure which showed typically the schematic structure of the array processor which concerns on Embodiment 1 and Embodiment 2. FIG. 3 is a block diagram showing a schematic configuration of a processing element according to Embodiment 1. FIG. 6 is a table showing initial values of registers R0 to R6 and contents recorded in each processing step when a three-dimensional discrete cosine transform process is performed using the array processor according to the first embodiment. In the table shown in FIG. 3, the state in which the contents of each register are changed is indicated by an arrow according to the processing step. 6 is a table showing initial values of registers R0 to R6 and contents recorded in each processing step when performing a three-dimensional inverse discrete cosine transform process using the array processor according to the first embodiment. In the table shown in FIG. 5, the state in which the contents of each register are changed is indicated by an arrow according to the processing step. 5 is a block diagram showing a schematic configuration of a processing element according to Embodiment 2. FIG. 10 is a table showing initial values of registers R0 to R6 and contents recorded in each processing step when a three-dimensional discrete cosine transform process is performed using the array processor according to the second embodiment. In the table shown in FIG. 8, the state in which the contents of each register are changed is indicated by an arrow according to the processing step. 10 is a table showing initial values of registers R0 to R6 and contents recorded in each processing step when performing a three-dimensional inverse discrete cosine transform process using the array processor according to the second embodiment. In the table shown in FIG. 10, the state in which the contents of each register are changed is indicated by an arrow according to the processing step.

  Hereinafter, an array processor according to the present invention will be described in detail with reference to the drawings. In Embodiment 1 and Embodiment 2 described later, 3D Discrete Cosine Transform (3D-DCT) and 3D Inverse Discrete Cosine Transform (3D-IDCT) are performed. The array processor to be calculated will be described. However, the array processor according to the present invention is not limited to the one used for the calculation of the three-dimensional discrete cosine transform and the three-dimensional inverse discrete cosine transform. By appropriately changing C in 1), a three-dimensional orthogonal transformation process based on another transformation method can be executed.

[Embodiment 1]
FIG. 1 is a diagram showing an array processor according to the first embodiment. The array processor 1 has eight processing elements PE. Here, the processing element PE is an operation configuration unit of an array processor having a role of performing product-sum operation processing.

  Two processing elements PE are arranged in each of the vertical direction, the horizontal direction, and the height direction (triaxial direction), and each processing element PE is arranged at each vertex of the array processor 1 that forms a rectangular parallelepiped. It is the composition which becomes.

  In the first embodiment, the aforementioned vertical direction is the i-axis direction, the aforementioned horizontal direction is the j-axis direction, and the aforementioned height direction is the k-axis direction. Each processing element PE is expressed by PE (i, j, k) using the coordinate position of ijk space composed of i-axis, j-axis, and k-axis in order to distinguish each processing element PE from other processing elements PE. Identified.

  As shown in FIGS. 1 and 2, each processing element PE includes three input terminals (i input terminal, j input terminal, k input terminal) provided in the −i axis direction, the −j axis direction, and the k axis direction. , And three output terminals (i output terminal, j output) provided in pairs with each input terminal (i input terminal, j input terminal, k input terminal) in the i axis direction, j axis direction, and -k axis direction, respectively. Terminal, k output terminal).

  Each output terminal is connected to an opposing input terminal (provided in the coaxial direction) of the processing element PE adjacent in the installation direction (axial direction) of the respective output terminal. For example, an i output terminal provided in the PE (1, 0, 1) direction in the −i axis direction is connected to an i input terminal provided in the PE (0, 0, 1) direction in the i axis direction.

  When there is no other processing element PE in the opposing direction, the input terminal and the output terminal of the processing element PE located at both ends of the arrangement positions along the respective axial directions are connected, so that A torus is formed by connecting input terminals and output terminals provided in a direction.

  Therefore, the processing elements PE aligned in the i-axis direction can output data from the i output terminal to the i input terminal of another processing element PE adjacent in the −i axis direction. A processing element existing at a spatial position where the i coordinate is 0 connects its i output terminal to the i input terminal of the processing element located on the other end side in the i-axis direction, and outputs data. It is possible. This structure is also the same in the processing elements PE aligned in the j-axis direction and the k-axis direction, respectively.

  In this way, in the processing elements PE arranged in the three-dimensional space, data can be sequentially output to the adjacent processing elements PE aligned in the corresponding axial direction. For this reason, the array processor 1 sequentially relays data of calculation results calculated in adjacent processing elements PE, predetermined data used for the calculation, and the like to other adjacent processing elements PE to perform continuous product-sum operations. Processing can be performed by the entire array processor 1.

  FIG. 2 is a block diagram showing an internal configuration of each processing element PE. The processing element PE has seven registers R0 to R6, an input switch unit 4, a selector unit 5, an arithmetic circuit unit 6, an output switch unit 7, and a control circuit unit 8.

  The registers R0 to R6 can record data used for the three-dimensional orthogonal transformation process. In the register R4, the register R5, and the register R6, the data C shown in Expression (1) is recorded. This C is an initial value determined according to the processing method for performing the calculation when performing the three-dimensional orthogonal transformation process using the array processor 1 according to the first embodiment. For example, it is possible to perform operations such as discrete cosine transform (DCT), Walsh Hadamard transform (WHT), discrete Fourier transform (DFT), and discrete sine transform (DST).

  In the array processor 1 according to the first embodiment, an initial value (DCT coefficient (fixed value)) suitable for three-dimensional discrete cosine transform (3D-DCT) is set. Specifically, the value of C (i, k) described below is recorded as an initial value in R4 of each processing element, and the value of C (k, j) described below is recorded as an initial value in register R5. The value of C (i, j) described below is recorded as an initial value in the register R6.

が記録される。ここで、ｎは各軸方向に向けて配設されたプロセッシングエレメントＰＥの個数を示しており、実施の形態１では、ｉ軸方向、ｊ軸方向、ｋ軸方向のそれぞれに対して２個ずつプロセッシングエレメントが配設されているため、以下、ｎは２（ｎ＝２）となる。 More specifically, processing element PE (i, j, k) where i = 0 and 0 ≦ k ≦ n−1 at the coordinate position (i, j, k) of the arrangement position of processing element PE. ) Register R4

Is recorded. Here, n indicates the number of processing elements PE arranged in each axial direction, and in the first embodiment, two each for the i-axis direction, the j-axis direction, and the k-axis direction. Since the processing element is provided, n is 2 (n = 2) below.

が記録される。 Next, the register R4 of the processing element PE (i, j, k) where 1 ≦ i ≦ n−1 and 0 ≦ k ≦ 1

Is recorded.

が記録され、また、１≦ｋ≦ｎ−１であり、かつ、０≦ｊ≦ｎ―１であるプロセッシングエレメントＰＥ（ｉ，ｊ，ｋ）のレジスタＲ５には、

が記録される。 Further, the register R5 of the processing element PE (i, j, k) where k = 0 and 0 ≦ j ≦ n−1 holds

Is stored in the register R5 of the processing element PE (i, j, k) where 1 ≦ k ≦ n−1 and 0 ≦ j ≦ n−1.

Is recorded.

が記録され、また、１≦ｉ≦ｎ−１であり、かつ、０≦ｊ≦ｎ―１であるプロセッシングエレメントＰＥ（ｉ，ｊ，ｋ）のレジスタＲ６には、

が記録される。 Furthermore, the register R6 of the processing element PE (i, j, k) where i = 0 and 0 ≦ j ≦ n−1 is

Is stored in the register R6 of the processing element PE (i, j, k) where 1 ≦ i ≦ n−1 and 0 ≦ j ≦ n−1.

Is recorded.

  It should be noted that the set values (constant values) of the above-described equations (3) to (8) recorded in the registers R4 to R6 are not changed until the calculation process is completed, and the same value is maintained.

  Next, 0 is recorded as an initial value in the registers R1, R2, and R3. The register R0 records three-dimensional input data for performing the three-dimensional discrete cosine transform processing, specifically, the value of X (i, j, k) in the above-described equation (1). As shown in FIG. 2, data may be guided to the registers R0 to R3 via the input switch unit 4. In this case, new data is overwritten and saved in the registers R0 to R3. Therefore, there is a possibility that data recorded in accordance with the arithmetic processing is changed. For this reason, in the registers R0 to R3, the calculation result or the setting value used for the calculation can be sequentially changed according to the progress of the calculation process. Then, as will be described later, the calculation result of the three-dimensional orthogonal transformation process finally calculated by the array processor 1 is recorded in the register R3.

  The input switch unit 4 switches information input from three input terminals (i input terminal, j input terminal, k input terminal) in accordance with an instruction from the control circuit unit 8 to any one of the registers R0 to R3. It has a role to guide and record. Data that is actually input via the input terminal is input via any two of the three input terminals (i input terminal, j input terminal, k input terminal). The control circuit unit 8 determines the input information according to the type of the input terminal and controls the input switch unit 4 to transfer the input data to the corresponding register (any one of the registers R0 to R3). Guide and record.

  The selector unit 5 acquires data used for arithmetic processing of the arithmetic circuit unit 6 from any three of the registers R0 to R6 and outputs the data to the arithmetic circuit unit 6. The selector unit 5 outputs the acquired three data to three input terminals (a input terminal, b input terminal, and c input terminal) provided according to the calculation contents of the arithmetic circuit unit 6. The data output to the b input terminal is input to the arithmetic circuit unit 6 via the b input terminal and is output to the output switch unit 7 as it is. In the selector unit 5, from which register (three of the registers R0 to R6) data is acquired, and whether the acquired data is output to the a input terminal, b input terminal, or c input terminal The determination process is performed according to an instruction from the control circuit unit 8.

  The arithmetic circuit unit 6 performs a product-sum operation based on the data a acquired from the a input terminal, the data b acquired from the b input terminal, and the data c acquired from the c input terminal. The product-sum operation is obtained by d = a × b + c, where d is the operation result. The calculation result d is output to the output switch unit 7 via the output terminal 10 of the calculation circuit unit 6.

  The output switch unit 7 acquires the data b output from the selector unit 5 to the b input terminal of the arithmetic circuit unit 6 and the arithmetic result d output via the output terminal 10 of the arithmetic circuit unit 6, In accordance with an instruction from the control circuit unit 8, the data b and the operation result d are output from any of the three output terminals (i output terminal, j output terminal, k output terminal). Actually, the data output through the output terminal is only two of the three output terminals (i output terminal, j output terminal, k output terminal). The control circuit unit 8 determines the input data and controls the output switch unit 7 to convert the data b and the operation result d into the corresponding output terminals (i output terminal, j output terminal, k output terminal). To either).

  The control circuit unit 8 has a role of performing operation control of the input switch unit 4, the selector unit 5, and the output switch unit 7 described above. The control circuit unit 8 determines the data input to the input switch unit 4, the selector unit 5, and the output switch unit 7 according to the content and the type of input terminal input, and according to the processing content of the array processor 1. The input switch unit 4, the selector unit 5, and the output switch unit 7 are controlled.

  Although not shown in FIG. 2, input data for performing the three-dimensional discrete cosine transform processing on the register R0 is input to each processing element PE, and initial values are input to the registers R1 to R3. 0, and data input means for inputting initial values C (i, k), C (k, j), C (i, j) to the registers R4 to R6, and final calculation Data acquisition means for acquiring data from the register R3 in which the result is recorded is provided.

  Next, a process in which the control circuit unit 8 of each processing element PE performs a three-dimensional discrete cosine transform process (3D-DCT process) by appropriately controlling the input switch unit 4, the selector unit 5, and the output switch unit 7. Will be explained.

  FIG. 3 is a table showing registers in which the initial values of the registers R0 to R6 and the contents recorded in the processing steps in each processing element PE (i, j, k) are used or changed. Reference numeral 4 denotes a state in which the contents of the register shown in FIG. 3 are changed by arrows according to processing steps. 4 indicates the output state of data corresponding to data b described later, and the solid arrow indicates the output state of data corresponding to calculation result d described later.

  After the initial values of the registers R0 to R6 are set, the control circuit unit 8 of each processing element PE controls the selector unit 5 so that the data recorded in the register R4 is stored in the a of the arithmetic circuit unit 6. A process of outputting to the input terminal, outputting the data recorded in the register R0 to the b input terminal of the arithmetic circuit unit 6, and outputting the data recorded in the register R1 to the c input terminal of the arithmetic circuit unit 6 is executed. In this process, as shown in FIGS. 3 and 4, the data recorded in the register R4 is an initial value of C (i, k), and the data recorded in the register R0 is subjected to a three-dimensional discrete cosine transform process. Is input data: X (i, j, k), and the data recorded in the register R1 has an initial value of 0.

  The arithmetic circuit unit 6 of each processing element PE uses the data of the register R4 input as the data a, the data of the register R0 input as the data b, and the data of the register R1 input as the data c. A product-sum operation (operation of d = a × b + c) is executed.

  Next, the control circuit unit 8 of each processing element PE controls the output switch unit 7 to acquire the calculation result d and data b, and outputs the calculation result d to the k input terminal of the processing element PE adjacent in the k-axis direction. In addition, the data b (specifically, the data recorded in the register R0) is output to the i input terminal of the processing element PE adjacent in the −i axis direction.

  Then, the control circuit unit 8 of each processing element PE controls the input switch unit 4 to obtain the operation result d from the adjacent processing element PE through the k input terminal, and the data b ( And the operation result d is recorded in the register R1, and the data b (data in the register R0) is recorded in the register R0.

  In this way, the control circuit unit 8 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the first embodiment, twice), a path connected in a torus shape by connecting the i input terminal and the i output terminal, and the k input terminal and the k output terminal The calculation processing result and the predetermined data are made a round along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the first period.

  By repeating this process n times, the result of product-sum operation is recorded in all the processing elements PE arranged in the k-axis direction in the register R1 of each processing element PE. In the first embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “0” and “1” shown in FIG. 3 and FIG. 4 indicate the processing contents corresponding to the above-described two processes.

  Subsequently, the control circuit unit 8 of each processing element PE controls the selector unit 5 to output the data recorded in the register R5 to the a input terminal of the arithmetic circuit unit 6, and the data recorded in the register R1. A process of outputting to the b input terminal of the arithmetic circuit unit 6 and outputting the data recorded in the register R2 to the c input terminal of the arithmetic circuit unit 6 is executed. In this processing, the data recorded in the register R5 is the initial value of C (k, j), and the data recorded in the register R1 is sum of products in all the processing elements PE arranged in the k-axis direction. The calculated result and the data recorded in the register R2 has an initial value of 0.

  The arithmetic circuit unit 6 of each processing element PE uses the data of the register R5 input as the data a, the data of the register R1 input as the data b, and the data of the register R2 input as the data c. A product-sum operation (operation of d = a × b + c) is executed.

  Next, the control circuit unit 8 of each processing element PE controls the output switch unit 7 to acquire the operation result d and data b, and the operation result d is j input terminal of the processing element PE adjacent in the −j axis direction. The data b (specifically, data recorded in the register R1) is output to the k input terminal of the processing element PE adjacent in the k-axis direction.

  Then, the control circuit unit 8 of each processing element PE controls the input switch unit 4 to obtain the calculation result d from the adjacent processing element PE through the j input terminal, and the data b ( (Register R1 data) is acquired, the operation result d is recorded in the register R2, and the data b (data in the register R1) is recorded in the register R1.

  In this way, the control circuit unit 8 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the first embodiment, twice), a path connected in a torus shape by connecting the j input terminal and the j output terminal, and the k input terminal and the k output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the second period.

  By repeating this processing n times, the result of product-sum operation in all the processing elements PE arranged in the k-axis direction (n-th product in the first cycle) is stored in the register R2 of each processing element PE. Based on the register R1 that is the result of the sum operation process, the result of the product-sum operation on all the processing elements PE arranged in the j-axis direction (by the nth product-sum operation process in the second period) (Operation result) is recorded, and the result of the product-sum operation in all the processing elements arranged in the k-axis direction is recorded in the register R1. In the first embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “2” and “3” shown in FIG. 3 and FIG. 4 indicate the processing contents corresponding to the above-described two processes.

  Subsequently, the control circuit unit 8 of each processing element PE controls the selector unit 5 to output the data recorded in the register R6 to the a input terminal of the arithmetic circuit unit 6, and the data recorded in the register R2 A process of outputting to the b input terminal of the arithmetic circuit unit 6 and outputting the data recorded in the register R3 to the c input terminal of the arithmetic circuit unit 6 is executed. In this processing, the data recorded in the register R6 is the initial value of C (i, j), and the data recorded in the register R2 is sum of products in all the processing elements PE arranged in the k-axis direction. On the basis of the calculated calculation result (the calculation result by the n-th product-sum calculation process in the first period), the calculation result (second calculation) performed by all the processing elements PE arranged in the j-axis direction The data recorded in the register R3 is an initial value of 0.

  The arithmetic circuit unit 6 of each processing element PE uses the data of the register R6 input as the data a, the data of the register R2 input as the data b, and the data of the register R3 input as the data c. A product-sum operation (operation of d = a × b + c) is performed.

  Next, the control circuit unit 8 of each processing element PE controls the output switch unit 7 to acquire the operation result d and data b, and the operation result d is input to the i of the processing element PE adjacent in the −i axis direction. The data b (specifically, data recorded in the register R2) is output to the j input terminal of the processing element PE adjacent in the −j axis direction.

  Then, the control circuit unit 8 of each processing element PE controls the input switch unit 4 to acquire the operation result d from the adjacent processing element PE through the i input terminal, and the data b ( The data (register R2 data) is acquired and the operation result d is recorded in the register R3, and the data b (data in the register R2) is recorded in R2.

  In this way, the control circuit unit 8 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the first embodiment, twice), a path connected in a torus shape by connecting the i input terminal and the i output terminal, and the j input terminal and the j output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the third period.

  As a result of repeating this process n times, the register R3 of each processing element PE stores the result of the product-sum operation in all the processing elements PE arranged in the k-axis direction (nth product in the first period). The product-sum operation results of all the processing elements PE arranged in the j-axis direction that have undergone product-sum operation based on the result of the operation of the sum operation processing (operation results of the n-th product-sum operation processing in the second period) Is used to record the calculation results (calculation results of the nth product-sum calculation processing in the third period) performed by all the processing elements PE arranged in the i-axis direction, and the register R2 stores k Based on the result of the product-sum operation in all the processing elements PE arranged in the axial direction (the operation result by the n-th product-sum operation processing in the first period), the j-axis Product-sum computed operation results in all processing elements PE arranged in direction (calculation result by n multiply and sum operation of the second round eyes) is to be recorded. In the first embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “4” and “5” shown in FIG. 3 and FIG. 4 indicate the processing contents corresponding to the above-described two processes.

  In this way, in the array processor 1 according to the first embodiment, the operation result and the predetermined data used for the product-sum operation are sequentially output to the adjacent processing elements PE, and the product-sum operation processing is performed in each processing element PE. The output of the calculation result to the adjacent processing element PE is sequentially processed by changing the output direction to the k-axis direction, the j-axis direction, and the i-axis direction. The calculation result can be recorded in the register R3. Therefore, unlike the conventional array processor, it is not necessary to provide a dedicated circuit for adjusting the input order of data and coefficient data during the calculation, and the circuit configuration can be simplified. Further, since the three-dimensional discrete cosine transform process (three-dimensional orthogonal transform process) can be performed by sequentially outputting the calculation result to the adjacent processing element PE, the calculation element PE can be inserted inside the processing element PE during the calculation of each dimension. The stored data and coefficient matrix elements do not need to be exchanged many times using a complicated wiring structure as in the prior art, and the processing can be speeded up and simplified.

  As described above, by using the array processor 1 according to the first embodiment, it is not necessary to perform replacement work between data during calculation, which is essential in the conventional configuration. In addition, by connecting a plurality of processing elements PE and sequentially performing calculation result processing, three-dimensional discrete cosine transform processing (three-dimensional discrete orthogonal transform processing) can be performed quickly, and the circuit configuration is further complicated. It becomes possible to suppress.

  Next, a method for calculating the three-dimensional inverse discrete cosine transform (3D-IDCT) using the array processor 1 described above will be described. FIG. 5 is a table showing the initial values of the registers R0 to R6 and the registers recorded in each processing step in each processing element PE (i, j, k), and FIG. 6 is shown in FIG. The state in which the contents of the registers are changed is indicated by arrows according to the processing steps. 6 indicates the output state of the data corresponding to the data b used in the calculation process, and the solid line arrow indicates the output state of the data corresponding to the calculation result d.

  When performing the three-dimensional inverse discrete cosine transform, the following C (k, j), C (i) are used as fixed values (IDCT coefficients (fixed values)) for the three-dimensional inverse discrete cosine transform in Equation (2). , K) and C (i, j) are used, and the respective values are recorded as initial values in the registers R4, R5 and R6.

が記録される。ここで、ｎは各軸方向に向けて配設されたプロセッシングエレメントＰＥの個数を示しており、実施の形態１では、以下、ｎ＝２となる。 More specifically, the processing element PE (i, j, k) where k = 0 and 0 ≦ j ≦ n−1 at the coordinate position (i, j, k) of the processing element PE. ) Register R4

Is recorded. Here, n indicates the number of processing elements PE arranged in the respective axial directions, and in the first embodiment, n = 2 hereinafter.

が記録される。 Next, in the register R4 of the processing element PE (i, j, k) where 1 ≦ k ≦ n−1 and 0 ≦ j ≦ n−1,

Is recorded.

が記録され、また、１≦ｉ≦ｎ−１であり、かつ、０≦ｋ≦ｎ―１であるプロセッシングエレメントＰＥ（ｉ，ｊ，ｋ）のレジスタＲ５には、

が記録される。 Further, the register R5 of the processing element PE (i, j, k) where i = 0 and 0 ≦ k ≦ n−1 includes

Is stored in the register R5 of the processing element PE (i, j, k) where 1 ≦ i ≦ n−1 and 0 ≦ k ≦ n−1.

Is recorded.

が記録され、また、１≦ｉ≦ｎ−１であり、かつ、０≦ｊ≦ｎ―１であるプロセッシングエレメントＰＥ（ｉ，ｊ，ｋ）のレジスタＲ６には、

が記録される。 Furthermore, the register R6 of the processing element PE (i, j, k) where i = 0 and 0 ≦ j ≦ n−1 is

Is stored in the register R6 of the processing element PE (i, j, k) where 1 ≦ i ≦ n−1 and 0 ≦ j ≦ n−1.

Is recorded.

  Also, 0 is recorded as an initial value in the registers R1, R2, and R3, and three-dimensional input data for performing the three-dimensional inverse discrete cosine transform processing, specifically, the above-described equation (2) is stored in the register R0. Y (i, j, k) values are recorded.

  After the initial values of the registers R0 to R6 are set, the control circuit unit 8 of each processing element PE controls the selector unit 5 to input the data recorded in the register R4 to the a input of the arithmetic circuit unit 6. A process of outputting data to the terminal, outputting data recorded in the register R0 to the b input terminal of the arithmetic circuit unit 6, and outputting data recorded in the register R1 to the c input terminal of the arithmetic circuit unit 6 is executed. In this process, the data recorded in the register R4 is an initial value of C (k, j), and the data recorded in the register R0 is input data Y (i for performing the three-dimensional inverse discrete cosine transform process. , J, k), and the data recorded in the register R1 has an initial value of 0.

  The arithmetic circuit unit 6 of each processing element PE uses the data of the register R4 input as the data a, the data of the register R0 input as the data b, and the data of the register R1 input as the data c. A product-sum operation (operation of d = a × b + c) is performed.

  Next, the control circuit unit 8 of each processing element PE controls the output switch unit 7 to obtain the calculation result d and data b, and the calculation result d is applied to the k input terminal of the processing element PE adjacent in the k-axis direction. Further, data b (specifically, data recorded in the register R0) is output to the j input terminal of the processing element PE adjacent in the −j axis direction.

  Then, the control circuit unit 8 of each processing element PE controls the input switch unit 4 to obtain the operation result d from the adjacent processing element PE through the k input terminal, and the data b ( (Register R0 data) is acquired, the operation result d is recorded in the register R1, and the data b (data in the register R0) is recorded in the register R0.

  In this way, the control circuit unit 8 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (twice in the first embodiment), a path connected in a torus shape by connecting the k input terminal and the k output terminal, and the j input terminal and the j output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the first period.

  By repeating this processing n times, the result of product-sum operation in all the processing elements PE arranged in the k-axis direction (nth product in the first cycle) is stored in the register R1 of each processing element PE. The calculation result by the sum calculation process) is recorded. In the first embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “0” and “1” shown in FIG. 5 and FIG. 6 indicate processing contents corresponding to the above-described two processes.

  Subsequently, the control circuit unit 8 of each processing element PE controls the selector unit 5 to output the data recorded in the register R5 to the a input terminal of the arithmetic circuit unit 6, and the data recorded in the register R1. A process of outputting to the b input terminal of the arithmetic circuit unit 6 and outputting the data recorded in the register R2 to the c input terminal of the arithmetic circuit unit 6 is executed. In this processing, the data recorded in the register R5 is the initial value of C (i, k), and the data recorded in the register R1 is sum of products in all the processing elements PE arranged in the k-axis direction. The calculated result and the data recorded in the register R2 has an initial value of 0.

  The arithmetic circuit unit 6 of each processing element PE uses the data of the register R5 input as the data a, the data of the register R1 input as the data b, and the data of the register R2 input as the data c. A product-sum operation (operation of d = a × b + c) is executed.

  Next, the control circuit unit 8 of each processing element PE controls the output switch unit 7 to acquire the calculation result d and data b, and the calculation result d is input to the i input terminal of the processing element PE adjacent in the -i axis direction. The data b (specifically, data recorded in the register R1) is output to the k input terminal of the processing element PE adjacent in the k-axis direction.

  Then, the control circuit unit 8 of each processing element PE controls the input switch unit 4 to acquire the operation result d from the adjacent processing element PE through the i input terminal, and the data b ( (Register R1 data) is acquired, the operation result d is recorded in the register R2, and the data b (data in the register R1) is recorded in the register R1.

  In this way, the control circuit unit 8 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the first embodiment, twice), a path connected in a torus shape by connecting the i input terminal and the i output terminal, and the k input terminal and the k output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the second period.

  By repeating this processing n times, the result of product-sum operation in all the processing elements PE arranged in the k-axis direction (n-th product in the first cycle) is stored in the register R2 of each processing element PE. Based on the register R1 which is the result of the sum operation process, the result of the product-sum operation on all the processing elements PE arranged in the i-axis direction (by n product-sum operation processes in the second period) (Operation result) is recorded, and the result of product-sum operation in all the processing elements PE arranged in the k-axis direction is recorded in the register R1. The processing steps “2” and “3” shown in FIG. 5 and FIG. 6 indicate processing contents corresponding to the above-described two processings.

  Subsequently, the control circuit unit 8 of each processing element PE controls the selector unit 5 to output the data recorded in the register R6 to the a input terminal of the arithmetic circuit unit 6, and the data recorded in the register R2 A process of outputting to the b input terminal of the arithmetic circuit unit 6 and outputting the data recorded in the register R3 to the c input terminal of the arithmetic circuit unit 6 is executed. In this processing, the data recorded in the register R6 is the initial value of C (i, j), and the data recorded in the register R2 is sum of products in all the processing elements PE arranged in the k-axis direction. Based on the calculated calculation result (the calculation result by the n-th product-sum calculation processing in the first cycle), the calculation result (second calculation) performed by all the processing elements PE arranged in the i-axis direction The data recorded in the register R3 is an initial value of 0.

  The arithmetic circuit unit 6 of each processing element PE uses the data of the register R6 input as the data a, the data of the register R2 input as the data b, and the data of the register R3 input as the data c. A product-sum operation (operation of d = a × b + c) is performed.

  Next, the control circuit unit 8 of each processing element PE controls the output switch unit 7 to acquire the operation result d and data b, and the operation result d is input to the j of the processing element PE adjacent in the −j axis direction. The data b (specifically, data recorded in the register R2) is output to the i input terminal of the processing element PE adjacent in the -i axis direction.

  Then, the control circuit unit 8 of each processing element PE controls the input switch unit 4 to obtain the operation result d from the adjacent processing element PE through the j input terminal, and to the data b ( The data (register R2 data) is acquired, the operation result d is recorded in the register R3, and the data b (data in the register R2) is recorded in the register R2.

  In this way, the control circuit unit 8 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the first embodiment, twice), a path connected in a torus shape by connecting the j input terminal and the j output terminal, and the i input terminal and the i output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the third period.

  As a result of repeating this process n times, the register R3 of each processing element PE stores the result of the product-sum operation in all the processing elements PE arranged in the k-axis direction (nth product in the first period). The product-sum operation results of all the processing elements PE arranged in the i-axis direction that are product-sum-calculated based on the result of the sum operation processing (operation results of the n-th product-sum operation processing in the second period) Are used to record the calculation results (calculation results of the nth product-sum calculation processing in the third cycle) performed by all the processing elements PE arranged in the j-axis direction, and k is stored in the register R2. Based on the result of the product-sum operation in all the processing elements PE arranged in the axial direction (the operation result by the n-th product-sum operation processing in the first period), the i-axis Product-sum computed operation results in all the processing elements PE arranged in direction (calculation result by n times of product-sum operation processing of the second round eyes) is to be recorded. In the first embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “4” and “5” shown in FIG. 5 and FIG. 6 indicate processing contents corresponding to the above-described two processings.

  In this way, in the array processor 1 according to the first embodiment, the operation result and the predetermined data used for the product-sum operation are sequentially output to the adjacent processing elements PE, and the product-sum operation processing is performed in each processing element PE. The output of the calculation result to the adjacent processing element PE is sequentially processed by changing the output direction to the k-axis direction, the i-axis direction, and the j-axis direction. The calculation result can be recorded in the register R3. Therefore, unlike the conventional array processor 1, it is not necessary to provide a dedicated circuit for adjusting the input order of data and coefficient data during calculation, and the circuit configuration can be simplified. In addition, since the three-dimensional inverse discrete cosine transform process (three-dimensional inverse orthogonal transform process) can be performed by sequentially outputting the calculation results to adjacent processing elements PE, the processing element PE of each dimension is calculated in the middle. It is not necessary to exchange the data and coefficient matrix elements stored in the inside many times using a complicated wiring structure as in the conventional case, and it becomes possible to speed up and simplify the processing.

  As described above, by using the array processor 1 according to the first embodiment, it is not necessary to perform replacement work between data during calculation, which is essential in the conventional configuration. In addition, by connecting multiple processing elements and processing the results sequentially, 3D inverse discrete cosine transform processing (3D inverse discrete orthogonal transform processing) can be executed quickly, and the circuit configuration becomes more complex. Can be suppressed.

[Embodiment 2]
Next, the array processor according to the second embodiment will be described. The array processor 1 according to the second embodiment has the same configuration as the configuration state of the processing elements PE (connection state / arrangement state of each processing element PE) constituting the array processor 1 according to the first embodiment shown in FIG. In this state, the internal structure of the processing element PE constituting the array processor is different.

  FIG. 7 is a diagram schematically showing a schematic configuration of the processing element PE according to the second embodiment. In the processing element PE according to the second embodiment, the data output from the selector unit 15 to the a input terminal of the arithmetic circuit unit 16 is compared with the processing element PE according to the first embodiment (see FIG. 2). The operation circuit unit 16 is different in that it can be output not only to the a input terminal but also to the output switch unit 17. Therefore, the processing element PE according to the second embodiment has a feature that the number of output terminals extended to the output switch unit 17 is one more than that of the processing element PE according to the first embodiment. doing.

  In the array processor 1 according to the second embodiment, a control circuit unit 18 is provided to control the output switch unit 17 and other elements according to the input / output signal from the added a input terminal. . The elements other than the output switch unit 17 and the control circuit unit 18, that is, the input switch unit 14, the selector unit 15, the arithmetic circuit unit 16, and the registers R0 to R6 have the same configuration as the processing element PE according to the first embodiment. is there.

  A method of performing a three-dimensional discrete cosine transform process (3D-DCT process) using the array processor of this configuration will be described.

  First, values obtained based on Expressions 3 to 8 are set as initial values in the registers R4 to R6 in each processing element PE. These values are constants and are not changed until all calculations are completed. Further, 0 is recorded as an initial value in the registers R1 to R3. Further, in the register R0, three-dimensional input data for performing the three-dimensional discrete cosine transform process (3D-DCT process), specifically, the value of X (m, j, k) in the above-described equation (1) is recorded. Has been. Here, m is a value calculated by m = (− i−j + k) mod_n, and mod_n represents a modulo operation of n. Note that m is a remainder obtained by dividing (−i−j + k) by n, and n indicates the size of the three-dimensional input data n × n × n, that is, the size of the array processor 1. In the processing element PE according to the second embodiment, n = 2 as shown in FIG.

  Furthermore, as shown in FIG. 7, data may be guided to the registers R0 to R3 via the input switch unit 14. In this case, new data is overwritten and saved in the registers R0 to R3. End up. For this reason, as will be described later, in the registers R0 to R3, there is a possibility that the data recorded in accordance with the calculation process may be changed, and the calculation result or the setting used for the calculation depending on the progress of the calculation process. The value is changed sequentially. Finally, the calculation result of the three-dimensional discrete cosine transform process (3D-DCT process) calculated by the array processor 1 is recorded in the register R3.

  The input switch unit 14 switches the three input terminals (i input terminal, j input terminal, k input terminal) in accordance with an instruction from the control circuit unit 18, thereby adjacent processing elements PE through the three input terminals. It has a role of guiding and recording the data input more by one of the registers R0 to R3. Data that is actually input via the input terminal is input via any two of the three input terminals (i input terminal, j input terminal, k input terminal). The control circuit unit 18 determines the input information according to the type of the input terminal, and controls the input switch unit 14 to transfer the input data to the corresponding register (one of the registers R0 to R3). Guide and record.

  The selector unit 15 acquires data used for the arithmetic processing of the arithmetic circuit unit 16 from any three of the registers R0 to R6 and outputs the data to the arithmetic circuit unit 16. The selector unit 15 outputs the acquired three data to three input terminals (a input terminal, b input terminal, and c input terminal) provided according to the calculation contents of the arithmetic circuit unit 16. The data output to the a input terminal and the b input terminal is input to the arithmetic circuit unit 16 through the a input terminal and the b input terminal, and is output to the output switch unit 17 as it is. In the selector unit 15, from which register (three registers out of the registers R0 to R6) data is acquired, and whether the acquired data is output to the a input terminal, b input terminal, or c input terminal The determination process is performed according to an instruction from the control circuit unit 18.

  The arithmetic circuit unit 16 performs a product-sum operation based on the data a acquired from the a input terminal, the data b acquired from the b input terminal, and the data c acquired from the c input terminal. The product-sum operation is obtained by d = a × b + c, where d is the operation result. The calculation result d is output to the output switch unit 17 via the output terminal 20 of the calculation circuit unit 16.

  The output switch unit 17 is output from the selector unit 15 to the a input terminal of the arithmetic circuit unit 16, and is further output to the output switch unit 17 via the output terminal 21 and b of the arithmetic circuit unit 16. The data b output to the input terminal and further output to the output switch unit 17 via the output terminal 22 and the calculation result d output to the output switch unit 17 via the output terminal 20 of the arithmetic circuit unit 16 And according to an instruction from the control circuit unit 18, either one of the data a or data b is received from any two terminals of the three output terminals (i output terminal, j output terminal, k output terminal). , And has a role of outputting the calculation result d. Therefore, the data that is actually output through the output terminal is only two of the three output terminals (i output terminal, j output terminal, k output terminal). The control circuit unit 18 determines the input data and controls the output switch unit 17 so that either the data a or the data b and the calculation result d are output to the corresponding output terminals (i output terminals). , J output terminal, or k output terminal).

  The control circuit unit 18 has a role of performing operation control of the input switch unit 14, the selector unit 15, and the output switch unit 17 described above. The control circuit unit 18 determines the data input to the input switch unit 14, the selector unit 15, and the output switch unit 17 according to the content and the type of input terminal input, and according to the processing content of the array processor 1. The input switch unit 14, the selector unit 15, and the output switch unit 17 are controlled.

  Although not shown in FIG. 7, input data for performing the three-dimensional discrete cosine transform processing on the register R0 is input to each processing element PE, and initial values are input to the registers R1 to R3. 0, and data input means for inputting initial values C (i, k), C (k, j), C (i, j) to the registers R4 to R6, and final calculation Data acquisition means for acquiring data from the register R3 in which the result is recorded is provided.

  Next, the control circuit unit 18 of each processing element PE appropriately controls the input switch unit 14, the selector unit 15, and the output switch unit 17, thereby performing a three-dimensional discrete cosine transform process that is one of three-dimensional orthogonal transforms. A process of performing (3D-DCT processing) will be described.

  FIG. 8 is a table showing registers in which the initial values of the registers R0 to R6 and the contents recorded in the processing steps in each processing element PE (i, j, k) are used or changed. X (m, j, k) is set in the register R0. However, a value obtained by m = (− i−j + k) mod — 2 is used as the value of m. For this reason, X (0,0,0) is set in the register R0 of the processing element PE (0,0,0), and X (1,1) is set in the register R0 of the processing element PE (0,1,0). , 0) is set. In addition, X (1, 0, 0) is set in the register R0 of the processing element PE (1, 0, 0), and X (0, 1, 0) is set in the register R0 of the processing element PE (1, 1, 0). 0) is set. Furthermore, X (1, 0, 1) is set in the register R0 of the processing element PE (0, 0, 1), and X (0, 1, 1) is set in the register R0 of the processing element PE (0, 1, 1). 1) is set. In addition, X (0,0,1) is set in the register R0 of the processing element PE (1, 0, 1), and X (1, 1, 1) is set in the register R0 of the processing element PE (1, 1, 1). 1) is set.

  The initial values of the other registers are the same as those described in the first embodiment. FIG. 9 shows a state in which the contents of the registers R0 to R6 shown in FIG. 8 are changed by arrows according to processing steps. In addition, the arrow by the broken line shown in FIG. 9 is one of data a and data b described later, and indicates the output state of data used in the processing described later. Further, solid arrows indicate the output state of data corresponding to the calculation result d described later.

  After the initial values of the registers R0 to R6 are set, the control circuit unit 18 of each processing element PE controls the selector unit 15 to transfer the data recorded in the register R4 to the a of the arithmetic circuit unit 16. A process of outputting to the input terminal, outputting the data recorded in the register R0 to the b input terminal of the arithmetic circuit unit 16, and outputting the data recorded in the register R1 to the c input terminal of the arithmetic circuit unit 16 is executed. In this processing, as shown in FIGS. 8 and 9, the data recorded in the register R4 is an initial value of C (i, k), and the data recorded in the register R0 is processed by a three-dimensional discrete cosine transform process. Data: X (m, j, k) where m = (− i−j + k) mod — 2, and the data recorded in the register R 1 has an initial value of 0.

  The arithmetic circuit unit 16 of each processing element PE uses the data of the register R4 input as the data a, the data of the register R0 input as the data b, and the data of the register R1 input as the data c. A product-sum operation (operation of d = a × b + c) is executed.

  Next, the control circuit unit 18 of each processing element PE controls the output switch unit 17 to acquire the operation result d, data a, and data b, and the operation result d is input to the k of the processing element PE adjacent in the k-axis direction. The data b (specifically, data recorded in the register R0) is output to the i input terminal of the processing element PE adjacent in the -i axis direction. Note that the acquired data a is not output to the adjacent processing element PE.

  Then, the control circuit unit 18 of each processing element PE controls the input switch unit 14 to obtain the operation result d from the adjacent processing element PE through the k input terminal, and the data b ( And the operation result d is recorded in the register R1, and the data b (data in the register R0) is recorded in the register R0.

  In this way, the control circuit unit 18 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the second embodiment, twice), a path connected in a torus shape by connecting the i input terminal and the i output terminal, and the k input terminal and the k output terminal The calculation processing result and the predetermined data are made a round along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the first period. Note that, in the first-time n product-sum operation processing, the data a input to the output switch unit 17 via the output terminal 21 is not output to the adjacent processing element PE.

  By repeating this process n times, the result of product-sum operation is recorded in all the processing elements PE arranged in the k-axis direction in the register R1 of each processing element PE. In the second embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “0” and “1” shown in FIGS. 8 and 9 indicate processing contents corresponding to the above-described two processings.

  Subsequently, the control circuit unit 18 of each processing element PE controls the selector unit 15 to output the data recorded in the register R1 to the a input terminal of the arithmetic circuit unit 16, and the data recorded in the register R5. A process of outputting to the b input terminal of the arithmetic circuit unit 16 and outputting the data recorded in the register R2 to the c input terminal of the arithmetic circuit unit 16 is executed. In this processing, the data recorded in the register R5 is the initial value of C (k, j), and the data recorded in the register R1 is sum of products in all the processing elements PE arranged in the k-axis direction. The calculated result and the data recorded in the register R2 has an initial value of 0.

  The arithmetic circuit unit 16 of each processing element PE uses the data of the register R1 input as the data a, the data of the register R5 input as the data b, and the data of the register R2 input as the data c. A product-sum operation (operation of d = a × b + c) is executed.

  Next, the control circuit unit 18 of each processing element PE controls the output switch unit 17 to acquire the operation result d, data a, and data b, and the operation result d is j of the processing element PE adjacent in the −j axis direction. The data a is output to the input terminal, and the data a (specifically, the data recorded in the register R1) is output to the k input terminal of the processing element PE adjacent in the k-axis direction. The acquired data b is not output to the adjacent processing element PE.

  Then, the control circuit unit 18 of each processing element PE controls the input switch unit 14 to obtain the operation result d from the adjacent processing element PE through the j input terminal, and the data a ( (Register R1 data) is acquired, the operation result d is recorded in the register R2, and data a (data in the register R1) is recorded in the register R1.

  In this way, the control circuit unit 18 of each processing element PE performs the process of outputting the calculation result d and data a to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the second embodiment, twice), a path connected in a torus shape by connecting the j input terminal and the j output terminal, and the k input terminal and the k output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the second period. In the n-th product-sum operation processing in the second period, the data b input to the output switch unit 17 via the output terminal 22 is not output to the adjacent processing element PE.

  By repeating this processing n times, the result of product-sum operation in all the processing elements PE arranged in the k-axis direction (n-th product in the first cycle) is stored in the register R2 of each processing element PE. Based on the register R1 that is the result of the sum operation process, the result of the product-sum operation on all the processing elements PE arranged in the j-axis direction (by the nth product-sum operation process in the second period) (Operation result) is recorded, and the result of the product-sum operation in all the processing elements arranged in the k-axis direction is recorded in the register R1. In the second embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “2” and “3” shown in FIGS. 8 and 9 indicate the processing contents corresponding to the above-described two processings.

  Subsequently, the control circuit unit 18 of each processing element PE controls the selector unit 15 to output the data recorded in the register R2 to the a input terminal of the arithmetic circuit unit 16, and the data recorded in the register R6. A process of outputting to the b input terminal of the arithmetic circuit unit 16 and outputting the data recorded in the register R3 to the c input terminal of the arithmetic circuit unit 16 is executed. In this processing, the data recorded in the register R6 is the initial value of C (i, j), and the data recorded in the register R2 is sum of products in all the processing elements PE arranged in the k-axis direction. On the basis of the calculated calculation result (the calculation result by the n-th product-sum calculation process in the first period), the calculation result (second calculation) performed by all the processing elements PE arranged in the j-axis direction The data recorded in the register R3 is an initial value of 0.

  The arithmetic circuit unit 16 of each processing element PE uses the data of the register R2 input as the data a, the data of the register R6 input as the data b, and the data of the register R3 input as the data c. A product-sum operation (operation of d = a × b + c) is performed.

  Next, the control circuit unit 18 of each processing element PE controls the output switch unit 17 to obtain the calculation result d, data a, and data b, and the calculation result d is processed in the processing element PE adjacent in the −i axis direction. The data a (specifically, data recorded in the register R2) is output to the j input terminal of the processing element PE adjacent in the −j axis direction. The acquired data b is not output to the adjacent processing element PE.

  Then, the control circuit unit 18 of each processing element PE controls the input switch unit 14 to obtain the operation result d from the adjacent processing element PE through the i input terminal, and the data a ( The data (register R2 data) is acquired, the operation result d is recorded in the register R3, and the data a (data in the register R2) is recorded in the register R2.

  In this way, the control circuit unit 18 of each processing element PE performs the process of outputting the calculation result d and data a to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (twice in the second embodiment), a path connected in a torus shape by connecting the i input terminal and the i output terminal, and the j input terminal and the j output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the third period. Note that in the third product-sum operation processing in the third period, the data b input to the output switch unit 17 via the output terminal 22 is not output to the adjacent processing element PE.

  As a result of repeating this process n times, the register R3 of each processing element PE stores the result of the product-sum operation in all the processing elements PE arranged in the k-axis direction (nth product in the first period). The product-sum operation results of all the processing elements PE arranged in the j-axis direction that have undergone product-sum operation based on the result of the operation of the sum operation processing (operation results of the n-th product-sum operation processing in the second period) Are used to record the calculation results (calculation results of the nth product-sum calculation processing in the third period) performed by all the processing elements PE arranged in the i-axis direction. This is the calculation result of the three-dimensional discrete cosine transform. In addition, the register R2 stores j based on the operation result obtained by the product-sum operation in all the processing elements PE arranged in the k-axis direction (the operation result obtained by n times product-sum operation processing in the first period). The result of the product-sum operation performed by all the processing elements PE arranged in the axial direction (the operation result by the n-th product-sum operation processing in the second period) is recorded. This is a calculation result of a two-dimensional discrete cosine transform composed of the i-axis direction and the j-axis direction. Further, the calculation result of the one-dimensional discrete cosine transform in the i-axis direction is recorded in the register R1. In the second embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “4” and “5” shown in FIGS. 8 and 9 indicate the processing contents corresponding to the above-described two processings.

  In this manner, in the array processor 1 according to the second embodiment, the operation result and the predetermined data used for the product-sum operation are sequentially output to the adjacent processing elements PE, and the product-sum operation processing is performed in each processing element PE. The output of the calculation result to the adjacent processing element PE is sequentially processed by changing the output direction to the k-axis direction, the j-axis direction, and the i-axis direction. The calculation result can be recorded in the register R3. Therefore, unlike the conventional array processor, it is not necessary to provide a dedicated circuit for adjusting the input order of data and coefficient data during the calculation, and the circuit configuration can be simplified. Further, since the three-dimensional discrete cosine transform process (three-dimensional orthogonal transform process) can be performed by sequentially outputting the calculation result to the adjacent processing element PE, the calculation element PE can be inserted inside the processing element PE during the calculation of each dimension. The stored data and coefficient matrix elements do not need to be exchanged many times using a complicated wiring structure as in the prior art, and the processing can be speeded up and simplified.

  As described above, by using the array processor 1 according to the second embodiment, it is not necessary to perform replacement work of data during calculation, which is essential in the conventional configuration. In addition, by connecting a plurality of processing elements PE and sequentially performing processing result processing, three-dimensional discrete cosine transform processing (three-dimensional orthogonal transform processing) can be executed quickly, and the complexity of the circuit configuration is further suppressed. It becomes possible to do.

  Next, a method for calculating the three-dimensional inverse discrete cosine transform (3D-IDCT) using the array processor 1 described above will be described. FIG. 10 is a table showing the initial values of the registers R0 to R6 and the registers recorded in each processing step in each processing element PE (i, j, k), and FIG. 11 is shown in FIG. The state in which the contents of the registers are changed is indicated by arrows according to the processing steps. In addition, the arrow by the broken line shown in FIG. 11 is one of the data a and data b used in the calculation process, and indicates the output state of data used in the process described later. An arrow with a solid line indicates an output state of data corresponding to the calculation result d.

  First, initial values of the registers R0 to R6 in each processing element PE are set. Here, in the registers R4, R5, and R6, values obtained by Expressions 9 to 14 are set as initial values. These are constants and are not changed until the end of the operation.

  Also, 0 is recorded in the registers R1 to R3 as an initial value, and in the register R0, three-dimensional input data for performing a three-dimensional inverse discrete cosine transform process (3D-IDCT process), specifically, the above-described formula The value of Y (i, m, k) in (2) is recorded. Here, m is a value calculated by m = (− i−j + k) mod_n, and mod_n represents a modulo operation of n. That is, m is a remainder obtained by dividing (−i−j + k) by n. N indicates the size of the three-dimensional input data n × n × n, that is, the size of the array processor 1. In the processing element PE according to the second embodiment, n = 2 as shown in FIG.

  Accordingly, Y (0,0,0) is set in the register R0 of the processing element PE (0,0,0), and Y (0,1,0) is set in the register R0 of the processing element PE (0,1,0). 0) is set. Further, Y (1,1,0) is set in the register R0 of the processing element PE (1, 0, 0), and Y (1, 0, 0) is set in the register R0 of the processing element PE (1, 1, 0). 0) is set. Further, Y (0,1,1) is set in the register R0 of the processing element PE (0,0,1), and Y (0,0,1) is set in the register R0 of the processing element PE (0,1,1). 1) is set. In addition, Y (1, 0, 1) is set in the register R0 of the processing element PE (1, 0, 1), and Y (1, 1, 1) is set in the register R0 of the processing element PE (1, 1, 1). 1) is set.

  After the initial values of the registers R0 to R6 are set, the control circuit unit 18 of each processing element PE controls the selector unit 15 to input the data recorded in the register R0 to the a input of the arithmetic circuit unit 16. A process of outputting data to the terminal, outputting data recorded in the register R4 to the b input terminal of the arithmetic circuit unit 16, and outputting data recorded in the register R1 to the c input terminal of the arithmetic circuit unit 16 is executed. In this process, the data recorded in the register R4 is an initial value of C (k, j), and the data recorded in the register R0 is subjected to a three-dimensional inverse discrete cosine transform process (3D-IDCT process). Input data Y (i, m, k), where m = (− i−j + k) mod_n, and the data recorded in the register R1 has an initial value of 0.

  The arithmetic circuit unit 16 of each processing element PE uses the data of the register R0 input as the data a, the data of the register R4 input as the data b, and the data of the register R1 input as the data c. A product-sum operation (operation of d = a × b + c) is performed.

  Next, the control circuit unit 18 of each processing element PE controls the output switch unit 17 to obtain the operation result d, data a, and data b, and the operation result d is input to the k of the processing element PE adjacent in the k-axis direction. Further, the data a (specifically, data recorded in the register R0) is output to the j input terminal of the processing element PE adjacent in the −j axis direction. The acquired data b is not output to the adjacent processing element PE.

  Then, the control circuit unit 18 of each processing element PE controls the input switch unit 14 to obtain the operation result d from the adjacent processing element PE through the k input terminal, and the data a ( Register R0) and record the operation result d in the register R1, and record data a (data in the register R0) in the register R0.

  In this way, the control circuit unit 18 of each processing element PE performs the process of outputting the calculation result d and data a to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (twice in the second embodiment), a path connected in a torus shape by connecting the k input terminal and the k output terminal, and the j input terminal and the j output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the first period. Note that, in the n-th product-sum operation processing in the first period, the data b input to the output switch unit 17 via the output terminal 22 is not output to the adjacent processing element PE.

  By repeating this processing n times, the result of product-sum operation in all the processing elements PE arranged in the k-axis direction (nth product in the first cycle) is stored in the register R1 of each processing element PE. The calculation result by the sum calculation process) is recorded. In the second embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “0” and “1” shown in FIGS. 10 and 11 indicate the processing contents corresponding to the above-described two processings.

  Subsequently, the control circuit unit 18 of each processing element PE controls the selector unit 15 to output the data recorded in the register R5 to the a input terminal of the arithmetic circuit unit 16, and the data recorded in the register R1. A process of outputting to the b input terminal of the arithmetic circuit unit 16 and outputting the data recorded in the register R2 to the c input terminal of the arithmetic circuit unit 16 is executed. In this processing, the data recorded in the register R5 is the initial value of C (i, k), and the data recorded in the register R1 is sum of products in all the processing elements PE arranged in the k-axis direction. The calculated result and the data recorded in the register R2 has an initial value of 0.

  The arithmetic circuit unit 16 of each processing element PE uses the data in the register R5 input as the data a, the data in the register R1 input as the data b, and the data in the register R2 input as the data c. A product-sum operation (operation of d = a × b + c) is executed.

  Next, the control circuit unit 18 of each processing element PE controls the output switch unit 17 to obtain the calculation result d, data a, and data b, and the calculation result d is converted to i of the processing element PE adjacent in the −i axis direction. The data b is output to the input terminal, and the data b (specifically, the data recorded in the register R1) is output to the k input terminal of the processing element PE adjacent in the k-axis direction. Note that the acquired data a is not output to the adjacent processing element PE.

  Then, the control circuit unit 18 of each processing element PE controls the input switch unit 14 to obtain the operation result d from the adjacent processing element PE through the i input terminal, and the data b ( (Register R1 data) is acquired, the operation result d is recorded in the register R2, and the data b (data in the register R1) is recorded in the register R1.

  In this way, the control circuit unit 18 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the second embodiment, twice), a path connected in a torus shape by connecting the i input terminal and the i output terminal, and the k input terminal and the k output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the second period. Note that in the n-th product-sum operation processing in the second cycle, the data a input to the output switch unit 17 via the output terminal 21 is not output to the adjacent processing element PE.

  By repeating this processing n times, the result of product-sum operation in all the processing elements PE arranged in the k-axis direction (n-th product in the first cycle) is stored in the register R2 of each processing element PE. Based on the register R1 which is the result of the sum operation process, the result of the product-sum operation on all the processing elements PE arranged in the i-axis direction (by n product-sum operation processes in the second period) (Operation result) is recorded, and the result of product-sum operation in all the processing elements PE arranged in the k-axis direction is recorded in the register R1. The processing steps “2” and “3” shown in FIG. 10 and FIG. 11 indicate the processing contents corresponding to the above-described two processings.

  Subsequently, the control circuit unit 18 of each processing element PE controls the selector unit 15 to output the data recorded in the register R6 to the a input terminal of the arithmetic circuit unit 16, and the data recorded in the register R2 A process of outputting to the b input terminal of the arithmetic circuit unit 16 and outputting the data recorded in the register R3 to the c input terminal of the arithmetic circuit unit 16 is executed. In this processing, the data recorded in the register R6 is the initial value of C (i, j), and the data recorded in the register R2 is sum of products in all the processing elements PE arranged in the k-axis direction. Based on the calculated calculation result (the calculation result by the n-th product-sum calculation processing in the first cycle), the calculation result (second calculation) performed by all the processing elements PE arranged in the i-axis direction The data recorded in the register R3 is an initial value of 0.

  The arithmetic circuit unit 16 of each processing element PE uses the data of the register R6 input as the data a, the data of the register R2 input as the data b, and the data of the register R3 input as the data c. A product-sum operation (operation of d = a × b + c) is performed.

  Next, the control circuit unit 18 of each processing element PE controls the output switch unit 17 to obtain the operation result d, data a, and data b, and the operation result d is adjacent to the processing element PE in the −j axis direction. The data b (specifically, data recorded in the register R2) is output to the i input terminal of the processing element PE adjacent in the -i axis direction. Note that the acquired data a is not output to the adjacent processing element PE.

  Then, the control circuit unit 18 of each processing element PE controls the input switch unit 14 to obtain the calculation result d from the adjacent processing element PE through the j input terminal, and the data b ( (Register R2 data) is acquired, and the operation result d is recorded in the register R3, and the data b (data in the register R2) is recorded in the register R2.

  In this way, the control circuit unit 18 of each processing element PE performs the process of outputting the calculation result d and data b to the adjacent processing element PE, and the number of processing elements PE arranged in each axial direction. , I.e., n times (in the second embodiment, twice), a path connected in a torus shape by connecting the j input terminal and the j output terminal, and the i input terminal and the i output terminal The arithmetic processing result and the predetermined data are circulated along the path connected in a torus shape by the connection. This one-round processing corresponds to n product-sum operation processing in the third period. In the third product-sum operation process in the third period, the data a input to the output switch unit 17 via the output terminal 21 is not output to the adjacent processing element PE.

  As a result of repeating this process n times, the register R3 of each processing element PE stores the result of the product-sum operation in all the processing elements PE arranged in the k-axis direction (nth product in the first period). The product-sum operation results of all the processing elements PE arranged in the i-axis direction that are product-sum-calculated based on the result of the sum operation processing (operation results of the n-th product-sum operation processing in the second period) Are used to record the calculation results (calculation results of the nth product-sum calculation processing in the third period) performed by all the processing elements PE arranged in the j-axis direction. This is a calculation result of a three-dimensional inverse discrete cosine transform process (3D-IDCT process). Further, the register R2 stores i on the basis of the operation result obtained by the product-sum operation in all the processing elements PE arranged in the k-axis direction (the operation result by the n-th product-sum operation processing in the first period). An operation result obtained by the product-sum operation in all the processing elements PE arranged in the axial direction (operation result by n times product-sum operation processing in the second period) is recorded. This is a calculation result of a two-dimensional discrete inverse cosine transform composed of the i-axis direction and the k-axis direction. Further, the calculation result of the one-dimensional discrete inverse cosine transform in the i-axis direction is recorded in the register R1. In the second embodiment, since n = 2, the above-described processing is performed only twice. The processing steps “4” and “5” shown in FIG. 10 and FIG. 11 indicate processing contents corresponding to the above-described two processings.

  In this manner, in the array processor 1 according to the second embodiment, the operation result and the predetermined data used for the product-sum operation are sequentially output to the adjacent processing elements PE, and the product-sum operation processing is performed in each processing element PE. The output of the calculation result to the adjacent processing element PE is sequentially processed by changing the output direction to the k-axis direction, the i-axis direction, and the j-axis direction. The calculation result can be recorded in the register R3. Therefore, unlike the conventional array processor 1, it is not necessary to provide a dedicated circuit for adjusting the input order of data and coefficient data during calculation, and the circuit configuration can be simplified. In addition, since the three-dimensional inverse discrete cosine transform process (three-dimensional inverse orthogonal transform process) can be performed by sequentially outputting the calculation results to adjacent processing elements PE, the processing element PE of each dimension is calculated in the middle. It is not necessary to exchange the data and coefficient matrix elements stored in the inside many times using a complicated wiring structure as in the conventional case, and it becomes possible to speed up and simplify the processing.

  As described above, by using the array processor 1 according to the second embodiment, it is not necessary to perform replacement work of data during calculation, which is essential in the conventional configuration. In addition, by connecting a plurality of processing elements and processing the results sequentially, the 3D inverse discrete cosine transform process (3D inverse orthogonal transform process) can be executed quickly, and the circuit configuration can be further complicated. It becomes possible to suppress.

  The array processor according to the present invention has been described in detail with reference to the drawings. However, the array processor according to the present invention is not limited to the above-described configuration, and those skilled in the art can claim It is clear that various changes and modifications can be conceived within the scope described in the scope, and it is understood that these also belong to the technical scope of the present invention.

  For example, in the array processor 1 according to the first embodiment and the second embodiment, a configuration in which a total of eight processing elements PE are provided, two for each of the i-axis direction, the j-axis direction, and the k-axis direction. However, the array processor according to the present invention is not limited to a structure in which two array processors are arranged in each axial direction, and two or more (for example, n) arrays. The case where it arrange | positions may be sufficient. Even when a plurality of processing elements are provided in this way, the calculation result and predetermined data are output to adjacent processing elements PE according to the method described in the first and second embodiments, and the circuit is completed. This makes it possible to perform calculations related to the three-dimensional orthogonal transformation process and the three-dimensional inverse orthogonal transformation process.

  In the array processor 1 according to the first embodiment and the second embodiment, the processing elements are arranged at coordinate positions corresponding to the i-axis, j-axis, and k-axis for convenience of explanation. When the processing element PE is actually arranged, it is not necessary to form the physical three-dimensional arrangement (three-dimensional arrangement) as described above, and the three input terminals provided in the processing element PE described above. And the three output terminals may be arranged in any way as long as they correspond to each other. For example, each processing element may be arranged in a plane by setting three axes on the same plane.

  In the first embodiment and the second embodiment, the array processor that performs the calculation of the three-dimensional discrete cosine transform and the three-dimensional inverse discrete cosine transform, which is an example of the three-dimensional orthogonal transform processing, has been described. The array processor according to the present invention is not used only for the three-dimensional orthogonal transform processing related to the above-described three-dimensional discrete cosine transform and three-dimensional inverse discrete cosine transform, but C (i, k), C (k, j), By changing the initial value (DCT coefficient) indicated by C (i, j) to an appropriate coefficient, other three-dimensional orthogonal transforms such as Walsh Hadamard transform (WHT), discrete Fourier transform (DFT), etc. It can be used for arithmetic processing.

  Furthermore, in the array processor 1 shown in the first embodiment and the second embodiment, the case has been described in which the arithmetic circuit units 6 and 16 are configured to perform arithmetic processing using a physical dedicated arithmetic circuit. Instead of using such a physical circuit, the arithmetic processing function of the control circuit units 8 and 18 is used to perform an operation corresponding to the arithmetic processing of the arithmetic circuit units 6 and 16, and the arithmetic processing is performed. For example, the circuit may not be physically provided.

  In the case of using the array processor 1 shown in the first embodiment and the second embodiment, the data is first output in the i-axis direction, the j-axis direction, the k-axis direction, the data transfer direction, and in which axis direction. It is possible to freely set and change the data processing order. In addition, it is possible to freely set and change where the data and initial values (DCT coefficients) input to each processing element PE are stored in the registers R0 to R6 in each processing element PE (i, j, k). Is possible. As described above, even when the data transfer direction, processing order, and data storage setting are changed, the same processing result as the contents shown in the first and second embodiments can be obtained. In addition to the methods shown in the first embodiment and the second embodiment, various methods are conceivable for obtaining the same result. However, it is obvious that those skilled in the art can easily come up with these modifications within the scope of the claims, and these modifications naturally belong to the technical scope of the present invention. It is understood.

DESCRIPTION OF SYMBOLS 1 ... Array processor 4, 14 ... Input switch part 5, 15 ... Selector part 6, 16 ... Operation circuit part 7, 17 ... Output switch part 8, 18 ... Control circuit part 10, 20 ... Output terminal (of operation circuit part) 21, 22... Output terminal PE (from select section to output switch section) Processing element R 0 to R 6. Register

Claims (1)

Forming a conceptual three-dimensional arrangement state by arranging n processing elements each having a product-sum operation function in three axial directions,
For each processing element, three sets of input terminals and output terminals associated with the axial direction are provided in association with each axial direction, and one processing element arranged adjacent to the same axial direction in the axial direction. By connecting the input terminal and the output terminal in the axial direction of the other processing element, the three input terminals and the output terminal of each processing element are connected in a torus shape corresponding to the axial direction,
In each processing element, an operation result obtained by performing the product-sum operation based on the product-sum operation function is output from an output terminal corresponding to one axial direction to another processing element adjacent in the one axial direction, The operation data used when performing the product-sum operation is output from the output terminal corresponding to the other axial direction to another processing element adjacent to the other axial direction,
In the processing element obtained from the other processing elements adjacent to each other in the different axial directions, the calculation result and the calculation data are calculated using the acquired calculation result and the calculation data, and based on the product-sum calculation By outputting the calculation result and the calculation data to other processing elements adjacent to each other in the axial direction from the output terminal corresponding to the acquired input terminal, it is connected in a torus shape in one axial direction. In all the processing elements, n times product-sum operation processing in the first period is executed in synchronization with each other,
After the first product-sum operation processing in the first cycle, each processing element changes the axial direction of the output terminal that outputs the operation result, and the operation data is changed corresponding to the change in the axial direction. Change the axial direction of the output terminal to be output, and execute n times of product-sum operation processing in the second period in synchronization with each other,
After the nth product-sum operation processing in the second cycle, each processing element changes the axial direction of the output terminal that outputs the calculation result to a different axial direction from the first cycle and the second cycle. In addition, the axial direction of the output terminal that outputs the calculation data corresponding to the change in the axial direction is changed to an axial direction different from the first period and the second period, and the product of n times in the third period By performing the sum operation in sync with each other,
An array processor that performs three-dimensional orthogonal transform processing ,
Each processing element is
One operand value storage means for storing operand values used for the product-sum operation;
Three input information storage means for storing the calculation result or the calculation data input via the input terminal;
Three constant value storage means for storing constant values determined corresponding to the calculation method by the multiply-accumulate function;
Arithmetic processing means for performing a product-sum operation using any one of the calculation result, the calculation data, the operand value, and the constant value;
Input switch means for guiding information input from any of the three input terminals to either the input information storage means or the operand value storage means;
Output switch means for outputting the operation data and the operation result of the product-sum operation performed by the operation processing means from any of the three output terminals;
Selector means for reading three data from any one of the operand value storage means, the input information storage means, and the constant value storage means and guiding the data to the arithmetic processing means;
Control means for controlling the input switch means, the output switch means and the selector means;
Have
When the calculation result is input via the input terminal, the control means controls the input switch means to guide the calculation result to one of the input information storage means, and controls the selector means. Then, the calculation result read from the input information storage means is guided to the calculation processing means, and when the calculation processing is not performed n times in one cycle, the output switch means is controlled to control the output switch means. When the calculation result obtained by the product-sum operation by the calculation processing means is output from the axial output terminal corresponding to the input terminal to which the calculation result is input, and the nth calculation process is performed in one cycle The output switch means is controlled to output the operation result obtained by the product-sum operation by the operation processing means from an output terminal in an axial direction different from the input terminal to which the operation result is input. That
An array processor characterized by that.

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