JP3977003B2 - Discrete cosine transform / inverse discrete cosine transform method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data conversion processing device such as a microprocessor or a microcomputer, and more particularly to an image processing and audio processing application data processing device that performs discrete cosine transformation, inverse discrete cosine transformation, or the like.
[0002]
[Prior art]
Digitized images and voices have a huge amount of data, which poses a problem during storage and transmission. Therefore, it is possible to take measures such as compressing before storage and decompressing when used, or compressing before transmission and decompressing after reception.
[0003]
Hereinafter, image compression / decompression will be described as an example.
[0004]
compression
1.2D discrete cosine transform
2. Quantization
3. Huffman coding
Elongation
4). Huffman decoding
5). Inverse quantization
6. Two-dimensional inverse discrete cosine transform
The two-dimensional discrete cosine transform 1 and the two-dimensional inverse discrete cosine transform 6 are performed on a two-dimensional block of 8 * 8 pixels, and the conversion result is also a two-dimensional block value group of 8 * 8 elements.
[0005]
By the two-dimensional discrete cosine transform transformation of 1, the elements corresponding to the high-frequency components of the 8 * 8 block usually have a value close to 0, and the majority of them becomes 0 by the weighted quantization operation. The 3 Huffman encoding converts 8 * 8 block elements into a bitstream. At this time, since conversion is performed using the fact that there are many zeros in the element, it is said that the required number of bytes in the converted bit stream is about 1/10.
[0006]
Huffman Decomposition 4 in decompression performs the reverse operation of 3, and generates an 8 * 8 block element group from the bitstream. In the inverse quantization of 5, the element group before the quantization is restored by multiplying the inverse of the weight given in the quantization of 2. The 6-dimensional inverse discrete cosine transform of 6 performs the inverse operation of 1 to restore 8 * 8 pixels.
[0007]
Here, the labor required for the above-described compression / decompression operation is shown. When an ordinary general-purpose processor is used, 2000 to 3000 instructions are required for each of 8 * 8 blocks for both compression and decompression. When a 640 * 480 full-color (24 bits / pixel) image is targeted, it is 14400 times and requires execution of 28.8M to 43.2M instructions per still image. When using a processor that operates at 100 MHz for processing one instruction, only a compression / decompression speed of 2 to 4 frames / second can be obtained, and moving images can be captured and played back in real time. It is difficult to obtain.
[0008]
In view of this, many methods have been adopted in which a separate processing apparatus equipped with a special dedicated arithmetic unit for assisting image and sound compression / decompression is prepared.
[0009]
As another solution, a SIMD (Single Instruction Multiple Data) instruction that simultaneously processes a matrix / vector operation instruction and a plurality of product-sum operations, etc., which is also installed in a general-purpose processor is used. Thus, a method for configuring the conversion processing apparatus is also mentioned. Since the discrete cosine transformation is a linear transformation, the N-point transformation can be expressed by an N * N matrix, and the transformation process is completed by obtaining the matrix product using the matrix / vector operation instruction or SIMD instruction.
[0010]
[Problems to be solved by the invention]
It has been stated that the transformation matrix used in the second processing device shown above has a size of N * N for N-point discrete cosine transformation. For example, when an 8 * 8 two-dimensional discrete cosine transform process is repeated, a matrix operation for obtaining 8 outputs using 64 coefficients and 8 input data shown in FIG. And 8 times in the horizontal direction.
[0011]
At this time, since the 64 coefficients are constants, it is ideal to process them while holding them in the processor. However, practically, it is required to process while sequentially reading 64 parts arranged in the main memory because of the restriction on the number of registers.
[0012]
Also, in order to efficiently perform the above 8-point conversion processing, it is desirable to prepare an 8 * 8 matrix calculator and a SIMD calculator with a parallel degree of 8, but it is convenient in the field of, for example, three-dimensional graphics. 4 * 4 matrix operation and SIMD operation with a parallel degree of 4 are reasonable. Furthermore, in the case of the 32-point discrete cosine transform used for voice compression / decompression, it is more difficult to realize from the coefficient and circuit scale.
[0013]
In the embodiment of Japanese Patent Laid-Open No. 9-212484, the 8 * 8 discrete cosine transform is decomposed into an even function part and an odd function part number as shown in FIG. It is shown in the intermediate equation that leads to the conclusion that the component, the 4 * 4 component in the lower left, is zero. When a processor equipped with a 4 * 4 matrix and an arithmetic unit for obtaining the product of a four-dimensional vector is used, conversion processing can be performed by two matrix operations by adding some pre-processing and post-processing. Is implied.
[0014]
However, since two different 4 * 4 coefficient matrices are used, a process of replacing 4 * 4 coefficient data is required every time a matrix operation is performed in the discrete cosine transform process. For example, when the ratio of the number of cycles for matrix calculation and coefficient replacement is 1: 1, the use efficiency of the matrix calculator can be estimated to be 50% or less.
[0015]
It is an object of the present invention to reduce the overhead required to replace the transform coefficient matrix and increase the utilization efficiency of an arithmetic unit in order to achieve high-speed discrete cosine transform and inverse discrete cosine transform by matrix operation and SIMD operation. And
[0016]
[Means for Solving the Problems]
In the present invention, in order to solve the above problem, the property of the definition formula of discrete cosine transform is used. By adding a pre-processing butterfly operation and a post-processing addition process, the N-point discrete cosine transform can be divided into two N / 2-point discrete cosine transforms. At this time, since only one (N / 2) * (N / 2) matrix is used as the coefficient matrix, it is not necessary to replace the matrix, and high-speed conversion processing is possible.
[0017]
The number of coefficients in the 8-point conversion process is ¼ compared to FIG. 7 and ½ compared to FIG. 4, and the number of registers holding coefficients in the processor can be reduced.
[0018]
This division is repeated an arbitrary number of times, so that the pre-processing and post-processing are slightly increased. However, the matrix coefficients and the operation scale are 1/4, 1/16,. . . Therefore, the optimum number of divisions can be selected for the processor to be used.
[0019]
Since the above-described division is also established with respect to inverse discrete cosine transform, similarly, transformation processing that does not require matrix replacement is possible.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
(1) Definition of discrete cosine transform
The definition formula of the one-dimensional discrete cosine transform is shown as in FIG. The definition of the coefficient A is Equation (3). When quantization is performed after discrete cosine transform as in image compression, or when inverse quantization is performed before inverse discrete cosine transform as in image expansion, If the weighting coefficient at the time of quantization is multiplied by A, the definition of the discrete cosine transform can be simplified as shown in Expression (3 ′). Hereinafter, equations (2), (3 ′), and (4) will be used as defining equations for the one-dimensional discrete cosine transform.
[0021]
N = 8 is used for compression and expansion of still images and moving images, which are typical applications of discrete cosine transform and inverse discrete cosine transform. Therefore, if N = 8 in the discrete cosine transform of FIG. 5, the matrix operation shown in FIG. 7 can be used. The elements of the matrix are normalized using Equation (5) among the properties of c (n, N) shown in FIG. Since the inverse discrete cosine transform corresponds to a calculation obtained by transposing this matrix, only the discrete cosine transform is handled here.
[0022]
The N * N point two-dimensional discrete cosine transform was performed N times in the vertical direction and N times in the vertical direction, and then N times in the horizontal direction (or N times in the horizontal direction and then N times in the vertical direction). Can be defined as That is, the N * N-point two-dimensional discrete cosine transform can be decomposed into N-point one-dimensional discrete cosine transform 2N times. Hereinafter, the one-dimensional discrete cosine transform is mainly treated.
[0023]
(2) Division of 8-point discrete cosine transform
Here, the equation (2) is set as k = 2K and k = 2K + 1, and is separated into an even output and an odd output. By utilizing the properties of Equation (6) and Equation (7), the even side can be transformed as in Equation (9) and the odd side can be transformed as in Equation (10). Further, when K = N / 2-1 on the odd side, that is, X [N−1] is derived as shown in Expression (11) using the property of Expression (6). By substituting N = 8 into Equation (10), Equation (9), and Equation (11), a matrix representation of Equation (1) is obtained. Focusing on the 4 * 4 components at the upper left and lower right of this matrix, it is the same matrix as the 4-point discrete cosine transform, and with the above formula modification, the 8-point discrete cosine transform adds some pre-processing and post-processing. By doing so, it was shown that it can be divided into two 4-point discrete cosine transforms. FIG. 2 shows the butterfly diagram.
[0024]
When performing inverse discrete cosine transform, the calculation procedure is performed in reverse order from the output side to the input side. At that time, an inverse matrix of the coefficient matrix is required, but a transposed matrix may be used due to the nature of the coefficient matrix of the discrete cosine transform. In the embodiment described below, only discrete cosine transform is handled, but it will be described that inverse discrete cosine transform can also be realized by using the method of processing in the reverse order described here.
[0025]
(3) Example 1
The configuration of the conversion apparatus of this embodiment is shown in FIG. The conversion device 101 includes a processor 102 and a storage unit 103, inputs data from an input device 111 connected to the outside, performs conversion processing such as image compression / decompression, and outputs a conversion result from the output device 112. The processor 102 and the storage unit 103 are connected by an address bus 104 and a data bus 105, specify the address of the storage device by the address calculated by the address generator 106 in the processor, and communicate with the register file 107 in the processor through the data bus. Perform data transfer. The storage unit 103 includes a program storage device 109 and a data storage device 110. The arithmetic unit 108 reads the contents of the register file, performs arithmetic processing, and writes the result back to the register file again. The configuration of the register file 107 is shown in FIG. The register file 1 is composed of R0 to R15 and the register file 2 is composed of XR0 to XR15. The registers Rn, Rn + 1, Rn + 2, and Rn + 3 of the register file 0 are referred to as VRn.
[0026]
Here, instructions of the processor 102 and their operations are defined. First, a TRV instruction that performs a matrix product of a 4 * 4 matrix and a vector having 4 elements is described as follows.
[0027]
TRV VRs, VRd (s, d = 4n)
The TRV instruction regards 16 registers of register file 1 as a 4 * 4 matrix, a register group in register file 0, and VRs as a four-dimensional vector, and stores the multiplication result of the matrix and the vector in VRd. FIG. 11 shows the operation contents of the TRV instruction.
[0028]
Next, ADD, SUB, MUL, ADD4, SUB4, and MUL4 are defined as follows as instructions for addition, subtraction, and multiplication.
[0029]
ADD Rs, Rt, Rd
SUB Rs, Rt, Rd
MUL Rs, Rt, Rd
ADD4 VRs, VRt, VRd (s, t, d = 4n)
SUB4 VRs, VRt, VRd (s, t, d = 4n)
MUL4 VRs, VRt, VRd (s, t, d = 4n)
The ADD, SUB, and MUL instructions add, subtract, and multiply the registers Rs and Rt, and store the result in the register Rd. The ADD4, SUB4, and MUL4 instructions add, subtract, and multiply the corresponding elements of the register group VRt with the register group VRs, and store the result in VRd. FIGS. (12), (13), and (14) show the operation contents of the ADD4 instruction, SUB4 instruction, and MUL4 instruction. Further, the following four instructions are defined as instructions for loading data from the main memory into the register and conversely storing data from the register into the main memory.
[0030]
LD b, disp, Rd
ST b, disp, Rs
LD4 b, disp, step, VRd (d = 4n)
ST4 b, disp, step, VRs (s = 4n)
The LD instruction loads the data stored at the address (b + disp) of the main memory into the register Rd. The ST instruction stores the value of the register Rs at the address (b + disp) of the main memory. The LD4 instruction transfers the data stored at the addresses (b + disp), (b + disp + step), (b + disp + 2 * step), (b + disp + 3 * step) of the main memory to the registers Rd, Rd + 1, Rd + 2, and Rd + 3 in the register file 1. Load it. The ST4 instruction stores the values of the registers Rs, Rs + 1, Rs + 2, and Rs + 3 at addresses (b + disp), (b + disp + step), (b + disp + 2 * step), and (b + disp + 3 * step) of the main memory.
[0031]
Finally, an EXCHG instruction for exchanging the contents of register file 0 and register file 1 is defined.
[0032]
EXCHG
An example of performing image conversion processing using 8 * 8 two-dimensional discrete cosine transform in the above apparatus will be described below.
[0033]
As shown in FIG. 15, the storage device 103 in FIG. 1 stores a conversion program, 4 * 4 matrix data, four coefficient data, and 8 * 8 pixels * B block image data on the main memory. And
[0034]
First, coefficient matrix data and butterfly calculation coefficient data are loaded into a register. This loading operation needs to be performed only once at the beginning of the discrete cosine transform processing of the B block. By this operation, the coefficients shown in FIG. 10 are loaded into the register file, and these coefficients are not changed during the B block conversion operation.
[0035]
#Matrix, coefficient load
LD4 MATRIX, 0, 1, R0
LD4 MATRIX, 4, 1, R4
LD4 MATRIX, 8, 1, R8
LD4 MATRIX, 12, 1, R12
EXCHG
LD4 COEFF, 0, 1, 12
Next, an instruction sequence for performing 8-point one-dimensional discrete cosine transform is shown. OFF indicates an offset from the IMG and is set to 0 in the first processing.
[0036]
# 8-point discrete cosine transform (horizontal)
LD4 IMG, 0 + OFF, 1, VR8
LD4 IMG, 7 + OFF, -1, VR4
ADD4 VR8, VR4, VR0
SUB4 VR8, VR4, VR4
MUL4 VR4, VR12, VR4
TRV VR0, VR0
TRV VR4, VR4
ADD R4, R5, R4
ADD R5, R6, R5
ADD R6, R7, R6
ST4 IMG, 0 + OFF, 2, VR0
ST4 IMG, 1 + OFF, 2, VR4
By performing the conversion process composed of these 12 instructions 8 times while increasing OFF by 8, the one-dimensional discrete cosine transform in the horizontal direction is completed for 8 * 8 pixels. Thereafter, OFF is set to 0, 1,. . . , 7 and changing the following instruction sequence 8 times.
[0037]
# 8 discrete cosine transform (vertical)
LD4 IMG, 0 + OFF, 8, VR8
LD4 IMG, 56 + OFF, -8, VR4
ADD4 VR8, VR4, VR0
SUB4 VR8, VR4, VR4
MUL4 VR4, VR12, VR4
TRV VR0, VR0
TRV VR4, VR4
ADD R4, R5, R4
ADD R5, R6, R5
ADD R6, R7, R6
ST4 IMG, 0 + OFF, 16, VR0
ST4 IMG, 56 + OFF, -16, VR4
With the above operation, the 8 * 8 two-dimensional discrete cosine transform is completed. If the number of blocks B to be converted is sufficiently large, 6 instructions necessary for matrix and coefficient loading can be ignored. Therefore, it can be said that processing can be performed with 192 instructions per block.
[0038]
In the conventional example, a coefficient load of 6 instructions is required for each TRV instruction, and since 32 TRV instructions are used during conversion of one block, 6 instructions * 32 times = 192 instructions are added. It can be said that the number of instructions can be reduced to half by the present invention.
[0039]
(4) Example 2
This embodiment shows an implementation when a processor having a vector inner product operation instruction instead of a matrix operation instruction is used. It is assumed that the coefficients and data are arranged on the main memory as shown in FIG.
[0040]
Assume that the processor used in the present embodiment has the following differences from the first embodiment.
1. As shown in FIG. 16, it has only one register file composed of 32 registers, and therefore does not have an EXCHG instruction.
2. Have IPR instructions instead of TRV instructions
IPR VRs, VRt, Rd (s, t = 4n)
In the IPR instruction, the register groups VRs and VRt are regarded as vectors of four elements, respectively, and the inner product thereof is stored in the register Rd. FIG. 17 shows the calculation contents.
[0041]
A procedure for performing 8 * 8 discrete cosine transform and inverse discrete cosine transform using the above processor will be described below.
[0042]
First, matrix data and coefficient data are loaded into a register. This loading operation needs to be performed only once at the beginning of the discrete cosine transform processing of the B block.
[0043]
#Matrix, coefficient load
LD4 COEFF, 0, 1, VR12
LD4 MATRIX, 0, 4, VR16
LD4 MATRIX, 1, 4, VR20
LD4 MATRIX, 2, 4, VR24
LD4 MATRIX, 3,4, VR28
Next, an instruction sequence for performing 8-point one-dimensional discrete cosine transform is shown. OFF indicates an offset from the IMG and is set to 0 in the first processing.
[0044]
# 8-point discrete cosine transform (horizontal)
LD4 IMG, 0 + OFF, 1, 8
LD4 IMG, 7 + OFF, -1, 4
ADD4 VR8, VR4, VR0
SUB4 VR8, VR4, VR4
MUL4 VR4, VR12, VR4
IPR VR0, VR16, R8
IPR VR0, VR20, R9
IPR VR0, VR24, R10
IPR VR0, VR28, R11
IPR VR4, VR16, R0
IPR VR4, VR20, R1
IPR VR4, VR24, R2
IPR VR4, VR28, R3
ADD R1, R9, R1
ADD R2, R10, R2
ADD R3, R11, R3
ST4 IMG, 0 + OFF, 2, VR8
ST4 IMG, 1 + OFF, 2, VR0
By performing the conversion process composed of these 18 instructions eight times while increasing OFF by eight, the horizontal one-dimensional discrete cosine conversion is completed for 8 * 8 pixels. Thereafter, OFF is set to 0, 1,. . . , 7 and changing the following instruction sequence 8 times.
[0045]
# 8 discrete cosine transform (vertical)
LD4 IMG, 0 + OFF, 8, 8
LD4 IMG, 56 + OFF, -8, 4
ADD4 VR8, VR4, R0
SUB4 VR8, VR4, R4
MUL4 VR4, VR12, R4
IPR VR0, VR16, R8
IPR VR0, VR20, R9
IPR VR0, VR24, R10
IPR VR0, VR28, R11
IPR VR4, VR16, R0
IPR VR4, VR20, R1
IPR VR4, VR24, R2
IPR VR4, VR28, R3
ADD R1, R9, R1
ADD R2, R10, R2
ADD R3, R11, R3
ST4 IMG, 0 + OFF, 16, VR8
ST4 IMG, 56 + OFF, -16, VR0
With the above operation, the 8 * 8 two-dimensional discrete cosine transform is completed. If the number of blocks B to be converted is sufficiently large, 5 instructions necessary for matrix and coefficient loading can be ignored, so that the 2-dimensional discrete cosine transform can be processed with 288 instructions per block.
[0046]
(5) Example 3
This embodiment shows an implementation when a processor having a SIMD instruction instead of a matrix operation instruction is used. It is assumed that the coefficients and data are arranged on the main memory as shown in FIG.
[0047]
The processor used in the present embodiment is assumed to have the following differences from the second embodiment.
1. Have MAC4 instruction instead of IPR instruction
2. Broadcast extension of MUL4 and MAC4 instructions, with MUL4B and MAC4B instructions
MAC4 VRs, VRt, VRd (s, t, d = 4n)
The MAC4 instruction adds the products of the registers Rs, Rs + 1, Rs + 2, and Rs + 3 and the registers Rt, Rt + 1, Rt + 2, and Rt + 3 to the registers Rd, Rd + 1, Rd + 2, and Rd + 3.
[0048]
MUL4B VRs, VRt, VRd, b (s, t, d = 4n, b = 0-3)
MAC4B VRs, VRt, VRd, b (s, t, d = 4n, b = 0-3)
The MUL4B instruction stores the products of the registers Rs + b, Rs + b, Rs + b, Rs + b and the registers Rt, Rt + 1, Rt + 2, and Rt + 3 in the registers Rd, Rd + 1, Rd + 2, and Rd + 3. The MAC4B instruction adds the products of the registers Rs + Rb, Rs + b, Rs + b, Rs + b and the registers Rt, Rt + 1, Rt + 2, and Rt + 3 to the registers Rd, Rd + 1, Rd + 2, and Rd + 3.
[0049]
A procedure for performing 8 * 8 discrete cosine transform and inverse discrete cosine transform using the above processor will be described below.
[0050]
First, matrix data and coefficient data are loaded into a register. This loading operation needs to be performed only once at the beginning of the discrete cosine transform processing of the B block.
[0051]
#Matrix, coefficient load
LD4 COEFF, 0, 1, VR12
LD4 MATRIX, 0, 4, VR16
LD4 MATRIX, 1, 4, VR20
LD4 MATRIX, 2, 4, VR24
LD4 MATRIX, 3,4, VR28
Next, an instruction sequence for performing 8-point one-dimensional discrete cosine transform is shown. OFF indicates an offset from the IMG and is set to 0 in the first processing.
[0052]
# 8-point discrete cosine transform (horizontal)
LD4 IMG, 0 + OFF, 1, VR8
LD4 IMG, 7 + OFF, -1, VR4
ADD4 VR8, VR4, VR0
SUB4 VR8, VR4, VR4
MUL4 VR4, VR12, VR4
MUL4B VR0, VR16, VR8, 0
MAC4B VR0, VR20, VR8, 1
MAC4B VR0, VR24, VR8, 2
MAC4B VR0, VR28, VR8, 3
MUL4B VR4, VR16, VR0, 0
MAC4B VR4, VR20, VR0, 1
MAC4B VR4, VR24, VR0, 2
MAC4B VR4, VR28, VR0, 3
ADD R1, R9, R1
ADD R2, R10, R2
ADD R3, R11, R3
ST4 IMG, 0 + OFF, 2, VR8
ST4 IMG, 1 + OFF, 2, VR0
By performing the conversion process composed of the 18 instructions eight times while increasing OFF by eight, one-dimensional discrete cosine transformation in the horizontal direction is completed for 8 * 8 pixels. Thereafter, OFF is set to 0, 1,. . . , 7 and changing the following instruction sequence 8 times.
[0053]
# 8 discrete cosine transform (vertical)
LD4 IMG, 0 + OFF, 8, VR8
LD4 IMG, 56 + OFF, -8, VR4
ADD4 VR8, VR4, VR0
SUB4 VR8, VR4, VR4
MUL4 VR4, VR12, VR4
MUL4B VR0, VR16, VR8, 0
MAC4B VR0, VR20, VR8, 1
MAC4B VR0, VR24, VR8, 2
MAC4B VR0, VR28, VR8, 3
MUL4B VR4, VR16, VR0, 0
MAC4B VR4, VR20, VR0, 1
MAC4B VR4, VR24, VR0, 2
MAC4B VR4, VR28, VR0, 3
ADD R1, R9, R1
ADD R2, R10, R2
ADD R3, R11, R3
ST4 IMG, 0 + OFF, 16, VR8
ST4 IMG, 56 + OFF, -16, VR0
With the above operation, the 8 * 8 two-dimensional discrete cosine transform is completed. If the number of blocks B to be converted is sufficiently large, 5 instructions necessary for matrix and coefficient loading can be ignored, so that the 2-dimensional discrete cosine transform can be processed with 288 instructions per block.
[0054]
(6) Example 4
In this embodiment, the processing procedure of the present invention is described in C language and used. It is assumed that the coefficients and data are arranged on the main memory as shown in FIG.
[0055]
First, as shown in FIGS. 18 and 19, a data type used for discrete cosine transform and inverse discrete cosine transform is defined as DCTYPE, and M [4] [4] as a 4 * 4 two-dimensional global array constant of the same type. Declare C4 [4]. A 4 * 4 matrix value is set for M, and four coefficients are set for C4. This corresponds to the registers XR0 to XR15 and R12 to R15 of the first embodiment. Next, ld4 (), st4 (), add4 (), sub4 (), mul4 (), trv () are defined as lower functions. ld4 () extracts four DCTYPE values from the memory address indicated by the pointer adr and substitutes them into a one-dimensional array VR having a length of four. Conversely, st4 writes the value of VR into the address indicated by the pointer adr. add4 (), sub4 (), and mul4 () perform addition, subtraction, and multiplication for each element of the one-dimensional arrays VR1 and VR2 each having a length of 4, and assign the result to VR3. trv () calculates the product of the matrix indicated by the 4 * 4 two-dimensional array M and the one-dimensional array VR1 of length 4, and substitutes the result into VR2. These functions perform processing corresponding to LD4, ST4, ADD4, SUB4, MUL4, and TRV of the first embodiment.
[0056]
Based on the above variables and the number of subordinates, functions for performing 8-point discrete cosine transformation and 8 * 8 two-dimensional discrete cosine transformation can be written as dct8 () and dct8_8 () in FIG. Since this program is optimized by a C compiler prepared for each processor to be used, it can be said that the execution performance depends on the compiler performance. However, since the algorithm of the present invention uses only a 4 * 4 coefficient matrix for 8 * 8 discrete cosine transform, it is compared with a program using 64 coefficients that directly implements the 8 * 8 matrix operation shown in FIG. Thus, it is possible to reduce the number of loads / stores between the main memory and the processor, and it can be expected that the compiler outputs a higher-speed machine language instruction sequence. As in the first and second embodiments, in the case of a processor equipped with a matrix operation instruction or SIMD instruction, a result closer to that described in machine language using the built-in function of the compiler can be obtained. It is also possible to describe machine language only for lower functions.
[0057]
(7) Example 5
The present embodiment shows an example in which the 16-point discrete cosine transform is performed using the 8-point discrete cosine transform of the fourth embodiment. Using the dividing method of the present invention, the 16-point transform is divided into 8 points, and the 8-point discrete cosine transform is processed by the function of the fourth embodiment, so that the 4 * 4 coefficient matrix is fixed and 16 points are obtained. Perform a discrete cosine transform of
[0058]
By substituting N = 16 into the equations (9), (10), and (11) derived earlier, it can be seen that it can be divided into two 8-point discrete cosine transforms as shown in FIG. This indicates that a 16-point discrete cosine transform can be divided into two 8-point discrete cosine transforms by adding a pre-process and a post-process.
[0059]
Using this feature, 16-point discrete cosine transform is described using the functions shown in FIGS. 18 and 19 and the dct8 () function shown in FIG. 20 as shown in FIGS. 22, 23, and 24.
[0060]
Similarly, 32 points, 64 points,. . . The 2 ^ n point discrete cosine transform can also be obtained using a 4 * 4 coefficient matrix.
[0061]
(8) Example 6
The conversion apparatus of the present embodiment is different from that of the first embodiment in that the program storage device 109 of the conversion apparatus of FIG. Executable instructions and processing contents are all the same as in the first embodiment.
[0062]
(9) Example 7
The conversion device of this embodiment is different from that of the first embodiment in that the data storage device 110 of the conversion device of FIG. Executable instructions and processing contents are all the same as in the first embodiment.
[0063]
(10) Example 8
The configuration of the conversion apparatus of this embodiment is shown in FIG. The conversion device 2501 is configured by a processor 2502. The processor 2502 is different from the first embodiment in that a program storage device 109 and a data storage device 110 are incorporated in addition to the address generator 106, the register file 107, and the arithmetic unit 108. Executable instructions and processing contents are all the same as in the first embodiment.
[0064]
【The invention's effect】
The present invention can calculate N-point discrete cosine transform and inverse discrete cosine transform using only one fixed (N / 2 ^ k) * (N / 2 ^ k) coefficient matrix. And As a result, the operation of replacing the coefficient matrix, which has conventionally been necessary for each matrix operation, is unnecessary and the overhead can be removed, so that the utilization efficiency of the arithmetic unit is improved.
[0065]
In addition, the scale of operation and the number of registers necessary for storing coefficients can be reduced, and the circuit area can be reduced. This makes it possible to configure a high-speed image / sound compression / decompression processing device while suppressing an increase in circuit area by adding a matrix computing unit or similar arithmetic device to a general-purpose processor.
[Brief description of the drawings]
FIG. 1 shows a data conversion apparatus to which the present invention is applied.
FIG. 2 is an 8-point discrete cosine transform division (butterfly diagram) to which the present invention is applied.
FIG. 3 shows division (matrix representation) of 8-point discrete cosine transform to which the present invention is applied.
FIG. 4 is a conventional 8-point discrete cosine transform (matrix representation).
FIG. 5 is a definition formula of discrete cosine transform.
FIG. 6 shows the properties of coefficients c (k, N) used in discrete cosine transform and inverse discrete cosine transform.
FIG. 7 is a matrix representation according to the definition formula of 8-point one-dimensional discrete cosine transform.
FIG. 8 is a formula modification of the discrete cosine transform according to the present invention.
FIG. 9 is an equation modification (X [N−1]) of the 8-point discrete cosine transform according to the present invention.
10 shows a configuration of a register according to the first embodiment.
FIG. 11 shows processing contents of a TRV instruction in the first embodiment.
12 shows processing contents of an ADD4 instruction in Embodiment 1. FIG.
FIG. 13 shows processing contents of a SUB4 instruction in the first embodiment.
FIG. 14 shows processing contents of a MUL4 instruction in the first embodiment.
FIG. 15 is a main memory arrangement of data used in an 8 * 8-point two-dimensional discrete cosine transform.
FIG. 16 shows a configuration of a register according to the second embodiment.
FIG. 17 shows processing contents of an IPR instruction in the second embodiment.
FIG. 18 is a C language description (lower function 1) of 8-point discrete cosine transform using the 4 * 4 matrix of the fourth embodiment.
FIG. 19 is a C language description (lower function 2) of 8-point discrete cosine transform using the 4 * 4 matrix of the fourth embodiment.
20 is a C language description (upper function) of 8-point 1-dimensional discrete cosine transform and 8 * 8-point 2-dimensional discrete cosine transform of Embodiment 4. FIG.
FIG. 21 is a division (butterfly diagram) of a 16-point discrete cosine transform according to the present invention.
FIG. 22 is a C language description (lower function) of 16-point discrete cosine transform using the 4 * 4 matrix of the fifth embodiment.
FIG. 23 is a C language description (upper function) of 16-point one-dimensional discrete cosine transform according to the fifth embodiment.
FIG. 24 is a C language description (upper function) of 16 * 16 point two-dimensional discrete cosine transform according to the fifth embodiment.
FIG. 25 shows a configuration of an apparatus according to an eighth embodiment.
[Explanation of symbols]
101: Conversion device
102: Processor
103: Storage unit
104: Address bus
105: Data bus
106: Address generator
107: Register file
108: Calculator
109: Program storage device
110: Data storage device
111: Input device
112: Output device
2501: Conversion device
2502: Processor.

Claims (2)

A processor, a program including N (N = 2 ⁿ , where n is a natural number) point discrete cosine transform processing, data to be subjected to the discrete cosine transform processing , matrix data and coefficient data for the discrete cosine transform processing, In a data processing device including a storage device for storing,
The discrete cosine transform processing is divided into 2 ^k (k is a natural number) N / 2 ^k point discrete cosine transform processing according to the processor to be used by adding pre- and post-processing,
The pre- and post-processing is performed such that at least two coefficient matrices of the discrete cosine transform coefficient matrix for the 2 ^k (k is a natural number) N / 2 ^k- point discrete cosine transform process are the same. ,
The processor has a register file, reads the data to be subjected to the discrete cosine transform processing from the storage device, and based on the program stored in the storage device, the preprocessing and 2 ^k (k is a natural number) ) times and the N / 2 ^k point discrete cosine transform, have rows and rear processing, first the register the matrix data and the coefficient data from the storage device of the N / 2 ^k point discrete cosine transform It is characterized in that it is loaded only once into a file and used as the coefficient matrix, and the N / 2 ^k- point discrete cosine transform processing is repeated 2 ^k (k is a natural number) times while the coefficient matrix is held in the register file. Data processing device. A processor, a program including an N (N = 2 ⁿ (n is a natural number)) point inverse discrete cosine transform process, data to be subjected to the inverse discrete cosine transform process, matrix data and coefficients for the inverse discrete cosine transform process In a data processing device including a storage device for storing data,
The inverse discrete cosine transform process is divided into 2 ^k (k is a natural number) N / 2 ^k- point inverse discrete cosine transform processes according to the processor to be used by adding a pre- and post-process,
The pre- and post-processing is performed so that at least two coefficient matrices of the inverse discrete cosine transform coefficient matrix for the 2 ^k (k is a natural number) N / 2 ^k- point inverse discrete cosine transform process are the same. And
The processor has a register file, reads the data to be subjected to the inverse discrete cosine transform processing from the storage device, and based on the program stored in the storage device, the preprocessing and 2 ^k (k is and said N / 2 ^k-point inverse discrete cosine transform processing a natural number) times, have rows and rear process, the N / 2 ^k-point inverse discrete cosine transform first the matrix data and said storage device the coefficient data processing Is loaded into the register file only once to obtain the coefficient matrix, and the N / 2 ^k- point inverse discrete cosine transform process is repeated 2 ^k (k is a natural number) times while the coefficient matrix is held in the register file. A data processing apparatus.

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