JP5546329B2 - Data converter - Google Patents

Description

  The present invention relates to a compression coding technique for image data, and more particularly to a technique for conversion to DC component coefficients in reversible conversion from real space block integer data to frequency space block integer data.

  As an international standard encoding system for still images, there is JEPG recommended by ISO and ITU-T. In JEPPG, image data is divided into blocks of 8 × 8 pixels, and a discrete cosine transform of 8 × 8 size is applied to the blocks to convert them into coefficient data on a frequency space. Then, the coefficient data is quantized, and the quantized data is entropy-encoded to perform irreversible compression of the image data.

  Here, the compression ratio can be adjusted by controlling the quantization step in the above quantization. Information lost due to quantization cannot be recovered, but image data can be compressed more significantly than previous coding by removing the information from a visually inconspicuous part.

  In the JPEG encoding method, it is assumed that quantization is performed with the quantization step set to “1”. In this case, due to the nature of orthonormal transformation called DCT, the sum of squares of the data in the real space in the block and the square sum of the coefficient data in the frequency space are equal, and the signal power is not lost by the transformation. . However, since information is lost, the original data cannot be completely restored even if the coefficient data is inversely transformed. This means that lossless encoding cannot be performed even if the quantization step is set to “1” and quantization is performed. Therefore, in JPEG, this lossless encoding is realized by defining another encoding process called entropy encoding for a prediction difference between adjacent pixels that is completely different from DCT.

  JPEG2000, the international standard encoding method for still images defined next to JPEG, provides two types of wavelet transform for lossy compression and wavelet transform for lossless compression to support lossy compression and lossless compression. It was. The encoding process after the conversion is shared by the lossy compression and the lossless compression, but the conversion is not shared.

  Furthermore, in JPEG-XR defined as an international standard encoding method, integer data common to lossy compression and lossless compression is obtained by using a ladder operation (lifting operation) described in Non-Patent Document 1 described later. Defines a reversible conversion from to integer coefficients. As a result, the entire encoding process can be shared by lossy compression and lossless compression.

  JPEG-XR defines 4 × 4 pixel size blocks, 16 × 16 pixel size macroblocks, and larger tiles, and performs encoding in tile units. The conversion from the real space to the frequency space is performed hierarchically as follows.

  A block having a size of 4 × 4 pixels shown in FIG. 1A is divided into sub-blocks each having four pixels shown in FIGS. Then, a reversible Hadamard transform to an integer coefficient (hereinafter referred to as an integer reversible Hadamard transform) is applied to each sub-block to convert it into four coefficients.

  Furthermore, the transform coefficients at the same level in each of the four sub-blocks are collected to form four sets of transform coefficients, and further transforms are applied to the group. That is, an integer reversible Hadamard transform is again applied to a set of four sub-block DC component coefficients (DC coefficients), and a block-unit DC coefficient (block DC coefficient) and three non-DC coefficients ( AC coefficient) is generated. For the other three sets, each of the four data is regarded as 2 × 2 data, and is converted into an AC coefficient by applying a conversion in which the rotation is converted from the biaxial direction. AC coefficients obtained at this stage are classified as HP coefficients. Eventually, one block data (4 × 4 pixel data) is converted into one block DC coefficient and 15 HP coefficients.

  The block DC coefficients are collected from the 16 blocks constituting the macroblock, and the same block transformation as described above is again applied to the 4 × 4 block DC coefficient data. The AC coefficient obtained by the conversion is classified as an LP coefficient, and the DC component coefficient obtained by the conversion represents a DC component of the macroblock, which is classified as a final DC coefficient. In this specification, the DC coefficient is distinguished from the above-described block DC coefficient by calling it a macroblock DC coefficient so as not to be confused.

  JPEG-XR encoding modes include Spatial Mode and Frequency Mode. In Frequency Mode, all macroblock DC coefficients in a tile are encoded, and then encoded in the order of all LP coefficients in the tile, followed by HP coefficients, to form an encoded stream.

  In the integer reversible transform that uses the lifting operation, the input data is sequentially updated and converted. Therefore, when the block DC coefficient is generated, the AC coefficient is generally generated at the same time. It can be converted more efficiently. However, if only the block DC coefficient is left and the AC coefficient or an intermediate calculation result is deleted without being saved, the efficiency of the conversion process is significantly reduced. Various lifting operations employed in JPEG-XR are described in detail in Japanese Patent Application Laid-Open No. 2004-151620, but it is also assumed that a DC coefficient and an AC coefficient are generated simultaneously.

  Therefore, when one macroblock DC coefficient is generated, normally 15 LP coefficients and 240 (= 15 coefficients × 16 blocks) HP coefficients are generated simultaneously. If these LP coefficients and HP coefficients are discarded, the efficiency of the conversion process becomes extremely low, so it is necessary to temporarily store them in a memory or a buffer.

  The “buffer” here refers to a small-capacity storage unit in an LSI (Large Scale Integrated circuit) on which a function such as compression coding is implemented, and the “memory” refers to a general-purpose memory having a relatively large capacity. The general-purpose memory is connected to the LSI and used as a large-capacity storage unit.

  The storage destination of the LP coefficient and the HP coefficient differs depending on the device. Both coefficients may be stored in memory, and LP coefficients may be stored in a buffer and HP coefficients may be stored in a memory. In any case, a coefficient having a larger amount of data is more likely to be stored in a memory having a larger capacity.

  In the Frequency Mode, a plurality of macroblock DC coefficients in a tile are continuously encoded, and a large amount of HP coefficients and LP coefficients corresponding to the same are generated, so these are basically stored in “memory”. Further, the coefficient data stored in the memory needs to be read at the timing of actual encoding processing and supplied to the LSI. Such saving and reading to the memory means that the memory access bandwidth is increased. Therefore, the approximate number of memory accesses is shown below.

  If the image data to be encoded is stored in the memory, it is necessary to read the image data once by the conversion process to coefficient data on the frequency space.

  When both the LP coefficient and the HP coefficient generated by the conversion processing are stored in the memory, 255 coefficients are stored per 256 pixel data, so that, on average, 255/256 times≈1 writing It is necessary to do. Since the saved coefficient data is always read for later encoding processing, the number of times of reading the coefficient data is equal to the number of times of writing. After all, when counting from the original image data, it is necessary to read or write a total of three times.

  In the case of Spatial Mode instead of Frequency Mode, encoding is performed in the order of DC coefficients, LP coefficients, and HP coefficients in units of macroblocks. In this case, since it is only necessary to hold the coefficient for one macroblock, the coefficient data can be held in a buffer inside the LSI. Therefore, it is only necessary to read the image data from the memory once. In comparison, Frequency Mode has a memory access amount that is three times that of Spatial Mode.

  As described above, if the LP coefficient / HP coefficient is discarded, the efficiency of the conversion process is extremely deteriorated. Therefore, the generated LP coefficient / HP coefficient must be temporarily stored. Will increase. If the generation of only the block DC coefficient can be easily realized, it is not necessary to simultaneously generate the HP coefficient, and as a result, it is not necessary to discard or temporarily store the HP coefficient. The same applies to the generation of LP coefficients when generating macroblock DC coefficients.

JP 2006-197572 A

F. Brukers and A.M. Enden, “New Networks for Perfect Inversion and Perfect Reconstruction” IEEE JSAC, vol. 10, no. 1. pp. 130-137, Jan 1992

  As described above, in the conventional arithmetic unit that implements the conventional integer reversible block transform, it is necessary to generate the DC coefficient and the AC coefficient together in order to perform the calculation efficiently. In the mode in which the AC coefficient is not immediately encoded, it is necessary to temporarily store the AC coefficient in a memory or the like, which causes a new problem of increasing the number of memory accesses.

  The present invention intends to provide a technique for calculating reversible transform DC coefficient data of a coefficient block from a coefficient block of a two-dimensional array with a simple configuration.

In order to solve this problem, for example, the data conversion apparatus of the present invention has the following configuration. That is,
A data conversion device that calculates a DC coefficient among integer conversion coefficients that can be reversibly converted with respect to a block from 4 ⁿ (n is an integer of 2 or more) pieces of integer data,
The block is divided into sub-blocks composed of four preset data, and 0 or 1 indicating whether the total value of the four data composing each sub-block is even or odd for each sub-block Parity generation means for generating parity having any of the following values:
A sum calculating means for calculating a sum of values indicated by all data constituting the block;
Adding means for adding the sum value calculated by the sum calculating means and the parity value of each sub-block calculated by the parity generation unit;
DC coefficient calculating means for calculating reversible integer DC coefficient data for the block from the value obtained by the adding means.

  According to the present invention, it is possible to generate a DC coefficient for integer reversible transformation with a remarkably small circuit scale.

  By providing the arithmetic unit as a DC coefficient dedicated generation circuit in the encoding apparatus, the DC coefficient can be easily generated without generating the LP coefficient / HP coefficient, and the LP coefficient / HP coefficient is stored in the memory. There is no need. Therefore, the number of memory accesses can be reduced by the amount that the LP coefficient / HP coefficient is not required to be written into the memory.

The figure which shows the relationship between a block and four subblocks. The figure showing the structure of the encoding apparatus suitable for application of this invention. The figure showing the structure of a parity generation part. The figure showing the structure of the DC coefficient calculating apparatus which is the 1st Embodiment of this invention. The figure showing the structure of the DC coefficient calculating apparatus which is the 2nd Embodiment of this invention. The figure showing the example of a structure of the DC coefficient calculating apparatus which is the 3rd Embodiment of this invention. The figure showing the structure of the DC coefficient calculating apparatus which is the 4th Embodiment of this invention.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In this embodiment, an example in which the data conversion apparatus of the present invention is applied to JPEG XR will be described.

  In order to generate macroblock DC coefficient data to be encoded, it is necessary to generate block DC coefficient data in 16 blocks constituting the macroblock before that. In the Frequency Mode, when the block DC coefficient data is generated, if the HP coefficient is generated at the same time, the coefficient data becomes enormous, so it is necessary to temporarily store it in a memory or discard it. As mentioned above, this is a very inefficient process.

Therefore, encoding processing procedures based on the present invention are shown in the following 1 to 9, and the configuration of an encoding device capable of realizing the processing procedures is shown in FIG. As shown in FIG. 2, the encoding apparatus includes a first conversion unit 301, a selector 302, a second conversion unit 304, a third conversion unit 303, a memory control unit 305, an image storage unit 306, a selector 307, A layer control unit 308 and a coefficient encoding unit 310 are included. In this encoding apparatus, each processing procedure is shown below. Further, which component is processed by each processing procedure is indicated on the right side of the right arrow (→).
1. Generate block DC coefficient data (→ first conversion unit 301)
2. The generated block DC coefficient data is temporarily saved (→ buffer 309).
Generation of macroblock DC coefficient data from 3.4 × 4 block DC coefficient data (→ third conversion unit 303)
4). Encode macroblock DC coefficient data (→ coefficient encoding unit 310)
(These 1 to 4 are performed for all data in the tile.)
5.4 × 4 block DC coefficient data is block-converted to generate LP coefficients (→ second conversion unit 304)
6). LP coefficient data is encoded (→ coefficient encoding unit 310).
(Do 5 and 6 for all block DC coefficients in tile)
7). Block conversion is performed on image data to generate HP coefficient data (→ second conversion unit 304)
8). HP coefficient data is encoded (→ coefficient encoding unit 310).
(Do 7 and 8 for all image data in the tile)
9. Apply steps 1-8 to tile image data to be encoded next

  Normally, block DC coefficient data and HP coefficient data are generated simultaneously by block conversion (frequency conversion) of image data. Macroblock DC coefficient data and LP coefficient data are also generated simultaneously by block conversion of the block DC coefficient data. On the other hand, in the above processing flow, only the block DC coefficient data or only the macroblock DC coefficient data is generated by the unique method based on this embodiment, that is, the operation using the parity calculated in units of subblocks.

  Hereinafter, in the first embodiment, a method for generating only DC coefficient data among integer transform coefficients that can be reversibly converted to a block will be shown, and in the second and subsequent embodiments, a method for generating macroblock DC coefficient data will be shown.

  As described above, the DC coefficient data for block conversion described in the JPEG-XR recommendation document is the 4 × 4 integer data shown in FIG. 1 (A) and shown in FIGS. 1 (B) to (E). It can be generated by dividing into four sub-blocks and performing conversion processing as follows.

  First, the first-stage integer reversible Hadamard transform is performed on each of the four sub-blocks to obtain four sub-block DC coefficient data. Then, the second-stage integer reversible Hadamard transform is performed on the four sub-block DC coefficient data. The DC coefficient data of the second-stage integer reversible Hadamard transform is the block DC coefficient.

  When focusing on one sub-block (any one of FIGS. 1B to 1E), if the total value of the data in the sub-block is an even number, a value obtained by dividing the total value by 2, The values indicated by the sub-block DC coefficient data of the sub-block are equal. That is, no rounding error occurs in the first-stage integer reversible Hadamard transform for the target sub-block.

  On the other hand, when the total value of the data in the target sub-block is an odd number, the value obtained by dividing the total value by 2 is appended with 0.5 decimal data. The value obtained by rounding up the decimal point becomes the value of integer sub-block DC coefficient data compatible with JPEG-XR. In this case, a rounding error of +0.5 occurs. A rounding error of +0.5 occurs for each sub-block having an odd sum, and this is input to the second-stage Hadamard transform.

  On the other hand, in the case of linear orthogonal transformation such as DCT (discrete cosine transformation) in JPEG or MPEG, the total value of all data in a block (4 × 4 size) is obtained, and linear transformation is performed simply by multiplying this by 1/4. DC coefficients can be calculated. The total value of all the data can be calculated by adding the input data in order without worrying about the input order of the data, and a linear conversion DC coefficient can be generated with a simple configuration.

[First embodiment: When four data in the row direction are input in parallel]
Therefore, in the first embodiment, an arithmetic device capable of calculating a block DC coefficient of integer reversible transformation based on the total value of all the data in the block is disclosed. According to the arithmetic device, the block DC coefficient can be generated with a simple configuration. The block DC coefficient calculation device described below is also applied to the first conversion unit 301 and the third conversion unit 303 in FIG.

  First, the major feature of the first embodiment is that the sub-block-unit parity calculation method and the configuration of the parity generation unit are shown first, and then the configuration of the block DC coefficient calculation device using the parity generation unit. Indicates.

  The sum of the four data input to the second-stage Hadamard transform shown above is larger than the total value of the intra-block data in the linear transform by the rounding error that occurs for each sub-block. Therefore, if the rounding error of the integer reversible Hadamard transform of each sub-block can be accurately added to the total value of the data in the block, the sum of the four data input to the second-stage Hadamard transform can be calculated.

  Here, as described above, the sum value of the data in the block does not depend on the input order of the data, it is only necessary to add the data in the input order, and the calculation can be performed with a simple configuration.

  On the other hand, whether or not a rounding error occurs in units of sub-blocks needs to be calculated depending on the data input order. However, the signal representing the rounding error (+0.5 or 0) is 1 bit, which matches the odd / even (sex) of the sum value of the data in the sub-block.

  Therefore, in the present embodiment, for each of the four sub-blocks, the parity (bit) Pi (i = 0, 1, 2, 3) is calculated and generated to determine whether the total value of the data is odd or even. . Hereinafter, the calculation contents of the parity Pi will be described. Data [i] (i = 0, 1, 2, 3,..., 13, 14) of 4 × 4 block data in FIG. , 15).

The parity of the sub-block of FIG. 1B is P0, the parity of the sub-block of FIG. 1C is P1, the parity of the sub-block of FIG. 1D is P2, and the parity of the sub-block of FIG. Assuming P3, they can be calculated by the following equation (1).
P0 = (Data [0] & 1) ^ (Data [3] & 1) ^ (Data [12] & 1) ^ (Data [15] & 1)
P1 = (Data [1] & 1) ^ (Data [2] & 1) ^ (Data [13] & 1) ^ (Data [14] & 1)
P2 = (Data [4] & 1) ^ (Data [7] & 1) ^ (Data [8] & 1) ^ (Data [11] & 1)
P3 = (Data [5] & 1) ^ (Data [6] & 1) ^ (Data [9] & 1) ^ (Data [10] & 1)… (1)
Here, in the above equation (1), “&” indicates a logical product operator between the same bits, and “^” indicates an exclusive logical OR operator between the bits. Therefore, the least significant bit of Data [i] is extracted by “Data [i] & 1”. As a result of the above calculation, P0 = 0 if the total value of the four data in the sub-block of FIG. 1B is an even number, and P0 = 1 if the total value is an odd number. The same applies to the other sub-blocks.

Further, instead of the above equation (1), the calculation can be performed as in the following equation (2). This calculation is effective when the four data of the sub-block are input in parallel and the four data can be easily added.
P0 = (Data [0] + Data [3] + Data [12] + Data [15]) & 1
P1 = (Data [1] + Data [2] + Data [13] + Data [14]) & 1
P2 = (Data [4] + Data [7] + Data [8] + Data [11]) & 1
P3 = (Data [5] + Data [6] + Data [9] + Data [10]) & 1… (2)
Here, the operator “+” literally represents addition of numerical values.

  FIG. 3 shows the configuration of the parity generation unit 400 that generates the parity P0, P1, P2, P3 based on the parity calculation formula shown in Expression (1). Here, it is assumed that block data is input in parallel in the order of raster scanning. Also, it is assumed that only the least significant bit (LSB) of each of four pieces of data input in parallel is input to the parity generation unit 400 of FIG.

In the configuration of FIG. 3, the least significant bit of the four data input in parallel is input from the terminal group 401, but the first four parallel input data {Data [0], Data [1], Data From [2], Data [3]}
(Data [0] & 1) ^ (Data [3] & 1)
(Data [1] & 1) ^ (Data [2] & 1)
Is calculated.

From the second 4 parallel input data {Data [4], Data [5], Data [6], Data [7]}
(Data [4] & 1) ^ (Data [7] & 1)
(Data [5] & 1) ^ (Data [6] & 1)
Is calculated.

  These operations are calculated by the exclusive OR elements 411 and 412, pass through the exclusive OR elements 413 and 414, and are stored in 1-bit registers R 0, R 1, R 2 and R 3 indicated by reference numerals 420 to 423. Stored in The bit data stored in these registers R0, R1, R2, and R3 is used to generate parities P0, P1, P2, and P3.

Next, from the third 4 parallel input data {Data [8], Data [9], Data [10], Data [11]}
(Data [8] & 1) ^ (Data [11] & 1)
(Data [9] & 1) ^ (Data [10] & 1)
Is calculated. These are subjected to exclusive OR operation by the exclusive OR elements 413 and 414 and the 1-bit data held in the registers R2 and R3 selected by the selectors 431 and 432, respectively, and are connected to the terminals as parity P2 and P3. 441 and 442.

From the last 4th parallel input data {Data [12], Data [13], Data [14], Data [15]}
(Data [12] & 1) ^ (Data [15] & 1)
(Data [13] & 1) ^ (Data [14] & 1)
Is calculated. These are subjected to exclusive OR operation with 1-bit data held in the registers R0 and R1 selected by the selectors 431 and 432 and exclusive OR elements 413 and 414, respectively, and are connected to the terminals as parity P0 and P1. 441 and 442.

  Assuming that one block is processed in four cycles, the parity output from the exclusive OR elements 413 and 414 to the terminals 441 and 442 is valid only in the latter two cycles, and in the first two cycles, the meanings from the terminals 441 and 442 are significant. No data is output. Therefore, both the two signals are masked to “0” during the first two cycles by a control signal (not shown) and a mask circuit.

  FIG. 4 shows the configuration of a device that calculates the block DC coefficient of integer reversible transform using the parity generation unit 400 described above, that is, the configuration of the first embodiment. Main components other than the parity generation unit 400 are a total calculation unit 510 that calculates the total value of input data, a parity adder 520 that adds the parity as a value, and an output of the total calculation unit that shifts the output to the right by 2 bits. Bit shifter 530.

  In the conventional calculation for obtaining the block DC coefficient, in addition to the first and second Hadamard transformers, a data order conversion buffer for processing input data in sub-block units in the raster scanning order is required. It was. In the DC coefficient calculation apparatus according to the present embodiment, the data order conversion buffer is not necessary, and a first adder 511 that calculates a sum value of four data input in parallel from terminals 501 to 504, and the adder 511 Only the second adder 512 for accumulating the addition results obtained from the above and the register 513 are required. With these first adder 511 and second adder 512, the total value of the data in the block can be obtained. Here, it is assumed that the register 513 is cleared to zero each time the calculation of the block DC coefficient of one block is started.

  If the input data of the first adder 511 is four data constituting a sub-block, a value obtained by adding the four data and dividing by two becomes the DC coefficient of the sub-block. This means that the least significant bit of the data output from the first adder 511 to the second adder 512 is the first bit after the decimal point. On the other hand, since the parity P0 calculated based on the equation (1) or (2) represents a rounding error of 0.5, the weight when viewed as a value is the same as 1 bit after the decimal point of the fixed-point data. .

  Therefore, the parity Pi (i = 0, 1, 2, 3) has the same weight as the least significant bit of the input data to the second adder 512, and the two parities output from the parity generation unit 400 are When adding by the parity adder 520, it adds to the least significant bit of accumulation addition data. As a result, the sum value of the sub-block DC coefficients obtained by adding all rounding errors superimposed by the first-stage integer reversible Hadamard transform is obtained as the output of the second adder 512.

  Similarly, the DC coefficient of the 4th-order Hadamard transform in the second stage is a value obtained by dividing the total value of the four data by 2, and therefore, the decimal point position in the output of the second adder 512 is set to the decimal point position of the input. Shift one bit in the upper bit direction. Originally, the input of the second adder is fixed-point data in which the lower 1 bit is a decimal number, so the output of the second adder 512 is finally the decimal data of the lower 2 bits.

  According to the interpretation of the JPEG-XR recommendation, the second-stage integer reversible Hadamard transform corresponds to a rounding process that rounds off the decimal part. Therefore, the 2-bit shifter 530 right-shifts the lower 2 bits of the value held in the register 513 and simply truncates it, and outputs the result as a block DC coefficient.

  Note that the operation shown in FIG. 4 can be realized by either software or hardware, but when realized by hardware, the shifter 530 is connected to the output terminal 505 by shifting the signal line for 2 bits of the output bus of the register 513. Just do it.

  In addition, in block processing, when block data is delivered in an array, it is easy to add sub-block data. Therefore, it is efficient to calculate parity by the operation shown in Equation (2).

The following shows the processing procedure for calculating the block DC coefficient of the integer reversible transform using the parity calculation method shown in Equation (2).
sum0 = Data [0] + Data [3] + Data [12] + Data [15];
sum1 = Data [1] + Data [2] + Data [13] + Data [14];
sum2 = Data [4] + Data [7] + Data [8] + Data [11];
sum3 = Data [5] + Data [6] + Data [9] + Data [10];
P0 = sum0 &1;
P1 = sum1 &1;
P2 = sum2 &1;
P3 = sum3 &1;
sum = sum0 + sum1 + sum2 + sum3 + P0 + P1 + P2 + P3;
DC = sum >>2;
(Here, “x >> y” represents shifting x by y bits in the lower direction)

  In the first to fourth lines, data is added for each sub-block, and in the fifth to eighth lines, the least significant bit is extracted as a parity from the data addition result for each sub-block. On the line, all the addition results and parity are added. In the last tenth line, the summation result is shifted right by 2 bits to generate a block DC coefficient for integer reversible transformation.

[Second Embodiment: When Adding Input Data One by One]
The configuration of FIG. 4 in the first embodiment can be applied to the first conversion unit 301 and the third conversion unit 303 of FIG. 2, but there are four lines for 4 × 4 data forming one block. It was premised on data being input in parallel and processed. However, paying attention to the third conversion unit 303 (an integer reversible conversion unit that generates a macroblock DC coefficient), the third conversion unit 303 inputs the block DC coefficient output from the block DC coefficient calculation unit of FIG. Therefore, it is possible to input the input DC coefficients one by one. More specifically, since the conversion unit of FIG. 4 processes 4 × 4 data in units of four and generates one block DC coefficient every four cycles, the DC coefficient is intermittently generated one by one. 3 converters 303.

  With such an input format, only one adder is required to calculate the total value of input data necessary to generate the macroblock DC coefficient. In this case as well, the parity of each sub-block is generated by performing the operation shown in Equation (1), which extracts only the least significant bit of the input data and calculates the exclusive OR for each sub-block.

  Therefore, in the second embodiment, in particular, FIG. 5 shows a configuration of a macroblock DC coefficient calculation apparatus that can be used as the third conversion unit 303 in FIG. As shown in the figure, the macroblock DC coefficient arithmetic unit includes a parity generation unit 702 that calculates parity from the least significant bit of input data, a parity adder 721 that adds parity to the input data, and a total that calculates the total value of the input data. A calculation unit 730 and a shifter 530 are included. Components having the same functions as those in FIGS. 3 and 4 are given the same part numbers.

  It can be seen that all of the parity generation unit 702, the parity adder 721, and the sum calculation unit 730 have a simple configuration as compared to the first embodiment (FIG. 3). Here, the parity calculation in the parity generation unit 702 is performed as follows. It is assumed that 4 × 4 sub-block DC coefficients are input from the input terminal 701 in the raster scan order.

  First, the registers R0, R1, R2, and R3 are initialized to “0”. At this timing, the register 732 is also cleared to zero.

  Thereafter, each time one sub-block DC coefficient is input from the input terminal 701, the selector 715 selects R0, R1, R1, R0, R2, R3, R3, R2, R2, R3, R3, R2, R0, R1. , R1, R0 are selected in this order, and an exclusive OR is calculated with the least significant bit of the input sub-block DC coefficient, and stored again in the selected register.

  By the operation of the selector 715, the register R0 is selected when the 0th, third, twelfth, and fifteenth data are input. Therefore, an operation equivalent to the equation (1) is performed, and the operation result is set as the parity P0. It is output to the parity adder 721.

  Similarly, the register R1 is selected when the first, second, thirteenth, and fourteenth data are input, the register R2 is selected when the fourth, seventh, eighth, and eleventh data are input, and the register R3 is selected when the fifth, sixth, ninth, and tenth data are input. Selected when the second data is entered. For this reason, an operation equivalent to the parity calculation formula shown in Formula (1) is performed.

  The output of the parity generation unit 702 is valid only when the 10, 11, 14, and 15th data is input. Otherwise, the output to the parity adder 721 is “0” by a control signal and a mask circuit (not shown). To prevent unnecessary data from being added.

  The generated effective parities P0, P1, P2, and P3 are added to the input data by the parity adder 721, and the addition result is cumulatively added to the register 732 of the sum calculation unit 730. Finally, when the result of adding all the data in the block and the parity is stored in the register 732, the value is output to the shifter 530.

  After that, as in the first embodiment, the output of the sum calculation unit is right-shifted by 2 bits by the shifter 530, and the shifted value is output as a macroblock DC coefficient. In the first embodiment, the configuration of the arithmetic unit is shown in which data is input in parallel in four, and in the second embodiment, data is intermittently input one by one. In addition to this, the input form may be 2-parallel, 8-parallel, 16-parallel input, etc., but those skilled in the art can easily configure the arithmetic device corresponding to them from the two embodiments described here. Would be able to.

  Also, the parity adder 721 and the adder 731 in the sum calculation unit can be combined into one adder with carry input that can add 1-bit parity as carry. In this case, the parity adding means is embodied as a carry input of an adder with carry input. An example in which this is used is shown in a third embodiment shown below.

[Third Embodiment: Only three parity calculations show two types of arithmetic processing]
In the first and second embodiments, the parity is calculated for each sub-block. In the third embodiment, an example in which part of the parity calculation is omitted and the circuit scale is further reduced will be described.

  Specifically, among the four parities calculated in the first and second embodiments, only three parities are calculated and the macroblock DC coefficient is calculated.

  Based on the second embodiment, FIG. 6A shows a configuration of an arithmetic device that embodies the third embodiment, and FIG. 6B shows a modification thereof.

  In the third embodiment, the operation of the parity P0 is omitted, and instead, the least significant bit of the output of the sum operation unit is added as the parity P0 in the configuration shown in FIG. It is the configuration shown in FIG. 6B that is always added as “1”. The reason why such calculation is possible will be described below.

  When the total value of 4 × 4 data to be converted is an even number, the sum of the four parities is even, and when the sum of the data is an odd number, the sum of the parity is odd. Therefore, the result of adding the parity to the data sum is always an even number.

  From another viewpoint, if the result of adding three parities to the total value of data is an even number, the remaining parity is “0”. Further, if the result of adding three parities to the total value of data is an odd number, the remaining parity is “1”. In other words, it can be said that the remaining parity value is uniquely determined from the result of adding three parities to the total value of the data, and the remaining parity is equal to the least significant bit of the addition result.

  Therefore, it is possible to add the least significant bit as a result of adding three parities to the total value of data as the remaining parity. An arithmetic device based on this principle has a configuration shown in FIG. In the figure, reference numeral 801 is an adder with carry input described at the end of the second embodiment, reference numeral 802 is an adder for adding the least significant bit of the total value as the remaining parity, and reference numeral 803 is It is a parity generation unit that calculates only the three parities. The other components are the same as those of the same part number in FIG.

  On the other hand, when “1” is added when the least significant bit of the result of adding three parities to the sum of data is “0”, “1” is just added by truncating 2 bits after the decimal point. "Is truncated. When the least significant bit is “1”, “1” needs to be added.

  Therefore, there is no problem even if “1” is always added regardless of the value of the least significant bit. An arithmetic unit based on this is shown in FIG. In this configuration, by setting the initial value of the register 804 in the sum operation unit to “1”, the operation of adding “1” as a parity is omitted. It is also possible to output “1” at the timing of outputting P0 from the parity generation unit and add it.

[Fourth embodiment: rounded down in sub-block units, rounded up in block units]
In the first, second, and third embodiments, the calculation of a DC coefficient that is compatible with the integer reversible transformation in JPEG-XR has been taken into consideration, so rounding processing in units of sub-blocks in the first stage is rounded up. Was cut off at the second block level.

  The present invention is not limited to integer reversible conversion in JPEG-XR, and is also effective for, for example, 4 × 4 block 16-point integer reversible Adahr conversion.

  The 16-point integer reversible Haadard transform to which the present invention is applicable is described in, for example, Japanese Patent Registration No. 0390990. Here, the 4th order integer reversible Hadamard transform is applied to the 4th column or row direction as sub-blocks, and the 2nd step is a 4th order using 4 data with the column and row direction changed as a unit. Apply integer reversible Hadamard transform. This realizes a two-dimensional integer reversible Hadamard transform for 4 × 4 block data, that is, a 16-point integer reversible Hadamard transform. In the conversion, there are a great number of combinations of rounding processes of the first-stage and second-stage integer reversible Hadamard transforms.

  Here, as an example, the configuration of the arithmetic unit in the present invention is shown when the rounding process of the first stage conversion is rounded down and the rounding process of the second stage conversion is rounded up.

  The rounding error generated by the rounding process is +0.5 in the case of rounding up, and is −0.5 in the case of rounding down. In order to reflect this rounding error in the total value of the block data, the parity for the sub-block which is the first stage conversion unit is subtracted from the total value of the data. In order to round up the rounding process of the second stage conversion, 2-bit data of “10” is added to the total value of the data reflecting the parity, and the addition result is right-shifted by 2 bits. The 2 bits “10” to be added here is data having a weight of 0.5 because it is data of 2 bits after the decimal point.

  FIG. 7 shows the configuration of an arithmetic unit that obtains the DC coefficient by incorporating the contents described above into the second embodiment.

  The processing is basically the same as in the second embodiment, but there are the following differences.

  The four processes for adding the parity are replaced with a process for subtracting the parity (or adding by inverting the sign of the positive / negative sign), and “10” (binary), that is, “2” is added to the total data immediately before the 2-bit shift. "(Decimal number) is added.

The embodiment according to the present invention has been described above. In the above embodiment, the size of the coefficient block is 4 × 4. However, since the number of coefficients included in the sub-block is only four, it is generally applicable to 4 ⁿ (n is an integer of 2 or more). The present invention is not limited to the above embodiment.

(Other examples)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

Claims (4)

A data conversion device that calculates a DC coefficient among integer conversion coefficients that can be reversibly converted with respect to a block from 4 ⁿ (n is an integer of 2 or more) pieces of integer data,
The block is divided into sub-blocks composed of four preset data, and 0 or 1 indicating whether the total value of the four data composing each sub-block is even or odd for each sub-block Parity generation means for generating parity having any of the following values:
A sum calculating means for calculating a sum of values indicated by all data constituting the block;
Adding means for adding the sum value calculated by the sum calculating means and the parity value of each sub-block calculated by the parity generation unit;
A data conversion apparatus comprising: DC coefficient calculation means for calculating reversible integer DC coefficient data for the block from the value obtained by the addition means. The logical AND operator between the same bits is “&”, the exclusive OR operator is “^”, and the four data constituting the target sub-block are Data [0], Data [1], When expressed as Data [2], Data [3]
The parity generating means calculates the parity P of the target sub-block,
P = (Data [0] & 1) ^ (Data [1] & 1) ^ (Data [2] & 1) ^ (Data [3] & 1)
The data conversion apparatus according to claim 1, further comprising: a circuit that calculates as follows.   2. The DC coefficient computing means bit-shifts the value of the addition result by the adding means, and outputs data obtained by the bit shift as DC coefficient data for lossless transformation of the coefficient block. Or the data conversion device according to 2; 2. The data conversion device according to claim 1, wherein n = 2 is set, and a block is formed by collecting 4 × 4 DC coefficients calculated by the first data conversion device. A data conversion apparatus characterized in that a macroblock DC coefficient is calculated by performing data conversion of the block in a data conversion apparatus.

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