KR100236972B1 - Discrete cosine transform apparatus for decoding and encoding with low-transmission rate - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Two-dimensional discrete cosine converter for low bit rate compression / restore.

2. The technical problem to be solved by the invention

It is intended to reduce the circuit cost and to reduce the delay time of the forward / reverse discrete cosine converter by using small devices.

3. Summary of Solution to Invention

First selecting means for selecting one of serial data input from an external source and second discrete cosine transformed data; Means for serial / parallel or parallel / serial conversion in accordance with the data input from the first selection means; Second selection means for selecting one of the parallel data inputted from the serial / parallel conversion means and the data of the first discrete cosine transformed; Means for transforming data input from the second selecting means into one-dimensional discrete cosine transform; And storage means for converting the data into column priority or row priority parallel data according to the type of data inputted from the discrete cosine converting means.

4. Important uses of the invention.

Used to compress / restore image data.

Description

2D Discrete Cosine Converter for Low Bit Rate Compression / Restore

The present invention relates to a two-dimensional discrete cosine transformer for low bit rate compression / restore, and in particular, to reduce the circuit cost by using a parallel pre-memory and a one-dimensional discrete cosine transform (DCT) used for image signal processing, The present invention relates to a two-dimensional discrete cosine converter for reducing the delay time of the forward / reverse discrete cosine converter.

1 is a block diagram of a conventional two-dimensional discrete cosine converter, in which 11 is a multiplexer, 12 is a serial / parallel converter, 13 is a 1-dimensional discrete cosine converter, 14 is a parallel / serial converter, and 15 is a prememory. .

When the amount of computation required for the two-dimensional discrete cosine transform is small, it is economical to implement the two-dimensional discrete cosine transducer using one one-dimensional discrete cosine transducer and transpose memory as shown in FIG.

It is possible to use the serial / parallel converter 12, or the parallel / serial converter 14, according to the method of supplying data to one circuit composed of shift registers in FIG.

In FIG. 1, data sequentially input in a row major order through the multiplexer 11 is converted into parallel data through a serial / parallel converter 12 and then one-dimensional discrete in the one-dimensional discrete cosine converter 13. A cosine transform operation is performed to convert the sequential data through the parallel / serial converter 14 and store it in the pre-memory memory 15.

Data stored in the pre-memory memory 15 is inputted to the one-dimensional discrete cosine converter 13 in a column major order through the multiplexer 11 and the serial / parallel converter 12 to perform a one-dimensional discrete cosine conversion operation. Once again, the results are supplied externally in sequential data format via the bottle / serial converter 14.

The two-dimensional discrete cosine transformer of FIG. 1 can be used efficiently when the amount of calculation required for the discrete cosine transform is small.

The screen size of QCIF, a screen format used in H.263, an international standard for low-rate video compression / restore, is 176x144. Using the fast discrete cosine transform algorithm, 8x8 discrete cosine transforms (DCT) can be performed by 96 multiplications, 466 additions, and a total of 562 operations, so that two-dimensional discrete cosine transforms are performed on 30 QCIF screens per second. The calculation required is as follows.

30 x 99 x 6 x 562 ≒ 10 x 10 ⁶

However, since video compression and restoration such as H.263 requires one forward and backward discrete cosine transformers for encoding and one reverse discrete cosine transformer for decoding, the amount of computation required to perform the discrete cosine transform is 30x106.

This calculation amount is relatively large to be performed by a digital signal processor (DSP) which is a software method without using a dedicated discrete cosine converter. This is because the digital signal processor (DSP) must perform various operations in addition to the discrete cosine transform.

In this case, a configuration similar to that of FIG. 2 can be considered. FIG. 2 shows a schematic diagram of a two-dimensional discrete cosine converter using a conventional sequential pre-memory memory. In the drawing, 21 and 25 are serial / parallel converters and 22 and 26 are one-dimensional discrete cosine. The transducers 23 and 27 represent the bottle / serial transducer and 24 the transpose memory, respectively.

The conventional two-dimensional discrete cosine converter inputs parallel data to the one-dimensional discrete cosine converter 22 through the serial / parallel converter 12 to calculate the discrete cosine transform coefficients, and then converts the serial data through the parallel / serial converter 23 again. Is converted into the transpose memory 24 and stored.

Then, the output of the pre-memory 24 is converted into parallel data again through the serial / parallel converter 25, and the same pixel value as the result of the reverse discrete cosine transform is output through the one-dimensional discrete cosine converter 26, The / serial converter 27 converts this to serial data and outputs it.

That is, the conventional two-dimensional discrete cosine converter as shown in FIG. 2 uses two one-dimensional discrete cosine transformers 22 and 26 and the pre-memory 24 to perform one discrete cosine transform coefficient (forward discrete cosine transform). ) Or pixel value (result of inverse discrete cosine transform), using such a conventional two-dimensional discrete cosine converter is a waste of circuitry.

For example, the efficiency of this two-dimensional discrete cosine converter is about 10% when the two-dimensional discrete cosine converter, which outputs one result (discrete cosine transform coefficient or pixel value) every clock, operates at 33 MHz.

Therefore, the discrete cosine converter for low bit rate image compression / restore requires a more economical method than using a two-dimensional discrete cosine converter, which is a widely used method but uses a dedicated converter.

Therefore, in order to solve the problems of the prior art as described above, in implementing the two-dimensional discrete cosine converter, the minimum element to facilitate the compression / recovery after decomposing the video signal having a low transmission rate into a frequency component It is an object of the present invention to provide a two-dimensional discrete cosine converter that can simplify the construction and greatly reduce the manufacturing cost and reduce the delay time of the forward / reverse discrete cosine converter.

1 is a block diagram of a conventional two-dimensional discrete cosine converter.

2 is a block diagram of a two-dimensional discrete cosine transducer using a conventional sequential memory.

3 is a block diagram of a parallel pre-memory for 8x8 discrete cosine transform used in the present invention.

4 is a diagram illustrating an embodiment of a two-dimensional discrete cosine converter for low-rate compression / restore according to the present invention.

* Explanation of symbols for main parts of the drawings

41,43: Multiplexer 42: Serial / Parallel, Bottle / Serial Converter

44: one-dimensional discrete cosine converter 45: parallel transpose memory

In order to achieve the above object, the present invention, in the two-dimensional discrete cosine converter, according to the selection control signal transmitted from the outside, to selectively output the serial data input from the outside and the second-order discrete cosine transformed parallel data feedback First selection means; A data array for converting serial data selected and output by the first selecting means into parallel data, converting parallel data selected and output by the first selecting means into serial data and outputting the converted serial data to the outside Conversion means; Second selecting means for selectively outputting parallel data converted and transferred by said data array converting means and first discrete cosine transformed data in response to said selection control signal; Discrete cosine transforming means for outputting the second-order discrete cosine transformed parallel data obtained by transforming data transmitted from the second selection means by one-dimensional discrete cosine transform; And converting the parallel data input from the discrete cosine converting means into column priority to the parallel data of the row priority, temporarily storing the parallel data, and outputting the converted data to the second selecting means, and inputting the row priority from the discrete cosine converting means. Parallel transposition storing means for converting the parallel data into parallel data having a column priority and storing the temporary data and outputting the temporary data to the second selection means.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a block diagram of a parallel transposition memory used in the present invention.

As shown in FIG. 3, the parallel pre-memory has a size of 8x8 with 16-bit internal precision, an Omega Network 31, an Inverse Omega Network 33, and a memory unit. It consists of 32.

The switch used in the omega network 31 and the reverse omega network 33 is a 2-bit 2x2 switch, and the memory unit is composed of eight 64x2 RAMs and 16 two-bit registers coupled to the input / output terminals of the RAM. .

The switches used in the two networks 31 and 33 change the switching state in word units (8 clocks), and each RAM inputs and outputs two bits of information every clock.

The parallel transposition memory outputs parallel data inputted in column (row) priority order in a row (column) priority order.

Using parallel prememory eliminates the need for the serial / parallel and parallel / serial converters required for the parallel-to-parallel data conversion between the parallel one-dimensional discrete cosine converter and the prememory.

Parallel prememory eliminates the use of two parallel one-dimensional discrete cosine converters and two parallel-to-parallel converters between the prememory memory, significantly reducing costs and eliminating data from passing through the serial-to-parallel converter. The delay of the two-dimensional discrete cosine transducer is reduced to improve the performance of the two-dimensional discrete cosine transducer. However, when only one one-dimensional discrete cosine converter is used as shown in FIG. 1, the cost is not easily reduced. This is because one serial / parallel converter and parallel / serial converter are inevitable due to the input / output characteristics of the two-dimensional discrete cosine converter.

4 is a diagram illustrating an embodiment of a two-dimensional discrete cosine converter for compression / restore of a low data rate according to the present invention, in which 41 and 43 are multiplexers, 42 are parallel / parallel, parallel / serial converters. Denotes a one-dimensional discrete cosine transducer, and 45 denotes parallel transposition memory.

In FIG. 4, the serial / parallel, parallel / serial converter 42 is used as a serial / parallel converter or a parallel / serial converter according to the same circuit or data supply method as the general serial / parallel converter or the parallel / serial converter.

The first multiplexer 41 selects data sequentially input in a row first order according to a selection control signal input from the outside, and outputs the data to the serial / parallel converter 42, and the serial / parallel converter 42 receives the first multiplexer. Serial data input from the firearm 41 is converted into parallel data and output.

The second multiplexer 43 selects parallel data input from the serial / parallel converter 42 by using a selection control signal input from the outside and outputs the parallel data to the one-dimensional discrete cosine converter 44.

The one-dimensional discrete cosine converter 44 performs a one-dimensional discrete cosine transform operation on the data inputted from the second multiplexer 43 in a row-first order, and stores the result in the parallel pre-memory memory 45.

This process continues until all 64 data are stored in the parallel transposition memory 45 in the case of 8x8 discrete cosine transform (DCT) / inverse discrete cosine transform (IDCT).

Data stored in the parallel pre-memory memory 45 is input to the second multiplexer 43 in the order of column priority, and the second multiplexer 43 selects this data by means of a selection control signal and again uses a one-dimensional discrete cosine converter 44. ), And the one-dimensional discrete cosine converter 44 performs the one-dimensional discrete cosine transform operation again.

The final transformed data in the one-dimensional discrete cosine converter 44 is input to the first multiplexer 41, and the first multiplexer 41 selects it and outputs it to the bottle / serial converter 42, and the bottle / serial converter. Reference numeral 42 converts serial data from the first multiplexer 41 and serially converts serial data and outputs the serial data.

This process continues until all 64 data are supplied externally in the case of 8x8 discrete cosine transform / inverse discrete cosine transform.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

As described above, the present invention implements a two-dimensional discrete cosine converter with only a minimum number of elements, and thus, when the internal precision is 16 bits, it corresponds to about 500 registers in the case of a 16x16 two-dimensional discrete cosine converter compared to a conventional two-dimensional discrete cosine converter. In the case of an 8x8 two-dimensional discrete cosine converter, the cost of about 250 registers can be reduced, and the number of times each data passes through the serial-to-parallel converter is reduced by half. By reducing the delay time, the performance of the two-dimensional discrete cosine converter is improved.

Claims (2)

2. A two-dimensional discrete cosine converter, comprising: first selecting means for selectively outputting serial data inputted from outside and second-order discrete cosine transformed parallel data according to a selection control signal transmitted from the outside; A data array for converting serial data selected and output by the first selecting means into parallel data, converting parallel data selected and output by the first selecting means into serial data and outputting the converted serial data to the outside Conversion means; Second selecting means for selectively outputting parallel data converted and transferred by said data array converting means and first discrete cosine transformed data in response to said selection control signal; Discrete cosine transforming means for outputting the second-order discrete cosine transformed parallel data obtained by transforming data transmitted from the second selection means by one-dimensional discrete cosine transform; And converting the parallel data input from the discrete cosine converting means into column priority to the parallel data of the row priority, temporarily storing the parallel data, and outputting the converted data to the second selecting means, and inputting the row priority from the discrete cosine converting means. And a transposition pre-storing means for converting parallel data into parallel data of a column priority and storing the temporary data and outputting the temporary data to the second selection means. 2. The two-dimensional compression / restore of claim 1, wherein each of the first and second selection means includes a multiplexer for selecting and outputting a signal indicated by the selection control signal among two input signals. Discrete cosine converter.