JP2007227606A - Method of manufacturing semiconductor wafer, and semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor wafer which can prevent spread of contamination over a semiconductor wafer, and to provide the semiconductor wafer. <P>SOLUTION: In the method of manufacturing the semiconductor wafer 51, an element isolation layer 12 for separating an SOI forming region 13 and a bulk forming region is first formed. Then, a resist film 18 for removing a silicon oxide film 14 on the SOI forming region 13 is formed. In this case, since a peripheral rinsing or peripheral exposure is not applied to the resist film on a peripheral portion 11b of the silicon substrate 11, the element isolation layer 12 of the peripheral portion 11b remains. After that, a silicon germanium layer 15 and a silicon layer 16 are formed by selective epitaxial growth on only the SOI forming region 13 where a surface 11a is exposed. Since the silicon germanium layer 15 is not formed on the peripheral portion 11b, a transfer system can be prevented from contacting the silicon germanium layer 15 causing contamination, although it contacts the peripheral portion 11b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer manufacturing method and a semiconductor wafer, and more particularly to a technique for forming an SOI (Silicon On Insulator) structure on a semiconductor wafer.

  A transistor formed on an SOI substrate has a smaller junction capacitance (capacitance between the source / drain region and the substrate) than that formed on a bulk silicon substrate. It has great advantages such as being operable. Non-Patent Document 1 discloses a SBSI (Separation by Bonding Si Islands) method in which a transistor can be formed on an SOI structure at a low cost by partially forming an SOI layer on a bulk silicon substrate.

  A method for forming an SOI structure on a bulk silicon substrate constituting a semiconductor wafer using the SBSI method will be described with reference to FIG. First, an element isolation layer 103 that separates an SOI formation region 102 from other regions is formed on a bulk silicon substrate 101. Next, in order to define the SOI formation region 102, a resist pattern (not shown) having an opening corresponding to the SOI formation region 102 is formed. Thereafter, using the resist pattern as a mask, the silicon oxide film (not shown) in the SOI formation region 102 is removed, and the surface 101a of the bulk silicon substrate 101 is exposed.

  At the same time, when the bulk silicon substrate 101 is transported to a subsequent processing step, the resist pattern in the peripheral portion 101b of the bulk silicon substrate 101, which is a portion where the transport system and the bulk silicon substrate 101 are in contact, is subjected to peripheral rinsing or peripheral processing. Remove by exposure. Then, by etching using this resist pattern as a mask, the element isolation layer 103 in the peripheral portion 101b is removed, and the surface 101a of the bulk silicon substrate 101 is exposed. Next, the bulk silicon substrate 101 is transferred to a subsequent processing step, and a silicon germanium (SiGe) layer and a silicon (Si) layer (both not shown) are epitaxially grown on the SOI formation region 102 on the bulk silicon substrate 101. Thereafter, the SOI structure is disposed on the semiconductor wafer 111 by forming according to the SBSI method described above.

T.A. Sakai et al. , Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

  However, when epitaxial growth is performed, a silicon germanium layer is epitaxially grown on the peripheral portion 101 b where the surface 101 a of the bulk silicon substrate 101 is exposed together with the SOI formation region 102. As a result, when the bulk silicon substrate 101 is transported, the silicon germanium layer that is the cause of the contamination grown on the peripheral portion 101b contacts the transport system, and there is a problem that germanium spreads in the furnace for processing. . In addition, when another semiconductor wafer is placed in the furnace, there is a problem that the other semiconductor wafer is contaminated with germanium.

  An object of this invention is to provide the manufacturing method of a semiconductor wafer which can suppress that a contamination spreads to a semiconductor wafer, and a semiconductor wafer.

  In order to achieve the above object, a method for manufacturing a semiconductor wafer according to the present invention includes a step of forming an oxide film on a semiconductor substrate, and an element isolation layer for separating an SOI formation region and another region on the semiconductor substrate. Forming the semiconductor substrate including a peripheral portion thereof; selectively removing the oxide film in the SOI formation region to expose the semiconductor substrate; and forming the SOI substrate in the SOI formation region on the semiconductor substrate. Selectively depositing one semiconductor layer by epitaxial growth, and selectively depositing a second semiconductor layer having an etching rate lower than that of the first semiconductor layer on the first semiconductor layer by epitaxial growth; Supporting the peripheral portion of the semiconductor substrate and transporting the semiconductor substrate to a subsequent process.

  According to this method, since the semiconductor substrate is exposed only in the SOI formation region, the first semiconductor layer and the second semiconductor layer can be selectively formed by epitaxial growth only in the SOI formation region without the oxide film. Therefore, when the semiconductor substrate is transported to the subsequent process, even if the transport system and the peripheral portion of the semiconductor substrate come into contact with each other, the first semiconductor layer that causes contamination is not formed in the peripheral portion. It is possible to suppress contact with the layer. As a result, contamination of the furnace in which the treatment is performed with the first semiconductor layer can be suppressed, and as a result, the contamination of the first semiconductor layer on other semiconductor substrates can be suppressed.

  In order to achieve the above object, a method for manufacturing a semiconductor wafer according to the present invention includes a step of forming an oxide film on a semiconductor substrate, and an element isolation layer for separating an SOI formation region and another region on the semiconductor substrate. Forming the semiconductor substrate including a peripheral portion thereof; selectively removing the oxide film in the SOI formation region to expose the semiconductor substrate; and forming the SOI substrate in the SOI formation region on the semiconductor substrate. Selectively depositing one semiconductor layer by epitaxial growth, and selectively depositing a second semiconductor layer having an etching rate lower than that of the first semiconductor layer on the first semiconductor layer by epitaxial growth; Supporting the peripheral portion of the semiconductor substrate and transporting the semiconductor substrate to a subsequent process; and the second semiconductor layer and the first semiconductor around the element region Forming a support hole exposing part of the semiconductor substrate and filling the support hole and covering the second semiconductor layer so as to cover the second semiconductor layer And etching the other part, leaving a region including the support hole and the element region, and thereby supporting the first semiconductor layer and the first semiconductor layer located below the support. (2) forming an exposed surface that exposes a part of an end of the semiconductor layer; and etching the first semiconductor layer through the exposed surface to thereby form the second semiconductor layer and the semiconductor substrate in the element region A step of forming a cavity portion between the first semiconductor layer, a step of forming a buried insulating layer in the cavity portion, and a planarization treatment of the upper portion of the second semiconductor layer so that the support is located on the second semiconductor layer. Remove some of Has a degree, the.

  According to this method, since the semiconductor substrate is exposed only in the SOI formation region, the first semiconductor layer and the second semiconductor layer can be selectively formed by epitaxial growth only in the SOI formation region without the oxide film. Therefore, when the semiconductor substrate is transported to the subsequent process, even if the peripheral portion of the semiconductor substrate that is in contact with the transport system and the transport system are in contact with each other, the first semiconductor layer that causes contamination is not formed in the peripheral portion. Therefore, it is possible to suppress contact with the first semiconductor layer. Thereby, it can suppress that the furnace which processes is contaminated with a 1st semiconductor layer, and can suppress that the contamination of a 1st semiconductor layer spreads to another semiconductor substrate. As a result, a semiconductor wafer that is not contaminated by the first semiconductor layer can be provided.

  In the method for manufacturing a semiconductor wafer according to the present invention, the first semiconductor layer is a silicon germanium layer, and the second semiconductor layer is a silicon layer.

  According to this method, by selective epitaxial growth, a silicon germanium layer is selectively formed only in an SOI formation region without an oxide film, and a silicon germanium layer is not formed in a peripheral portion in contact with the transport system on which the oxide film is formed. Therefore, it is possible to suppress contact between the transport system and silicon germanium when transporting the semiconductor substrate. Thereby, contamination by silicon germanium can be suppressed.

  In the method of manufacturing a semiconductor wafer according to the present invention, in the exposing step, the resist film in the peripheral portion of the resist film is peripherally rinsed to partially remove the oxide film on the semiconductor substrate by etching. Or it is not removed by peripheral exposure.

  According to this method, since the resist film in the peripheral portion of the semiconductor substrate is not removed, the oxide film in the peripheral portion can be left on the semiconductor substrate even when etching is performed using the resist film as a mask. As a result, the second semiconductor layer that causes contamination can be formed only in the SOI formation region without the oxide film by selective epitaxial growth. As a result, when the semiconductor substrate is transported while supporting the peripheral portion, it is possible to suppress contact between the transport system and the silicon germanium layer.

  In order to achieve the above object, in a semiconductor wafer according to the present invention, an element isolation layer that separates an SOI formation region from another region is formed on a semiconductor substrate including a peripheral portion of the semiconductor substrate. A semiconductor wafer having an SOI structure in which a buried insulating layer is formed on the semiconductor substrate in place of a silicon germanium layer formed by epitaxial growth, and a silicon layer is formed on the buried insulating layer by epitaxial growth. When the semiconductor wafer is transferred, the silicon germanium layer is not formed on the peripheral portion of the semiconductor substrate in contact with the transfer system.

  According to this configuration, the silicon germanium layer is selectively formed only in the SOI formation region in the semiconductor substrate, and the silicon germanium layer is not formed on the periphery of the semiconductor substrate. Even if the peripheral portion of the semiconductor substrate comes into contact, it is possible to suppress contact between the transport system and the silicon germanium layer that is a cause of contamination. Thereby, it is possible to suppress contamination of the furnace in which the treatment is performed with silicon germanium, and as a result, it is possible to suppress the contamination of silicon germanium to other semiconductor substrates.

  Hereinafter, a method for manufacturing a semiconductor wafer and an embodiment of a semiconductor wafer according to the present invention will be described with reference to the drawings.

  1 to 10 are schematic cross-sectional views showing a method for manufacturing a semiconductor wafer. Hereinafter, a method for manufacturing a semiconductor wafer will be described with reference to FIGS.

In the process shown in FIG. 1, an element isolation layer 12 is formed on a silicon substrate 11 as a semiconductor substrate constituting a semiconductor wafer. The element isolation layer 12 is, for example, a LOCOS (Local Oxidation of Silicon) oxide film, and is formed to electrically insulate the SOI formation region 13 from a bulk formation region (not shown) as another region. . Hereinafter, description of the bulk formation region is omitted. First, a silicon oxide film 14 (SiO ₂ ) as an oxide film (not shown) is formed on the silicon substrate 11. Next, a silicon nitride film (SiN) (not shown) is formed in the SOI formation region 13 on the silicon substrate 11 by using a photolithography technique and an etching technique. Thereafter, the element isolation layer 12 is formed by oxidizing the silicon substrate 11 other than the SOI formation region 13 using the silicon nitride film as a mask.

  In the step shown in FIG. 2, the surface 11 a of the silicon substrate 11 in the SOI formation region 13 is exposed in order to selectively epitaxially grow only the SOI formation region 13. First, a resist film 18 having an opening corresponding to the SOI formation region 13 is formed on the silicon substrate 11 using a photolithography technique. The portion of the resist film 18 corresponding to the peripheral portion 11b of the silicon substrate 11 is left without being removed by peripheral rinsing or peripheral exposure. Next, using this resist film 18 as a mask, the silicon oxide film 14 (see FIG. 1) in the SOI formation region 13 is removed by etching. As a result, the surface 11 a of the silicon substrate 11 is exposed only in the SOI formation region 13. In addition, the peripheral portion 11b of the silicon substrate 11 is in a state in which the element isolation layer 12 made of an oxide film is still formed due to the presence of the resist film 18.

  In the step shown in FIG. 3, a silicon germanium layer 15 as a first semiconductor layer and a silicon layer 16 as a second semiconductor layer are formed on the silicon substrate 11. Specifically, only the SOI formation region 13 on the silicon substrate 11 is selectively formed using an epitaxial growth technique. In order to improve the crystallinity of the silicon germanium layer 15, a silicon buffer layer may be formed on the silicon substrate 11 by epitaxial growth before the silicon germanium layer 15 is formed. Thus, the single crystal silicon germanium layer 15 and the single crystal silicon layer 16 are formed only in the SOI formation region 13 where the surface 11a of the silicon substrate 11 is exposed. Hereinafter, the silicon germanium layer 15 and the silicon layer 16 are collectively referred to as a single crystal epitaxial film 17. On the other hand, the silicon germanium layer 15 and the silicon layer 16 are not formed in the other regions covered with the oxide film, particularly the peripheral portion 11b of the silicon substrate 11 because the element isolation layer 12 remains formed. .

  As described above, the silicon germanium layer 15 is not formed on the peripheral portion 11b by selective epitaxial growth, so that when the silicon substrate 11 is transferred to each processing step, the transfer system (cassette, transfer system, etc.) and the peripheral portion 11b are in contact with each other. Even so, contact with the silicon germanium layer 15 can be prevented. Therefore, for example, germanium contamination can be prevented from spreading in the furnace for processing. Thereafter, contamination with germanium can be suppressed when the silicon substrate 11 is transported to each processing step.

  In the step shown in FIG. 4, the first support hole 21 and the second support hole 22 are formed in the single crystal epitaxial film 17. First, it corresponds to a first support hole forming region 23 in which the first support hole 21 is formed and a second support hole forming region 24 in which the second support hole 22 is formed. A resist pattern (not shown) having an opening in the region is formed using a photolithography technique. Next, using this resist pattern as a mask, the silicon layer 16, silicon germanium layer 15, and part of the silicon substrate 11 in the first support hole forming region 23 and the second support hole forming region 24 are sequentially removed by etching. To do. As a result, the first support hole 21 and the second support hole 22 are formed in the SOI formation region 13.

  Further, by opening the first support hole 21 and the second support hole 22, the one side surface 17 a and the other side surface 17 b of the single crystal epitaxial film 17 are exposed, and the surface 11 a of the silicon substrate 11 is exposed. A region between the first support hole 21 and the second support hole 22 is an element region.

In the step shown in FIG. 5, a support forming layer 27 for forming the support 26 (see FIG. 6) is formed on the entire silicon substrate 11. The support forming layer 27 is, for example, a silicon oxide film (SiO ₂ ). First, the resist pattern used in the previous process is removed. Next, a support forming layer 27 such as a silicon oxide film is embedded in the first support hole 21 and the second support hole 22 and the silicon layer 16 is covered by, for example, a CVD (Chemical Vapor Deposition) method. In this way, a film is formed on the entire silicon substrate 11.

  In the process shown in FIG. 6, the support 26 for supporting the silicon layer 16 is completed. First, a part of the support forming layer 27 other than the support forming region 28 where the support 26 is formed is removed. The removal method is performed by etching using a resist pattern (not shown) having an opening other than a planar region of the support 26 as a mask. Further, using the same resist pattern as a mask, a part of the single crystal epitaxial film 17 other than the support forming region 28 is removed by etching.

  As described above, the support 26 is formed from the support forming layer 27, and the support 26 and the single crystal epitaxial film 17 are in close contact with each other. In addition, the first side surface and the second side surface (the front side and the back side in FIG. 6) of the support 26 are exposed, and the single crystal epitaxial film is located below the first side surface and the second side surface of the support 26. 17 is an exposed surface in which end faces (a front side and a back side in FIG. 6) are exposed.

  In the step shown in FIG. 7, the silicon germanium layer 15 (see FIG. 6) on the lower side of the support 26 is selectively removed. First, the resist pattern used in the previous process is removed. Next, an etching solution such as hydrofluoric acid is brought into contact with the single crystal epitaxial film 17 below the support 26. At this time, etching is performed from the exposed surface of the single crystal epitaxial film 17. Since the silicon layer 16 has a lower etching rate than the silicon germanium layer 15, the silicon germanium layer 15 can be selectively etched and removed while leaving the silicon layer 16. As a result, a hollow cavity 29 is formed between the silicon substrate 11 and the silicon layer 16.

  In the step shown in FIG. 8, a buried insulating layer 31 (BOX layer: Buried Oxide layer) is formed in the cavity 29 (see FIG. 7). The buried insulating layer 31 is, for example, a silicon oxide film, and is formed by reacting silicon and oxygen contained in the silicon substrate 11 and the silicon layer 16 by using a thermal oxidation method.

  In the process shown in FIG. 9, the substrate 41 is completed. First, in order to electrically insulate the SOI structure, an insulating film 32 made of a silicon oxide film is formed all over the silicon substrate 11. The insulating film 32 is formed by, for example, a CVD method. Next, the entire surface of the silicon substrate 11 is flattened (flattening process) by CMP polishing (Chemical Mechanical Polishing). Thereby, a part of the insulating film 32 and the support body 26 is removed. Thereafter, a part of the unnecessary support 26 and a part of the insulating film 32 are removed up to the upper surface 16 a of the silicon layer 16. Thereby, the upper surface 16a of the silicon layer 16 is exposed, and a structure (SOI structure) in which the silicon layer 16 is element-isolated by the insulating film 32 and the buried insulating layer 31 is formed on the silicon substrate 11, and as a result, the substrate 41 is formed. Is completed.

  As described above, in order to leave the element isolation layer 12 in the peripheral part 11b of the silicon substrate 11, the peripheral part 11b is not subjected to peripheral rinsing or exposure, so that the selective epitaxial growth is performed on the element isolation layer 12 in the peripheral part 11b. The growth of the silicon germanium layer 15 can be suppressed. Thereby, when the silicon substrate 11 is transported to the subsequent processing step, even if the peripheral portion 11b of the silicon substrate 11 and the transport system come into contact with each other, the silicon germanium layer 15 does not exist in the peripheral portion 11b. It becomes possible to suppress contamination with germanium. As a result, it is possible to suppress the contamination from spreading to other substrates 41.

  In the process shown in FIG. 10, the semiconductor wafer 51 is completed. First, thermal oxidation is performed on the surface of the silicon layer 16 to form a gate insulating film 52 on the surface of the silicon layer 16. Then, a polycrystalline silicon layer is formed on the gate insulating film 52 by, eg, CVD. After that, the gate electrode 53 is formed on the gate insulating film 52 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, by using the gate electrode 53 as a mask, impurities such as As (arsenic), P (phosphorus), and B (boron) are ion-implanted into the silicon layer 16, so that the low electrode disposed on both sides of the gate electrode 53. LDD layers 54 a and 54 b made of concentration impurity introduction layers are formed on the silicon layer 16. Then, for example, an insulating layer is formed on the silicon layer 16 on which the LDD layers 54a and 54b are formed by the CVD method, and the insulating layer is etched back by dry etching such as RIE. Walls 55a and 55b are formed, respectively.

  Then, impurities such as As, P, and B are ion-implanted into the silicon layer 16 using the gate electrode 53 and the sidewalls 55a and 55b as a mask. As a result, source / drain electrode layers 56a and 56b made of high-concentration impurity introduced layers are formed on the side of the sidewalls 55a and 55b in the silicon layer 16, and as a result, a transistor is completed. In addition, by forming a bulk element in a bulk formation region (not shown), the semiconductor wafer 51 in which the SOI element and the bulk element are mixedly mounted on the silicon substrate 11 is completed.

  As described above, since the silicon germanium layer 15 is not formed on the peripheral portion 11b of the semiconductor wafer 51, the transfer system and the peripheral portion 11b of the semiconductor wafer 51 are in contact with each other when the semiconductor wafer 51 is transferred to the subsequent process. However, since the silicon germanium layer 15 is not formed on the peripheral portion 11b, it is possible to prevent the furnace for processing from being contaminated with silicon germanium. Thereby, the manufacturing method of the semiconductor wafer 51 which can suppress that the contamination by germanium spreads to the other semiconductor wafer 51 can be provided.

  As described above in detail, according to the semiconductor wafer manufacturing method and the semiconductor wafer of this embodiment, the following effects can be obtained.

  (1) According to this embodiment, the peripheral portion 11b of the silicon substrate 11 is not subjected to peripheral rinsing or exposure, and the resist film 18 having an opening corresponding to the SOI forming region 13 is used to form the SOI forming region 13. By removing a certain silicon oxide film 14 by etching, the surface 11 a of the silicon substrate 11 is exposed only in the SOI formation region 13. As a result, the element isolation layer 12 remains as it is formed on the peripheral portion 11b of the silicon substrate 11, and silicon is formed on the element isolation layer 12 of the peripheral portion 11b when selectively epitaxially grown on the silicon substrate 11. The formation of the germanium layer 15 can be suppressed. Therefore, when the silicon substrate 11 is transported to the subsequent process, even if the transport system and the peripheral portion 11b of the silicon substrate 11 come into contact with each other, the silicon germanium layer 15 that causes contamination is not formed on the peripheral portion 11b. It is possible to suppress contact with the silicon germanium layer 15. Thereby, it is possible to suppress contamination of the furnace in which the processing is performed with germanium, and as a result, it is possible to suppress the contamination of germanium on the other silicon substrate 11.

  In addition, this embodiment is not limited above, It can also implement with the following forms.

  (Modification 1) As described above, instead of preventing the silicon germanium layer 15 from growing on the element isolation layer 12 by selective epitaxial growth, for example, polycrystalline silicon formed on the element isolation layer 12 is used. The germanium layer may be decomposed and removed with chlorine gas or the like.

  (Modification 2) As described above, silicon is used as the material for the semiconductor substrate. However, the present invention is not limited to this. For example, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe Etc. may be used.

  (Modification 3) As described above, silicon germanium has been described as an example of the material of the first semiconductor layer and silicon is used as the material of the second semiconductor layer. However, the second semiconductor layer having a lower etching rate than the first semiconductor layer is used. For example, as a material of the first semiconductor layer and the second semiconductor layer, a combination selected from Ge, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or the like may be used. Good.

The schematic diagram which shows the manufacturing method of the semiconductor wafer in one Embodiment. The schematic cross section which shows the manufacturing method of a semiconductor wafer. The schematic cross section which shows the manufacturing method of a semiconductor wafer. The schematic cross section which shows the manufacturing method of a semiconductor wafer. The schematic cross section which shows the manufacturing method of a semiconductor wafer. The schematic cross section which shows the manufacturing method of a semiconductor wafer. The schematic cross section which shows the manufacturing method of a semiconductor wafer. The schematic cross section which shows the manufacturing method of a semiconductor wafer. The schematic cross section which shows the manufacturing method of a semiconductor wafer. 1 is a schematic cross-sectional view showing a semiconductor wafer manufacturing method and a structure of a semiconductor wafer. The schematic cross section which shows the manufacturing method of the conventional semiconductor wafer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Silicon substrate as a semiconductor substrate, 11a ... Surface, 11b ... Peripheral part, 12 ... Element isolation layer, 13 ... SOI formation area as 1st area | region, 14 ... Silicon oxide film as an oxide film, 15 ... 1st semiconductor A silicon germanium layer as a layer, 16 ... a silicon layer as a second semiconductor layer, 16a ... an upper surface, 17 ... a single crystal epitaxial film, 18 ... a resist film, 21 ... a first support hole, 22 ... a second support hole, 23 ... 1st support body hole formation area, 24 ... 2nd support body hole formation area, 26 ... Support body, 27 ... Support body formation layer, 28 ... Support body formation area, 29 ... Cavity part, 31 ... Embedded insulating layer, 32 ... Insulating film, 41 ... Substrate, 51 ... Semiconductor wafer, 52 ... Gate insulating film, 53 ... Gate electrode, 54a, 54b ... LDD layer, 55a, 55b ... Side wall, 56a ... Source electrode layer, 56 ... drain electrode layer.

Claims (5)

Forming an oxide film on a semiconductor substrate;
Forming an element isolation layer that separates an SOI formation region and another region on the semiconductor substrate including a peripheral portion of the semiconductor substrate;
Selectively removing the oxide film in the SOI formation region to expose the semiconductor substrate;
Selectively depositing a first semiconductor layer on the SOI formation region on the semiconductor substrate by epitaxial growth;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer by selective epitaxial growth;
And a step of supporting the peripheral portion of the semiconductor substrate and transporting the semiconductor substrate to a subsequent step. Forming an oxide film on a semiconductor substrate;
Forming an element isolation layer that separates an SOI formation region and another region on the semiconductor substrate including a peripheral portion of the semiconductor substrate;
Selectively removing the oxide film in the SOI formation region to expose the semiconductor substrate;
Selectively depositing a first semiconductor layer on the SOI formation region on the semiconductor substrate by epitaxial growth;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer by selective epitaxial growth;
Supporting the peripheral portion of the semiconductor substrate and transporting the semiconductor substrate to a subsequent process;
Forming a support hole that exposes the semiconductor substrate by removing a part of the second semiconductor layer and the first semiconductor layer around an element region;
Forming a support forming layer on the semiconductor substrate so as to fill the support hole and cover the second semiconductor layer;
Etching the other part, leaving the region including the support hole and the element region, thereby supporting the support and the end portions of the first semiconductor layer and the second semiconductor layer located below the support Forming an exposed surface that exposes a portion of
Etching the first semiconductor layer through the exposed surface to form a cavity between the second semiconductor layer in the element region and the semiconductor substrate;
Forming a buried insulating layer in the cavity;
Planarizing the second semiconductor layer and removing a portion of the support located on the second semiconductor layer;
A method for producing a semiconductor wafer, comprising: A method for producing a semiconductor wafer according to claim 1 or 2,
The first semiconductor layer is a silicon germanium layer;
The method of manufacturing a semiconductor wafer, wherein the second semiconductor layer is a silicon layer. A method for producing a semiconductor wafer according to any one of claims 1 to 3,
In the exposing step, the resist film in the peripheral portion of the resist film is not removed by peripheral rinse or peripheral exposure so as to partially remove the oxide film on the semiconductor substrate by etching. A method for manufacturing a semiconductor wafer. An element isolation layer that separates the SOI formation region from other regions is formed on the semiconductor substrate including the peripheral portion of the semiconductor substrate,
A buried insulating layer is formed on the semiconductor substrate in the SOI formation region instead of the silicon germanium layer formed by epitaxial growth,
A semiconductor wafer having an SOI structure in which a silicon layer is formed by epitaxial growth on the buried insulating layer;
A semiconductor wafer, wherein the silicon germanium layer is not formed in the peripheral portion of the semiconductor substrate that contacts a transport system when the semiconductor wafer is transported.

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