JP2007215237A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which chip area increment is small and a high-speed input initial stage latch is provided. <P>SOLUTION: The semiconductor device comprises a first latch 10 for receiving an input signal and holding the input signal for only a half cycle period of a first clock signal; a delay element connected to the output of the first latch; a second latch 11 connected to the output of the delay element and holding a signal supplied from the delay element for only a half cycle period of a second clock signal; and a circuit for adjusting at least one of the timings of the first clock signal and the second clock signal so that a signal latched by the first latch in the half cycle period of the first clock signal is latched by the second latch through the delay element in the half cycle period of a succeeding second clock signal, wherein the first latch and the second latch are constituted each by a transfer gate and a third latch having two inverters. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device having an input latch that captures a signal in synchronization with a clock signal.

  When the operating speed of the CPU increases, a high-speed operation is required also in a semiconductor device around the CPU such as a semiconductor memory device.

  For example, in a synchronous (clock synchronous type) memory, a command input (or address input) is input so as to satisfy the setup time / hold time requirement with respect to the rising edge of the external clock. An input command (or address) is normally latched by a latch circuit (edge trigger latch) at the first stage of input, and is maintained for a period of 1 tCK (tCK is a clock cycle), and is decoded by a decoder within this data holding period. Is done.

  FIG. 1 is a diagram showing the configuration of a conventional command (or address) input circuit and decoder. FIG. 2 is a timing chart showing the operation of the configuration of FIG.

  The configuration of FIG. 1 includes a latch 10, a latch 11, and a decoder 12. The latch 10 includes a gated inverter 13, an inverter 14, and a gated inverter 15. The latch 11 includes a gated inverter 16, an inverter 17, and a gated inverter 18. The latch 10 and the latch 11 are provided for each of the input signals in0 and in1.

  The latch 10 is supplied with a complementary signal intCLK_c of the clock signal intCLK_t, and the latch 11 is supplied with the clock signal intCLK_t. The gated inverter 13 of the latch 10 inverts the input signal in0 (or in1) when the clock signal intCLK_t is LOW (when the complementary signal intCLK_c is HIGH), and the latch circuit 20 including the inverter 14 and the gated inverter 15 is inverted. To supply. When the clock signal intCLK_t becomes HIGH, the input signal is latched by the latch circuit 20. At this time, the gated inverter 16 of the latch 11 is in the open state, and the signals latched by the latch circuit 20 are output as the latch signals in0lat and in1lat via the latch 11. When the clock signal intCLK_t subsequently becomes LOW, the gated inverter 16 is closed, and the input signal is latched in the latch circuit 21 including the inverter 17 and the gated inverter 18. While the clock signal intCLK_t is LOW, the next input signal is supplied to the latch 10, but the first input signal latched in the latch circuit 21 is held until the clock signal intCLK_t next becomes HIGH.

  In this way, as shown in FIG. 2, the latch signals in0lat and in1lat obtained by latching the input signal are maintained for a period of 1tCK (tCK is a clock cycle). Within this period, the decoder 12 of FIG. 1 decodes the latch signals in0lat and in1lat, and outputs an output signal out <0: 3> as a decoding result.

  In order to determine the input signal before the latch 10 latches the input signal, it is necessary to ensure the setup time as shown in FIG. In the above system, in addition to the setup time, a decoding time required for the decoder 12 to decode the input signal is required. Therefore, a delay corresponding to the sum of the setup time and the decoding time occurs until the decoding result is obtained from the input of the data signal.

  In order to solve this problem, a system is used in which a decoding operation is performed before latching using the setup time.

  FIG. 3 is a diagram showing a configuration of a conventional command (or address) input circuit and decoder that realizes high speed using the setup time. FIG. 4 is a timing chart showing the operation of the configuration of FIG. As shown in FIGS. 3 and 4, in this system, the decoder 12 is provided in the preceding stage of the latches 10 and 11, and the decoding process is executed within the setup time of the latches, thereby speeding up the process.

  However, this method requires many latches because the decoded signal is latched independently. For example, when decoding a 2-bit input as shown in FIG. 3, a total of 8 latches are required, and when decoding 3 bits, a total of 16 latches are required.

  In this system, the timing adjustment circuit 22 is used to delay the clock signal, thereby setting the latch timing at an appropriate timing that allows for the decoding time by the decoder. Therefore, it is necessary to secure a large timing margin in consideration of timing deviation caused by manufacturing variation of the timing adjustment circuit 22 or voltage fluctuation.

  Therefore, in the conventional method shown in FIG. 3, the chip area increases, and a sufficient speed margin cannot be achieved in order to secure a large timing margin by taking into account timing deviations due to manufacturing variations and voltage fluctuations. Further, if such a large timing margin is to be ensured for the setup time, there is a problem that the timing margin for the hold time is reduced. In general, when the clock cycle is shortened, the setup time and hold time are shortened, so that it is more difficult to secure a timing margin in a system in which the clock speed is advanced.

  In view of the above, it is an object of the present invention to provide a semiconductor device including a high-speed input first stage latch with a small increase in chip area.

  A semiconductor device according to the present invention includes a first latch that receives an input signal and holds the input signal for a half cycle period of a first clock signal, a delay element connected to the output of the first latch, and the delay A second latch connected to the output of the element and holding a signal supplied from the delay element for a half cycle period of a second clock signal; and the first latch in the half cycle period of the first clock signal Of the first clock signal and the second clock signal so that the latched signal is latched into the second latch via the delay element during the half cycle period of the second clock signal that follows. And a circuit for adjusting at least one of the timings, wherein the first latch and the second latch include a transfer gate and a third latch having two inverters.

  A semiconductor device according to another aspect of the present invention includes a first latch that receives a command signal and holds the command signal for a half cycle period of the first clock signal, and a command decoder connected to the output of the first latch A second latch connected to the output of the command decoder and holding a decode signal supplied from the command decoder for a half cycle period of the second clock signal; and the decode signal supplied from the second latch And a controller that performs access control based on the first and second latches, wherein the first latch and the second latch include a transfer gate and a third latch having two inverters. .

  According to another aspect of the present invention, a semiconductor device includes: a first latch that receives an address signal and holds the address signal for a half cycle period of the first clock signal; and an output of the first latch. A delay element that transfers an address signal to which the delay element is connected, and a second latch that is connected to the other end of the delay element and holds an address signal supplied from the delay element for a half cycle period of the second clock signal. In addition, the first latch and the second latch include a transfer gate and a third latch having two inverters.

  According to at least one embodiment of the present invention, the decoder is arranged between the two latches constituting the edge trigger circuit, and the decoding process is executed using the setup time, so that the time delay due to the decoder process is hidden. I can do it. In this configuration, the same number of latches as the number of input signals need be provided in the first stage, so that a high-speed latch / decode operation can be realized with a smaller number of circuit elements than in the conventional configuration. Further, by adjusting the timing of the clock signal, reliable data transfer from the first latch to the second latch can be realized.

  Further, since a delay element is arranged between two latches constituting the edge trigger circuit and signal transfer is executed using the setup time, a time delay due to signal transfer can be hidden. As a result, high-speed data transfer can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 5 is a block diagram showing a first embodiment of the latch circuit according to the present invention. In the first embodiment, the two latches constituting the edge trigger circuit, that is, the first stage latch that holds the signal transferred during the HIGH period of the clock signal and the signal that is transferred during the HIGH period of the clock signal are LOW. The latch of the next stage that is held for the period is separated, and a decoder is arranged between them. In FIG. 5, the same components as those of FIG. 1 are referred to by the same numerals, and a detailed description thereof will be omitted.

  The configuration in FIG. 5 includes a latch 10, a latch 11, a decoder 12, and a pulse width extension circuit 31. A decoder 12 is disposed between the latch 10 and the latch 11. The latch 10 is supplied with a clock signal intCLK_c ′ that is a complementary signal of the signal obtained by extending the pulse width of the clock signal intCLK_t by the pulse width extension circuit 31. The latch 11 is supplied with a clock signal intCLKd_t ′ obtained by delaying the clock signal intCLK_t by the timing delay 32. Here, the timing delay 32 is a wiring delay that is inevitably caused when the distance between the latches 10 and 11 is increased by providing the decoder 12 between the latches 10 and 11, for example. When it is necessary to consider the decoding time of the decoder 12, a delay circuit or the like may be intentionally inserted. The input signals in0 and in1 are command signals or address signals for a semiconductor device such as a semiconductor memory device.

  FIG. 6 is a timing waveform diagram showing the operation of the configuration of FIG.

  As shown in FIG. 6, when input signals in0 and in1 are input while securing a setup time until the fall of the complementary clock signal intCLK_c ′, this signal passes through the latch 10 and is supplied to the decoder 12. The decoder 12 performs a decoding process using the setup time. At the rising timing of the clock signal intCLK_t, the latch 10 latches the input signals in0 and in1. The signal inlat <0: 1> latched in the latch 10 is converted into a decode signal dec <0: 3> by the decoder 12, passes through the latch 11 released from the latched state, and is output as an output signal out <0: 3>. Supplied to the next stage. Next, the decode signal dec <0: 3> is latched in the latch 11 at the timing when the delayed clock signal intCLKd_t ′ falls. The signal latched by the latch 11 is supplied to the next stage as the output signal out <0: 3>, and the delayed clock signal intCLKd_t ′ is held for LOW. In this manner, the output signal out <0: 3> is output for a period of 1 tCK (tCK is a clock cycle).

  Here, since the clock signal intCLKd_t ′ is delayed by a timing delay 32 such as a wiring delay, in order for the latch signal of the latch 10 to be transferred to the latch 11 via the decoder 12 without any problem, the latch signal of the latch 10 It is necessary to lengthen the holding time. Assuming that the latch signal holding period of the latch 10 remains the HIGH period of the original clock signal intCLK_t, when the latch 11 latches data at the falling edge of the delayed clock signal intCLKd_t ′, the content of the latch 10 is the next signal. Because it has been rewritten in, correct signal transfer cannot be performed.

  Therefore, in the configuration shown in FIG. 5, the pulse width extending circuit 31 extends the latch signal holding period of the latch 10 so that correct signal transfer can be performed as shown in FIG.

  As described above, in the present invention, since the decoder is arranged between the two latches constituting the edge trigger circuit and the decoding process is executed using the setup time, the time delay due to the decoder process can be hidden. In this configuration, it is only necessary to provide the same number of first stage latches as the number of input signals. Therefore, a high-speed latch / decode operation can be realized with a smaller number of circuit elements than the conventional configuration of FIG. In addition, since the pulse width expansion circuit only extends the pulse width, the latch timing of the first stage latch is basically an edge timing with no timing adjustment, which is a timing compared to the case of using the timing adjustment circuit as in the past. It is difficult for deviation to occur. Note that it is not necessary to provide the pulse width expansion circuit when the timing margin is sufficient.

  FIG. 7 is a block diagram showing a second embodiment of the latch circuit according to the present invention. In the second embodiment, a pulse width suppression circuit 33 is provided instead of the pulse width expansion circuit 31 of FIG. In FIG. 7, the same components as those of FIG. 5 are referred to by the same numerals.

  The configuration of FIG. 7 includes latch 10, latch 11, decoder 12, and timing delay 32. A decoder 12 is disposed between the latch 10 and the latch 11. The latch 10 is supplied with a clock signal intCLK_c that is a complementary signal of the clock signal intCLK_t. The clock signal intCLKd_t ″ whose pulse width is shortened by the pulse width suppression circuit 33 is supplied to the latch 11 with respect to the clock signal delayed by the timing delay 32. The input signals in0 and in1 are command signals or address signals for a semiconductor device such as a semiconductor memory device.

  FIG. 8 is a timing waveform diagram showing the operation of the configuration of FIG.

  As shown in FIG. 8, when input signals in0 and in1 are input while securing a setup time until the complementary clock signal intCLK_c falls, this signal passes through the latch 10 and is supplied to the decoder 12. The decoder 12 performs a decoding process using the setup time. At the rising timing of the clock signal intCLK_t, the latch 10 latches the input signals in0 and in1. The signal inlat <0: 1> latched in the latch 10 is converted into a decode signal dec <0: 3> by the decoder 12, passes through the latch 11 released from the latched state, and is output as an output signal out <0: 3>. Supplied to the next stage. Next, the decode signal dec <0: 3> is latched by the latch 11 at the timing when the clock signal intCLKd_t ″ falls. The signal latched by the latch 11 is supplied to the next stage as the output signal out <0: 3>, and the clock signal intCLKd_t ″ whose pulse width is shortened by the pulse width suppression circuit 33 is held for LOW. In this manner, the output signal out <0: 3> is output for a period of 1 tCK (tCK is a clock cycle).

  In the second embodiment, the same effect as that of delaying the latch release timing on the latch 10 side in the first embodiment is realized by advancing the latch setting timing on the latch 11 side. In other words, by advancing the latch timing of the latch 11 by the pulse width suppression circuit 33, correct signal transfer can be performed as shown in FIG.

  As described above, in the present invention, since the decoder is arranged between the two latches constituting the edge trigger circuit and the decoding process is executed using the setup time, the time delay due to the decoder process can be hidden. In the above configuration, the number of latches in the first stage only needs to be the same as the number of input signals, so that a high-speed latch / decode operation can be realized with a smaller number of circuit elements than in the conventional configuration of FIG. The pulse width suppression circuit 33 need not be provided when the timing margin is sufficient.

  FIG. 9 is a block diagram showing a third embodiment of the latch circuit according to the present invention. In the third embodiment, a pulse width suppression circuit 33 is provided in addition to the configuration of FIG. In FIG. 9, the same components as those in FIGS. 5 and 7 are referred to by the same numerals.

  The configuration of FIG. 9 includes a latch 10, a latch 11, a decoder 12, and a timing delay 32. A decoder 12 is disposed between the latch 10 and the latch 11. The latch 10 is supplied with a clock signal intCLK_c ′ that is a complementary signal of the signal obtained by extending the pulse width of the clock signal intCLK_t by the pulse width extension circuit 31. The clock signal intCLKd_t ″ whose pulse width is shortened by the pulse width suppression circuit 33 is supplied to the latch 11 with respect to the clock signal delayed by the timing delay 32. The input signals in0 and in1 are command signals or address signals for a semiconductor device such as a semiconductor memory device.

  FIG. 10 is a timing waveform diagram showing the operation of the configuration of FIG.

  As shown in FIG. 10, the latch signal inlat <0: 1> latched by the latch 10 is held during the LOW period of the complementary clock signal intCLK_c ′ extended by the pulse width extension circuit 31. The latch signal inlat <0: 1> is latched in the latch 11 as the decode signal dec <0: 3> at the timing of the falling edge of the clock signal intCLKd_t ″ advanced by the pulse width suppression circuit 33.

  In the third embodiment, the latch release timing on the latch 10 side is delayed by the pulse width expansion circuit 31 and at the same time the latch setting timing on the latch 11 side is advanced by the pulse width suppression circuit 33, as shown in FIG. The correct signal transfer is possible. By using both the pulse width expansion circuit 31 and the pulse width suppression circuit 33, reliable data transfer can be realized when sufficient timing cannot be guaranteed with only one of them.

  FIG. 11 is a block diagram showing a fourth embodiment of the latch circuit according to the present invention. In the fourth embodiment, the two latches constituting the edge trigger circuit, that is, the first stage latch that holds the signal transferred during the HIGH period of the clock signal and the signal that is transferred during the HIGH period of the clock signal are LOW. The next-stage latch held for the period is separated, and the long-distance wiring 40 is arranged therebetween. In FIG. 11, the same components as those of FIG. 5 are referred to by the same numerals.

  The configuration of FIG. 11 includes a latch 10, a latch 11, a long distance wiring 40, and a pulse width extension circuit 31. A long distance wiring 40 is disposed between the latch 10 and the latch 11. The input signals in0 and in1 are command signals or address signals for a semiconductor device such as a semiconductor memory device.

  FIG. 12 is a timing waveform diagram showing the operation of the configuration of FIG.

  As shown in FIG. 12, when input signals in0 and in1 are input while securing a setup time until the fall of the complementary clock signal intCLK_c ′, this signal passes through the latch 10 and is supplied to the long distance wiring 40. . The long distance wiring 40 performs signal transfer using this setup time. At the rising timing of the clock signal intCLK_t, the latch 10 latches the input signals in0 and in1. The signal inlat <0: 1> latched in the latch 10 passes through the long distance wiring 40 and the latch 11 released from the latched state, and is supplied to the next stage as the output signal out <0: 1>. Next, the delayed latch signal inlatd <0: 1> transferred by the long-distance wiring 40 is latched in the latch 11 at the timing when the delayed clock signal intCLKd_t ′ falls. The signal latched by the latch 11 is supplied to the next stage as the output signal out <0: 1>, and the delayed clock signal intCLKd_t ′ is held for LOW. In this manner, the output signal out <0: 1> is output for a period of 1 tCK (tCK is a clock cycle).

  In the configuration shown in FIG. 11, as in the configuration of FIG. 5, the pulse width extension circuit 31 extends the latch signal holding period of the latch 10 so that correct signal transfer can be performed as shown in FIG. .

  As described above, in the present invention, the long distance wiring is arranged between the two latches constituting the edge trigger circuit, and the signal transfer is executed by using the setup time. Therefore, the time delay due to the signal transfer can be hidden. . Further, since the pulse width extension circuit only extends the pulse width, the latch timing of the first stage latch is basically an edge timing with no timing adjustment, and a timing shift hardly occurs. Note that it is not necessary to provide the pulse width expansion circuit when the timing margin is sufficient.

  As in the second and third embodiments for the decoder, the fourth embodiment for long-distance wiring has a configuration in which a pulse width suppression circuit is provided instead of the pulse width expansion circuit, or a pulse width expansion circuit. The pulse width suppression circuit may be provided.

  FIG. 13 is a diagram illustrating an example of a circuit configuration of the pulse width extension circuit 31.

  The pulse width expansion circuit 31 in FIG. 13 includes inverters 51 to 55 and a NOR circuit 56. When the input clock signal CLK becomes HIGH, the output of the inverter 55 becomes HIGH accordingly. Thereafter, the HIGH level of the input clock signal CLK is delayed by a predetermined delay time in the inverter train of the inverters 51 to 54 and is input to the NOR circuit. In this case, the output of the inverter 55 remains HIGH. Even when the input clock signal CLK becomes LOW, the output of the inverter train of the inverters 51 to 54 is HIGH during a predetermined delay time, so that the output of the inverter 55 remains HIGH. Thereafter, the LOW level of the input clock signal CLK is delayed by a predetermined delay time in the inverter trains of the inverters 51 to 54 and input to the NOR circuit, and the output of the inverter 55 changes to LOW accordingly. Therefore, the pulse width can be expanded by the predetermined delay time.

  FIG. 14 is a diagram illustrating an example of a circuit configuration of the pulse width suppression circuit 33.

  The pulse width suppression circuit 33 in FIG. 13 includes inverters 61 to 66 and a NAND circuit 67. When the input clock signal CLK becomes HIGH, the output of the inverter 66 becomes HIGH accordingly. Thereafter, the HIGH level of the input clock signal CLK is delayed by a predetermined delay time in the inverter train of the inverters 61 to 65, and is input to the NAND circuit as the LOW signal. In response to this, the output of the inverter 66 changes to LOW. Therefore, the pulse width can be reduced to the length of the predetermined delay time.

  FIG. 15 is a block diagram showing a configuration of a semiconductor memory device to which the latch according to the present invention is applied.

  15 includes input buffers 71-1 and 71-2, latches 72-1 and 72-2, long distance wirings 73-1 and 73-2, latches 74-1 and 74-2, and an address controller 75. , Input buffers 76-1 and 76-2, latches 77-1 and 77-2, inverters 78-1 and 78-2, command decoders 79-1 to 79-4, latches 80-1 to 80-4, command controller 81, an input buffer 82, a pulse width expansion circuit 83, a pulse width suppression circuit 84, a column decoder 85, a row decoder 86, and a memory cell array 87.

  When an address signal (2 bits as an example in the figure) is supplied to the input buffers 71-1 and 71-2, the first stage latches 72-1 and 72-2, the long distance wirings 73-1 and 73-2, and the next It is supplied to the address controller 75 via stage latches 74-1 and 74-2. The address controller 75 supplies the column address to the column decoder 85 and supplies the row address to the row decoder 86. The column decoder 85 and the row decoder 86 each decode the corresponding address, and thereby the designated address of the memory cell array 87 is accessed.

  When a command signal (2 bits as an example in the figure) is input to the input buffers 76-1 and 76-2, the first stage latches 77-1 and 77-2, inverters 78-1 and 78-2, command decoder 79- 1 to 79-4 and the latches 80-1 to 80-4 in the next stage are supplied to the command controller 81. The command controller 81 performs access control by controlling the address controller 75 and the like according to the command decoding results by the command decoders 79-1 to 79-4.

  The clock signal is supplied to the input buffer 82, and is supplied from the input buffer 82 to the pulse width extension circuit 83 and the pulse width suppression circuit 84. The pulse width expansion circuit 83 expands the pulse width of the clock signal and supplies it to the first latches 72-1 and 72-2 of the address system and the first latches 77-1 and 77-2 of the command system. The pulse width suppression circuit 84 reduces the pulse width of the clock signal and supplies it to the latches 74-1 and 74-2 at the next stage of the address system and the latches 80-1 to 80-4 at the next stage of the command system.

  In the address system, it is possible to hide the signal transfer time of the long distance wiring by arranging the first latch and the next latch separately at both ends of the long distance wiring necessary for address signal transfer, Latch operation and address signal transfer can be executed at high speed. In the command system, a command decoder is arranged between the latch at the first stage and the latch at the next stage, thereby making it possible to hide the time required for command decoding by the command decoder. It can be executed at high speed.

  FIG. 16 is a diagram showing further details when the latch circuit according to the present invention is used for the long distance wiring of the address signal of the semiconductor memory device.

  16 includes a clock pad 101, a plurality of address pads 102, a clock input buffer (IB) 103, a plurality of address clock buffers (IB) 104, a plurality of timing adjustment circuits 105 for each of a plurality of address signals, The first stage latch 106 for each address signal and the next stage latch 107 for each of a plurality of address signals are included.

  In a normal chip pad arrangement, the clock pad 101 is provided in the center of the chip, and the plurality of address pads 102 are provided in a row in the half on one side of the chip from the center to the end of the chip. In the configuration of FIG. 16, the first-stage latch 106 is provided near the approximate center of the column of the address pads 102 in order to reduce the delay of the clock signal due to the signal wiring. The delay of the clock signal from the clock input buffer 103 to the first-stage latch 106 is tD1 + tD2a + tD2b. Here, tD1 is a delay corresponding to the wiring from the clock pad 101 to the leftmost address pad 102, and tD2a + tD2b is a delay corresponding to the wiring from the leftmost address pad 102 to the central address pad 102. In the middle of the wiring from the leftmost address pad 102 to the central address pad 102, the clock signal wiring is branched, and the clock signal is supplied to the latch 107 at the next stage. The delay of this clock signal supplied to the next stage latch 107 is tD1 + tD2a.

  The delay of the address signal up to the timing adjustment circuit 105 is maximum at the leftmost or rightmost (A) address pad 102 and is tA0. This delay time tA0 is substantially the same as the delay tD2a + tD2b of the clock signal. The timing adjustment circuit 105 is for adjusting the difference in wiring length for each address signal from the address pad 102 to the timing adjustment circuit 105, and introduces a delay from 0 to tA0 according to the wiring length. A delay 0 is set for the address signal of the leftmost or rightmost (A) address pad 102, and a delay tA0 is set for the central address pad 102. As a result, all address signals have a substantially constant delay delay tA0.

  The first stage latch 106 is latched by the clock signal delayed by tD1 + tD2 (tD2 = tD2a + tD2b). Therefore, the delay tA0 of the address signal is absorbed by the delay of the clock signal when the latch 106 of the first stage latches.

  FIG. 17 is a diagram showing the operation timing of the configuration of FIG.

  As shown in FIG. 17, the address signal supplied to the point A in FIG. 16 is input with a margin for the setup time tIS with respect to the rising edge of the clock signal CLK. This address signal is delayed by tA0 + tA2 (≈tD2 + tA2) due to the wiring delay, and reaches point B in FIG. 16 (B in FIG. 17). The first-stage latch 106 existing on the way latches the address signal at the rising edge of the clock signal delayed by tD1 + tD2, and the address signal is maintained at the point B for a little longer than a half cycle of the clock signal.

  The address signal at point B passes through the latch 107 at the next stage at the rising timing of the clock signal CLKD delayed by tD1 + tD2a from the input clock signal CLK, reaches the point C in FIG. 16, and then rises in the clock signal CLKD. At the falling timing, it is latched by the latch 107 of the next stage (C in FIG. 17). The signal at the point C which is the output of the latch 107 is delayed by the subsequent wiring delay tA3 + tA4 and reaches the point D in FIG. 16 (D in FIG. 17). Therefore, the total signal delay from point A to point D is tD1 + tD2a + tA3 + tA4.

  In this way, in the configuration of FIG. 16, high-speed signal transfer can be realized by hiding the wiring delay between the first-stage latch and the next-stage latch.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows the structure of the conventional command (or address) input circuit and decoder. FIG. 2 is a timing chart showing the operation of the configuration of FIG. 1. It is a figure which shows the structure of the conventional command (or address) input circuit and decoder which implement | achieve speed-up using setup time. FIG. 4 is a timing chart showing the operation of the configuration of FIG. 3. 1 is a configuration diagram illustrating a first embodiment of a latch circuit according to the present invention. FIG. 6 is a timing waveform diagram showing an operation of the configuration of FIG. 5. It is a block diagram which shows 2nd Example of the latch circuit by this invention. FIG. 8 is a timing waveform diagram showing the operation of the configuration of FIG. 7. FIG. 6 is a block diagram showing a third embodiment of the latch circuit according to the present invention. FIG. 10 is a timing waveform diagram showing an operation of the configuration of FIG. 9. It is a block diagram which shows 4th Example of the latch circuit by this invention. FIG. 12 is a timing waveform diagram showing an operation of the configuration of FIG. 11. It is a figure which shows an example of the circuit structure of a pulse width expansion circuit. It is a figure which shows an example of the circuit structure of a pulse width suppression circuit. 1 is a configuration diagram showing a configuration of a semiconductor memory device to which a latch according to the present invention is applied. It is a figure which shows the detail at the time of using the latch circuit by this invention for the long distance wiring of the address signal of a semiconductor memory device. It is a figure which shows the operation | movement timing of the structure of FIG.

Explanation of symbols

10 Latch 11 Latch 12 Decoder 31 Pulse width expansion circuit 32 Timing delay 33 Pulse width suppression circuit 40 Long distance wiring

Claims (14)

A first latch that receives the input signal and retains the input signal for a half cycle period of the first clock signal;
A delay element connected to the output of the first latch;
A second latch connected to the output of the delay element and holding a signal supplied from the delay element for a half cycle period of a second clock signal;
The signal latched by the first latch during the half cycle period of the first clock signal is latched into the second latch via the delay element during the half cycle period of the second clock signal. A circuit for adjusting the timing of at least one of the first clock signal and the second clock signal,
The first latch and the second latch are constituted by a transfer gate and a third latch having two inverters. The semiconductor device according to claim 1, wherein the delay element is a decoder. The semiconductor device according to claim 1, wherein the transfer gate supplies an input signal to the third latch based on a clock signal. The semiconductor device according to claim 1, wherein the transfer gate is a gated clock. 5. The semiconductor device according to claim 1, wherein the circuit is a circuit that extends the half cycle of the first clock signal. 6. The semiconductor device according to claim 1, wherein the circuit is a circuit that shortens the half cycle of the second clock signal. 7. The circuit according to claim 1, wherein the circuit extends the half cycle of the first clock signal and shortens the half cycle of the second clock signal. 8. A semiconductor device according to 1. A first latch that receives the command signal and holds the command signal for a half cycle period of the first clock signal;
A command decoder connected to the output of the first latch;
A second latch connected to the output of the command decoder and holding a decode signal supplied from the command decoder for a half cycle period of a second clock signal;
A controller that performs access control based on the decode signal supplied from the second latch,
The semiconductor device, wherein the first latch and the second latch include a transfer gate and a third latch having two inverters. 9. The semiconductor device according to claim 8, wherein the transfer gate supplies an input signal to the third latch based on a clock signal. The semiconductor device according to claim 8, wherein the transfer gate is a gated clock. A first latch that receives the address signal and retains the address signal for a half cycle period of the first clock signal;
A delay element for transferring an address signal having one end connected to the output of the first latch;
A second latch connected to the other end of the delay element and holding an address signal supplied from the delay element for a half cycle period of a second clock signal;
The first latch and the second latch are constituted by a transfer gate and a third latch having two inverters. The semiconductor device according to claim 11, wherein the semiconductor device includes an address decoder that decodes an address signal. The semiconductor device according to claim 11, wherein the transfer gate supplies an input signal to the third latch based on a clock signal. The semiconductor device according to claim 11, wherein the transfer gate is a gated clock.

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