JP2003007069A - Semiconductor memory and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory and a semiconductor integrated circuit device in which a data input/output cycle can be varied quickly. SOLUTION: In this semiconductor memory, an internal clock synchronizing with a non-continuous external toggle signal PCLKINTCLK inputted with data read request is generated by an incorporated clock generating circuit. Data output processing and data output in the inside are performed synchronizing with the internal clock INTCLK. A data strobe signal STB indicating a data output cycle is outputted with data output. A cycle of the data strobe signal STB is same as a cycle of the internal clock INTCLK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device mounted in a system composed of a plurality of devices.

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory device having a high-speed interface function has been constructed as a synchronous semiconductor memory device which executes data input / output in synchronization with an external clock. For example, if such a synchronous semiconductor memory device is installed in a system composed of a plurality of devices that operate based on a common external clock, high-speed data input / output can be performed at the timing synchronized with the external clock. can do.

FIG. 13 is a timing chart for explaining the data input / output timing in the conventional synchronous semiconductor memory device.

Referring to FIG. 13, external clock EXTC
LK is a clock supplied in the system in which the synchronous semiconductor memory device is mounted. External clock EXTCL
K repeats high level (hereinafter also referred to as H level) and low level (hereinafter also simply referred to as L level) in a constant cycle.

A data output instruction to the synchronous semiconductor memory device is given as a read command READ at a timing synchronized with the external clock EXTCLK.

Inside the synchronous semiconductor memory device, a DLL (Delay Locked Loop) or a PLL (Phase) for generating an internal clock synchronized with the external clock EXTCLK.
Locked Loop) is included in the internal clock generation circuit. The clock generation circuit constantly monitors the external clock EXTCLK, which is a free-run signal, and generates an internal clock synchronized with the external clock.

In response to the input of the read command READ, a predetermined data output process is executed in synchronization with this internal clock in the synchronous semiconductor memory device. After a predetermined latency (two clock cycles in FIG. 13) has elapsed, output of data DAT is started in a cycle synchronized with external clock EXTCLK. In FIG. 13, data output is executed in synchronization with both the rising edge and the falling edge of the external clock EXTCLK.
The operation of the synchronous semiconductor memory device that executes a so-called DDR (Double Data Rate) operation is shown.

A data strobe signal STB is output in synchronization with the data DAT as a signal for indicating the data output period from the synchronous semiconductor memory device to other devices in the same system. The data strobe signal STB is
It has the same cycle in synchronization with the external clock EXTCLK.

Although not shown, the external clock E is similarly applied to the data input processing in the synchronous semiconductor memory device.
It is executed at a timing based on an internal clock synchronized with XTCLK. As a result, the synchronous semiconductor memory device
Data input / output can be executed in a cycle synchronized with the external clock EXTCLK.

[0010]

However, the data input / output in the conventional synchronous semiconductor memory device can be executed only in exactly the same cycle as the cycle of the external clock in the free-run state. Therefore, when it is desired to change the data input / output cycle in order to obtain an appropriate data transfer timing in consideration of the operation efficiency of the entire system, it is necessary to change the frequency of the external clock shared by the entire system.

That is, a semiconductor integrated circuit device mounted in a system, represented by a synchronous semiconductor memory device, is
When it is necessary to operate at a higher speed or operate at a lower speed from the state of operating at a certain constant speed, after changing the frequency of the common external clock once, the system It was not possible to change the operating speed until each of the devices that compose the device can operate stably based on the changed external clock. As a result, there is a problem in that it is difficult to quickly change the data input / output cycle of each semiconductor integrated circuit device configuring the system in consideration of the operation efficiency of the entire system.

The present invention has been made in order to solve such a problem, and an object of the present invention is to speed up the data input / output cycle regardless of the external clock shared by the entire system. A semiconductor memory device and a semiconductor integrated circuit device that can change are provided.

[0013]

According to another aspect of the present invention, there is provided a semiconductor memory device mounted in a system including a plurality of devices sharing an external clock signal, wherein a data output cycle is designated. Including a pulse to
A clock generation circuit that receives a discontinuous period control signal different from the external clock signal and generates an internal clock having a period based on a pulse, and in synchronization with the internal clock,
And an internal circuit that executes a data output process.

A semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the internal circuit uses a data strobe signal for indicating a data output period from the semiconductor memory device as an internal clock signal. The data strobe signal is output to the outside.

A semiconductor memory device according to a third aspect of the present invention is a semiconductor memory device mounted in a system composed of a plurality of devices that share an external clock signal, and includes a pulse for instructing a data input cycle. A clock generation circuit that receives a cycle control signal different from the external clock signal and generates an internal clock having a cycle based on a pulse, and an internal circuit that performs a data input process in synchronization with the internal clock.

A semiconductor memory device according to a fourth aspect is the semiconductor memory device according to the third aspect, wherein the internal circuit includes first and second input buffers for receiving input data of a plurality of bits, and a first input buffer. Alternatively, the first to n-th (n:
Natural number) n pipeline processing units.
The first and second input buffers operate complementarily at the timing in response to the cycle control signal, and each of the n pipeline processing units executes a predetermined operation at the timing based on the internal clock.

A semiconductor memory device according to a fifth aspect is the semiconductor memory device according to the fourth aspect, in which the clock generation circuit delays the internal clock by a predetermined time and obtains the 1st to n-th One sub clock and the first to nth second sub clocks obtained by delaying the inversion clock of the internal clock by a predetermined time are further generated to generate the ith (i: natural number of 1 to n). The pipeline processing unit operates in response to the i-th first and second sub-clocks, and the predetermined time is set to be smaller than 1/2 of the minimum period of the internal clock.

A semiconductor memory device according to a sixth aspect is the semiconductor memory device according to the first or third aspect, wherein the clock generation circuit delays the cycle control signal stepwise by a first delay time, A first delay unit that outputs a plurality of delayed signals, a phase comparison unit that compares the phases of each of the plurality of delayed signals with the period control signal, and a pulse pulse based on the comparison result in the phase comparison unit. A determination unit for detecting the width, a selector that receives the cycle control signal and the internal clock signal, outputs the internal clock signal after the generation of the internal clock signal, and outputs the cycle control signal in other periods. A second delay unit that delays the output of the selector by a second delay time corresponding to the pulse width and generates an internal clock in response to an instruction from the determination unit.

A semiconductor memory device according to a seventh aspect is the semiconductor memory device according to the sixth aspect, wherein the cycle control signal is 2
The phase comparison unit includes one or more pulses, and compares the rising edges or the falling edges of each delay signal and the cycle control signal.

A semiconductor memory device according to claim 8 is the semiconductor memory device according to claim 6, wherein the cycle control signal is 1
The phase comparator includes one or more pulses and compares the rising edge and the falling edge of each delay signal and the cycle control signal.

A semiconductor integrated circuit device according to a ninth aspect is a semiconductor integrated circuit device which is mounted in a system composed of a plurality of devices sharing a clock signal, and among the plurality of devices when outputting data. Receiving a non-continuous first cycle control signal different from the clock signal, which is input together with a data output request from another one of the two, and generates an internal clock having a cycle based on the first cycle control signal signal. And a clock generation circuit for performing data output processing in synchronization with the internal clock when outputting data. The internal circuit outputs the requested data according to the cycle of the internal clock and also outputs the data strobe signal for indicating the data output cycle.

According to a tenth aspect of the semiconductor integrated circuit device,
10. The semiconductor integrated circuit device according to claim 9, wherein the clock generation circuit is input with a data input request from another one of the plurality of devices at the time of data input.
Upon receiving a discontinuous second cycle control signal different from the clock signal, an internal clock having a cycle based on the second cycle control signal signal is generated, and the internal circuit synchronizes with the internal clock during data output. Then, the data input process is executed.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. In the following, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a schematic block diagram showing an overall structure of a synchronous semiconductor memory device 1 shown as a representative example of a semiconductor integrated circuit device according to a first embodiment of the present invention. In the first embodiment, the data output operation of synchronous semiconductor memory device 1 will be mainly described.

Referring to FIG. 1, a synchronous semiconductor memory device 1
Is a memory array 10 having a plurality of memory cells arranged in a matrix, an address terminal 12, a command control signal terminal 14, a clock terminal 16, and a data terminal 18.
And a data strobe signal terminal 19.

Address terminal 12 receives bank address BA and address signals A0-An for executing memory cell selection in memory array 10. The command control signal terminal 14 receives command control signals such as a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE and a data mask signal DQM. An operation instruction, that is, a command input to the synchronous semiconductor memory device 1 is executed by a combination of signal levels of command control signals.

Clock terminal 16 receives clock enable signal CKE and external toggle signal PCLK. The external toggle signal PCLK is externally input at the time of data output in order to instruct a data output cycle from the synchronous semiconductor memory device 1. The data terminal 18 exchanges data DAT with the outside. In this embodiment, 8-bit data D1 to D8 are input / output in one data output operation and one data input operation.

The data strobe signal terminal 19 inputs / outputs the data strobe signal STB for indicating the data input / output cycle of the synchronous semiconductor memory device 1. At the time of data input, data strobe signal STB is externally applied together with the input data. The synchronous semiconductor memory device 1 executes the data input process at the cycle designated by the data strobe signal STB. On the other hand, at the time of data output, the data strobe signal STB synchronized with the data output period from the synchronous semiconductor memory device 1 is internally generated and output from the data strobe signal terminal 19 as the data strobe signal STB.

Synchronous semiconductor memory device 1 further includes address buffer 22, control signal input buffer 24, control circuit and mode register 30, row decoder and word driver 40, column decoder 45, and sense amplifier 50. Equipped with.

The address buffer 22 has an address terminal 1
2 receives the bank address BA and the address signals A0 to An input to the row address XA and the column address YA.
Produces and. The row address XA and the column address YA are
Row decoder and word driver 40, and column decoder 4
5 and 5, respectively.

The control signal input buffer 24 receives the command control signal input to the command control signal terminal 14 and transfers it to the control circuit and the mode register 30. The control circuit and mode register 30 are
In response to a combination of command control signals from the outside received through control signal input buffer 24, synchronous semiconductor memory device 1 generates a control signal group for executing a specified command.

Synchronous semiconductor memory device 1 further includes an internal clock generation circuit 100 for generating internal clock INTCLK. Internal clock generation circuit 100
Generates an internal clock INTCLK having a cycle based on the external toggle signal PLCK input to the clock terminal 16 when outputting data. Further, at the time of data input, the internal clock INTCLK having a cycle based on the data strobe signal STB input to the data strobe signal terminal 19 is generated. The configuration and operation of the internal clock generation circuit 100 will be described later in detail.

Internal clock INTCLK is transmitted to control circuit and mode register 30, address buffer 22 and control signal input buffer 24. Therefore, the data input / output processing from the synchronous semiconductor memory device 1 can be executed in synchronization with the internal clock INTCLK.

Of the data input / output processing, the processing other than data transmission / reception with the outside is performed by the internal clock INTC.
It does not need to be executed in synchronization with LK. These processing timings are controlled by the control circuit and mode register 30.
Can be arbitrarily specified by.

The row decoder and word driver 40
Row selection in the memory array 10 is executed according to the row address XA. Specifically, it controls the selective activation of word lines (not shown) arranged for each memory cell row in memory array 10.

The column decoder 45 executes column selection in the memory array 10 according to the column address YA. Specifically, a plurality of bit lines (not shown) arranged for each memory cell column in memory array 10 are selectively coupled to sense amplifier 50.

The sense amplifier 50 is coupled to the bit line corresponding to the column selection result and amplifies the voltage of the selected bit line.

The synchronous semiconductor memory device 1 further includes a preamplifier / write driver 60 and an input buffer 70.
, Output buffer 75, multiplexer 80, Vr
ef generating circuit 85.

At the time of data output, preamplifier and write driver 60 amplifies and outputs 8-bit read data read from memory array 10 through sense amplifier 50.

The preamplifier and write driver 60 are
At the time of data input, externally input data (8 bits) is driven to a plurality of bit lines coupled to a memory cell to be a data write target. Multiplexer 8
0 sequentially transmits one bit of the eight read data read in parallel from the preamplifier and write driver 60 to the output buffer 75.

The output buffer 75 is a multiplexer 80.
The read data selectively transmitted from the data terminal 18
To the outside via. Further, at the time of data output, the data strobe signal STB generated based on the internal clock INTCLK, that is, synchronized with the internal clock INTCLK, is the data strobe signal terminal 1.
It is output from 9.

At the time of data output, the input buffer 7
0 receives the data DAT (D1 to D8) input to the data terminal 18 based on the reference voltage Vr. Vref
Generation circuit 85 generates reference voltage Vr for determining whether the data input to data terminal 18 is at H level or L level. At the time of data input, the data strobe signal STB is externally input to the data strobe signal terminal 19. Further, the data strobe signal STB is the internal clock INTCL.
It is also transmitted to the internal clock generation circuit 100 to generate K.

The operations of input buffer 70, output buffer 75 and multiplexer 80 are also executed in synchronization with internal clock INTCLK or data strobe signal STB.

FIG. 2 is a block diagram showing the structure of the internal clock generation circuit 100. Referring to FIG. 2, the internal clock generation circuit 100 includes a delay unit 110 and a phase comparison unit 1.
20, a determination unit 130, a selector 135, and a delay unit 1
40 and.

The delay section 110 has m (m: natural number) delay units 112 connected in series. Each of the delay units 112 gives a constant delay time ΔT to the input signal. When outputting data, the external toggle signal PLCK corresponding to the cycle control signal is input to the first-stage delay unit. A plurality of delay units 11
Taps for extracting the external toggle signal delayed stepwise by 2 are arranged corresponding to the nodes Na1 to Nam, respectively. As a result, the delay unit 110 causes the external toggle signals PCLKd1 to PC delayed by ΔT in m steps.
Output LKdm.

The phase comparison section 120 includes m comparison units 125-1 to 12-12 provided corresponding to the m delayed external toggle signals PCLKd1 to PCLKdm, respectively.
Have 5-m. Comparison unit 125-1 to 125-m
Each of the delayed external toggle signals PCLKd1-PCLKd.
Corresponding one of CLKdm and external toggle signal PC
Compare the phase with LK.

The judging section 130 is a comparison unit 125-1.
In response to the phase comparison result in each of .about.125-m, the switching point of the phase comparison result is detected.

FIG. 3 is a conceptual diagram for explaining the operation of internal clock generation circuit 100. Referring to FIG. 3, in the first embodiment of the present invention, external toggle signal PCL is used.
Let K have at least two pulses to indicate the data output period. External toggle signal PCLK
The pulse width of is equivalent to the data output cycle.

The delay unit 110 delays the first rising edge of the external toggle signal PCLK stepwise, and the phase comparing section 120 delays the next rising edge of the external toggle signal and the stepwise delayed external toggle signal PCLKd1. It is possible to detect the cycle Tc of the external toggle signal PCLK by comparing the phase with ~ PCLKdm. That is, the product of the number N of delay units (N: a natural number of 1 to m) included up to the node corresponding to the switching point of the phase comparison result and the delay time ΔT by the delay unit 112 is the external toggle signal PCLK. Corresponds to the cycle Tc of.

Referring again to FIG. 2, the selector 135
Receiving internal clock INTCLK output from delay unit 140 to node Nc and toggle signal PCLK, one of them according to selection control signal SL is transmitted to delay unit 140.
Specifically, in the period until the internal clock INTCLK is generated at the node Nc, the selector 135 outputs the external toggle signal PCLK. On the contrary, the node Nc
In the period after the internal clock INTCLK is generated, the selector 135 outputs the internal clock INTCLK.

The delay section 140 has m delay units 142 connected in series. The output of the selector 135 is input to the first-stage delay unit. Each of the delay units 142 has a delay time ΔT of the delay unit 112.
It has the same delay time as. As a result, the m delay units 142 are included in the selector 1 delayed stepwise by ΔT.
The outputs of 35 are output. Internal clock INTC
Switches S1 to Sm are respectively arranged between the node Nc where LK is generated and the output nodes of the m delay units.

One of the switches S1 to Sm corresponding to the switching point of the phase comparison result in the phase comparison section 120.
One is designated by the determination unit 130 and selectively turned on. As a result, the signal output from the selector 135 is delayed by the delay unit 140 by the cycle Tc of the external toggle signal PCLK detected by the delay unit 110 and output to the node Nc.

The selector 135 outputs the external toggle signal PCLK.
Is output, the external toggle signal PCLK is set to T
By delaying by c, the internal clock INTCLK is generated. Once internal clock INTCLK is generated, selector 135 and delay unit 140 form a self-oscillation loop corresponding to cycle Tc of external toggle signal PCLK, and internal clock INTCLK is continuously generated.

Referring again to FIG. 3, the internal clock INT
CLK is generated as a signal having the same cycle as cycle Tc detected based on at least two rising edges of external toggle signal PCLK. That is, when the duty ratio of the external toggle signal PCLK and the internal clock INTCLK is set to 50%, the internal clock INT
The pulse width Th of the CLK becomes equal to the pulse width of the toggle signal PCLK.

FIG. 4 is a block diagram showing a structure of internal clock generating circuit 101 according to another example of the structure.

Referring to FIG. 4, internal clock generation circuit 101 according to another configuration example is different from internal clock generation circuit 100 shown in FIG. 2 in that inverter 150 is further included. The inverter 150 inverts the external toggle signal PCLK and transmits it to the phase comparator 120. That is, in the internal clock generation circuit 101, the inverted external toggle signal PCLK and the delayed external toggle signal PCL
A phase comparison is performed with each of Kd1-PCLKdm.

Therefore, the comparison units 125-1 to 125-1
25-m delays the first rising edge of the external toggle signal PCLK stepwise by the delay section 110, and delays it stepwise by the phase comparing section 120 with the first falling edge of the external toggle signal PCLK. The pulse width Th of the external toggle signal PCLK can be detected by comparing the phases with the external toggle signals PCLKd1 to PCLKdm.

Each of delay units 142 has a delay time 2 · ΔT that is twice the delay time ΔT of delay unit 112. As a result, in the internal clock generation circuit 101, the m delay units 142 each output the output of the selector 135 delayed stepwise by 2 · ΔT. Therefore, by selectively turning on one of the switches S1 to Sm corresponding to the switching point of the phase comparison result in the phase comparison unit 120, the selector 13
The signal output from 5 is delayed by the delay unit 140 by twice the pulse width Th of the external toggle signal PCLK, that is, the period Tc of the external toggle signal PCLK, and the node N
It is output to c.

Since the operation of selector 135 is similar to that of internal clock generation circuit 100, detailed description will not be repeated.

With such a configuration, as shown in FIG. 5, if the external toggle signal PCLK includes at least one pulse, the pulse width Th of the external toggle signal PCLK can be detected. Further, the internal clock INTCLK is continuously generated at a constant cycle Tc based on the pulse width Th of the pulse included in the external toggle signal PCLK.

The internal clock INT generated in this way
The data output operation inside the synchronous semiconductor memory device 1 is sequentially executed in synchronization with CLK.

FIG. 6 is a timing chart for explaining the data output operation of synchronous semiconductor memory device 1.

Referring to FIG. 6, external toggle signal PCLK
A data output process is executed in response to a data output request given together with the read command READ. Specifically, 8 read from the memory array 10
Bit read data is output in parallel from the preamplifier and write driver 60 via the sense amplifier 50. The data reading process from the memory array 10 does not need to be executed at the timing synchronized with the internal clock INTCLK, and can be executed at any timing.

The 8-bit read data is sequentially selected by the multiplexer 80 bit by bit and transmitted to the output buffer 75. The output buffer 75 operates in response to the internal clock INTCLK, and sequentially outputs each of the output data D1 to D8 transmitted from the multiplexer 80 from the data terminal 18.

Alternatively, the 8-bit read data may be sequentially output by pipeline processing based on the internal clock. In this case, it is necessary to provide registers corresponding to the required number of bits in the multiplexer 80 part. The internal clock I used from the internal clock generation circuit 100 is the internal clock I
A clock different from NTCLK may be used.

Further, the output buffer 75 uses, for example, the internal clock INTCLK based on the internal clock INTCLK.
After buffering CLK, the data strobe signal terminal 19 outputs the data strobe signal STB to the outside.

As described above, with the structure according to the first embodiment, data output can be executed based on the data output cycle instructed by the external toggle signal input together with the data output request. This external toggle signal is a non-continuous signal that can be set independently of the external clock in the free-run state and can indicate a desired cycle.
Therefore, in the system including the synchronous semiconductor memory device 1, the data output cycle (frequency) can be flexibly changed in order to execute the data transfer with the optimum efficiency.

[Second Embodiment] In the second embodiment, a data input operation in synchronous semiconductor memory device 1 shown in FIG. 1 will be described. In the present embodiment, the data input operation in synchronous semiconductor memory device 1 is executed based on pipeline processing.

FIG. 7 is a conceptual diagram illustrating a data input process in synchronous semiconductor memory device 1 according to the second embodiment.

Referring to FIG. 7, input buffer 70 includes an odd buffer 76 for receiving odd bits of a plurality of bits of input data continuously input to data terminal 18,
And an even buffer 77 for receiving even bits. The odd-numbered buffer 76 has a data strobe signal STB.
It operates in response to the rising edge of and takes in the input data to the data terminal 18. The even-numbered buffer 77 operates based on the inverted signal of the data strobe signal STB, that is, complementary to the odd-numbered buffer 76, and takes in the input data to the data terminal 18.

The input data fetched by the input buffer is stepwise processed by each of pipeline processing units 90 to 92 and written to memory array 10.

Pipeline processing unit 9 in FIG.
The processes by 0 to 92 collectively indicate a series of data input processes executed by the row decoder and word driver 40, the column decoder 45, the sense amplifier 50, the preamplifier and the write driver 60, and the like. In the pipeline processing unit 92 at the final stage, it is assumed that the write operation for the selected memory cell is executed.

Although FIG. 7 shows an example in which the data input processing is divided into three stages and executed by the pipeline processing units 90 to 92, the data input processing may be performed at any arbitrary plurality of stages. It can be divided and executed.

Odd buffer 76 or even buffer 7
The input data captured by 7 is processed by each of the pipeline processing units 90 to 92 as pipeline processing 1 (also simply referred to as “processing 1”), pipeline processing 2 (also simply referred to as “processing 2”), and memory. The write operation to the cell is executed stepwise and transmitted to the selected memory cell.

Pipeline processing units 90, 91 and 92 operate in response to each of the rising edges of internal clock INTCLK and its inverted clock. Alternatively, it may be operated in response to each of the falling edges of internal clock INTCLK and its inverted clock.

FIG. 8 is a timing chart for explaining the progress of the data input process according to the second embodiment.

Referring to FIG. 8, in response to the rising edge of data strobe signal STB at time T0, 1
The th input data D1 is taken in by the odd buffer 76. At time T1 corresponding to the falling edge of the data strobe signal STB, that is, the rising edge of the inverted data strobe signal STB, the second input data D2 input to the data terminal 18 is taken in by the even buffer 77. In parallel, “processing 1” for the input data D1 is executed by the pipeline processing unit 90.

Based on the data strobe signal STB,
When the generation of the internal clock INTCLK is started, in response to the next rising edge of the internal clock INTCLK at time T2, the third input data D3 is taken in by the odd number buffer 76 in parallel with the first input data D3. Of the input data D1 is processed by the pipeline processing unit 91 (process 2), and the second input data is processed by the pipeline processing unit 90 (process 1).

Thereafter, at each of the rising edge and the falling edge of the data strobe signal STB, the input data is sequentially fetched bit by bit by the odd buffer 76 or the even buffer 77, and the fetched input data is pipelined. Processing units 90, 91
And 92, the data is processed stepwise in response to the internal clock INTCLK synchronized with the data strobe signal STB and written in the memory cell.

As described above, a plurality of bits of input data which are sequentially input are selectively taken in by the odd buffer 76 and the even buffer 77 which operate complementarily in response to the internal clock INTCLK, and each of the input data is input. Pipeline processing units 90, 91 for bits
And 92, it is possible to sequentially perform the data input processing without providing an overlapping processing period.

Therefore, a plurality of bits of input data can be processed efficiently and at high speed by using a circuit group for executing the data input process for 1-bit input data.

FIG. 9 is a timing chart illustrating the data input operation according to the second embodiment.

Referring to FIG. 9, when data is input, data strobe signal STB input to data strobe signal terminal 19 corresponds to the cycle control signal. Therefore, at the time of data input, the data strobe signal ST
Based on B, the internal clock INTCLK is generated. At the time of data input, the data strobe signal S
TB is input to the internal clock generation circuit 100 or 101 instead of the external toggle signal PCLK described in FIG. As a result, the data strobe signal STB can specify the data input cycle in the synchronous semiconductor memory device 1 by including two or one or more pulses for specifying the data input cycle.

Inside the synchronous semiconductor memory device 1,
As described with reference to FIGS. 7 and 8, the internal clock INT
Data input processing is executed based on a pipeline operation in synchronization with CLK. As a result, the input data DAT (D1 to D8) to the data terminal 18 can be subjected to the data input processing in accordance with the data input cycle designated by the data strobe signal STB.

In the example of FIG. 9, the data strobe signal STB for inputting 8-bit data is
Although an example including four pulses is shown, as described in the first embodiment, if the data strobe signal STB has one or more or two or more pulses, it corresponds to the pulse width. The internal clock can be generated inside the synchronous semiconductor memory device 1.

[Third Embodiment] In the second embodiment, data input is executed in the data input period designated by the data strobe signal STB, and the efficient data input is internally performed based on the pipeline operation. The configuration capable of executing the processing has been described. However, according to the configuration according to the second embodiment,
The data input processing time inside the synchronous semiconductor memory device 1 will vary depending on the data input cycle requested from the outside, that is, the pulse width of the data strobe signal STB. In the third embodiment, a configuration will be described in which data input from the outside is accepted based on a data input cycle requested from the outside, and the data input processing time inside is constant.

Referring to FIG. 10, in the structure according to the third embodiment, internal clock generation circuit 100 includes delay circuits 160 to 162 for delaying internal clock INTCLK in addition to the structure shown in FIG. , And delay circuits 165 to 167 for delaying the inverted clock of the internal clock INTCLK.

Delay circuits 160 to 162 delay internal clock INTCLK stepwise by ΔTc to generate sub clocks SC1 to SC3, respectively. That is,
The sub clock SC1 output from the delay circuit 160 is delayed by ΔTc from the internal clock INTCLK. Similarly, the sub clock S generated by the delay circuit 161.
C2 is delayed by ΔTc from the sub clock SC1. The sub clock SC3 generated by the delay circuit 162 is
It is delayed by ΔTc from the subclock SC2.

Similarly, the delay circuits 165 to 167 delay the inverted clock in steps of ΔTc to generate sub clocks ISC1 to ISC3, respectively. That is,
The sub clock ISC1 output by the delay circuit 165 is delayed by ΔTc from the inverted clock of the internal clock INTCLK. Similarly, the sub clock ISC2 generated by the delay circuit 166 is delayed from the sub clock ISC1 by ΔTc. The sub clock ISC3 generated by the delay circuit 167 is ΔTc more than the sub clock ISC2.
It has been delayed.

Pipeline processing unit 90 operates in response to each rising edge of subclocks SC1 and ISC1. Similarly, pipeline processing unit 91 operates in response to each rising edge of subclocks SC2 and ISC2, and pipeline processing unit 92 operates in response to each rising edge of subclocks SC3 and ISC3. .

FIG. 11 is a timing chart for explaining the progress of the data input process according to the third embodiment.

Referring to FIG. 11, in response to the rising edge of data strobe signal STB at time T0,
The first input data D1 is captured by the odd buffer 76.

Delay circuits 160-162 and 165-1
The delay time ΔTc in each of 67 is a half cycle (Tc / Tc) of the internal clock INTCLK in consideration of the processing time required in each pipeline processing unit 90, 91, 92.
It is set to be shorter than 2). The internal clock INTCLK changes its cycle according to the data input cycle requested from the outside, but the delay time ΔTc is
For example, it is determined in consideration of the minimum cycle assumed in the specifications.

Therefore, time ta prior to time t1 corresponding to the falling edge of internal clock INTCLK.
At, since the sub clock SC1 rises, the pipeline processing unit 90 executes "processing 1" on the first input data D1. After that, time t
At times tb and tc when a predetermined delay time ΔTc has elapsed from a, “processing 2” by the pipeline processing unit 91 and “memory cell writing” by the pipeline processing unit 92 are executed.

On the other hand, at time T1 which is later than time ta and earlier than time tb, the even-numbered buffer 77 responds to the rising edge of the inverted signal of the data strobe signal STB.
Thus, the second input data D2 is captured. After that, at a time td, te, and tf when a predetermined delay time ΔTc has elapsed from the time T1, the “processing 1” by the pipeline processing unit 90 and the “processing 2” by the pipeline processing unit 91 are performed on the second input data D2. , And the “memory cell write” by the pipeline processing unit 92, respectively.

The subsequent input data D3, ... Are also taken in by the odd number buffer 76 and the even number buffer 77 at the timing in response to the data strobe signal STB, and the data input by the pipeline processing at the same timing as the input data D1 and D2. The process is executed.

As described above, according to the configuration according to the third embodiment, as in the second embodiment, the data input process based on the pipeline process is executed in accordance with the data input cycle requested from the outside, and the data input process is performed. The required time can be maintained constant regardless of the data input cycle required from the outside.

[Fourth Embodiment] In the fourth embodiment, a system constituted by using the semiconductor integrated circuit device according to the present invention represented by the synchronous semiconductor memory device described in the first to third embodiments will be described. The configuration will be described.

FIG. 12 is a schematic block diagram showing a structure of a system 300 including a semiconductor integrated circuit device according to the present invention.

Referring to FIG. 12, system 300 according to the fourth embodiment includes semiconductor integrated circuit devices 200 and 21.
Equipped with 0. For example, synchronous semiconductor memory device 1 described in the first to third embodiments can be applied to each of semiconductor integrated circuit devices 200 and 210. Further, the invention is not limited to the synchronous semiconductor memory device, and can be similarly applied to a circuit device such as a memory controller, a microcomputer, a chip set, a graphic chip, and a CPU (Central Processing Unit).

Semiconductor integrated circuit devices 200 and 210
Is the internal clock generation circuit 10 described in the first embodiment.
Built-in 0 (or 101).

In system 300, common external clock EXTCLK is provided, and semiconductor integrated circuit device 2
00 and 210 can also operate in synchronization with the external clock EXTCLK.

Data transfer between the semiconductor integrated circuit devices 200 and 210 constituting the system 300 is performed by the external toggle signal PCLK and the data strobe signal ST.
It is executed based on the data input period and the data output period designated by B, respectively.

For example, when the semiconductor integrated circuit device 210 requests the semiconductor integrated circuit device 200 for data output, the toggle signal PCLKb for instructing the data output cycle is output together with the data output request. The semiconductor integrated circuit device 200 executes data output processing based on the internal clock INTCLKa generated by the internal clock generation circuit 100 (or 101) based on the toggle signal PCLKb. The semiconductor integrated circuit device 200 is
In accordance with the data output cycle designated by the toggle signal PCLKb, n-bit (n: a natural number of 2 or more) data DAT is output. Further, together with the data DAT, the data strobe signal STBa having the same cycle as the internal clock INTCLKa is output.

In semiconductor integrated circuit device 210 which receives data from semiconductor integrated circuit device 200, internal clock INTC synchronized with data strobe signal STBa is used.
LKb is generated by the internal clock and the internal clock INTC is generated.
Input processing of n-bit data DAT is executed in synchronization with LKb. As a result, the data DAT transferred from the semiconductor integrated circuit device 200 is transferred to the data strobe signal ST.
It can be received in synchronization with Ba.

Even when system 300 is composed of three or more semiconductor integrated circuit devices, similar data transfer can be performed by setting a toggle signal and a data strobe signal for each semiconductor integrated circuit device. You can

As described above, in the system configured using the semiconductor integrated circuit device according to the device of the present invention,
Since the data transfer between the devices can be changed in consideration of the efficiency of the entire system, it is possible to execute the optimum data transfer for the system.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0109]

In the semiconductor memory device according to the first and second aspects of the present invention, the data output can be executed on the basis of the cycle control signal in a cycle completely independent of the external clock, and therefore, in an appropriate cycle considering the overall efficiency of the system. Data can be transferred.

In the semiconductor memory device according to the third aspect, data input can be executed on the basis of the cycle control signal at a cycle completely independent of the external clock, so that data can be transferred at an appropriate cycle in consideration of the overall efficiency of the system.

In addition to the effect of the semiconductor memory device according to the third aspect, the semiconductor memory device according to the fourth aspect can efficiently execute the data input process of a plurality of bits by the pipeline process.

According to the semiconductor memory device of the fifth aspect, in addition to the effect of the semiconductor memory device of the fourth aspect, the semiconductor memory device does not depend on the data input cycle instructed by the cycle control signal,
The time required for the data input process can be made constant.

According to the semiconductor memory device of the sixth aspect, in addition to the effect of the semiconductor memory device of the first aspect, the frequency corresponding to the pulse width included in the cycle control signal is based on the discontinuous cycle control signal. It is possible to generate an internal clock having

The semiconductor memory device according to the seventh aspect can enjoy the effect of the semiconductor memory device according to the sixth aspect when the cycle control signal includes at least two pulses.

The semiconductor memory device according to claim 8 can enjoy the effect of the semiconductor memory device according to claim 6 when the cycle control signal includes at least one pulse.

According to another aspect of the semiconductor integrated circuit device of the present invention, data input and data output are performed with other devices in the same system at a cycle completely independent of the external clock based on the cycle control signal. Since it can be executed, data can be transferred at an appropriate cycle considering the overall efficiency of the system.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a synchronous semiconductor memory device shown as a representative example of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an internal clock generation circuit shown in FIG.

FIG. 3 is a conceptual diagram for explaining the operation of the internal clock generation circuit shown in FIG.

FIG. 4 is a block diagram showing another configuration example of the internal clock generation circuit shown in FIG.

5 is a conceptual diagram for explaining the operation of the internal clock generation circuit shown in FIG.

6 is a timing chart illustrating a data output operation of the synchronous semiconductor memory device shown in FIG.

FIG. 7 is a conceptual diagram illustrating a data input process according to the second embodiment of the synchronous semiconductor memory device shown in FIG. 1.

FIG. 8 is a timing chart illustrating the progress of the data input process according to the second embodiment.

FIG. 9 is a timing chart illustrating a data input operation according to the second embodiment.

10 is a conceptual diagram illustrating a data input process according to the third embodiment of the synchronous semiconductor memory device shown in FIG.

FIG. 11 is a timing chart illustrating the progress of the data input process according to the third embodiment.

FIG. 12 is a schematic block diagram showing a configuration example of a system configured by the semiconductor integrated circuit device according to the present invention.

FIG. 13 is a timing chart for explaining data input / output timing in the conventional synchronous semiconductor memory device.

[Explanation of symbols]

1 synchronous semiconductor memory device, 10 memory array, 12
Address terminal, 14 command control signal terminal, 16 clock terminal, 18 data terminal, 19 data strobe signal terminal, 30 control circuit and mode register, 40 word driver, 45 column decoder, 50
Sense amplifier, 70 input buffer, 75 output buffer, 76 odd buffer, 77 even buffer, 80
Multiplexer, 90, 91, 92 pipeline processing unit, 100, 101 internal clock generation circuit, 11
0,140 delay unit, 112,142 delay unit,
120 phase comparison part, 125-1 to 125-m comparison unit, 130 determination part, 135 selector, 150
Inverter, 160 to 162, 165 to 167 Delay circuit, 200, 210 Semiconductor integrated circuit device, 300 system, EXTCLK external clock, INTCLK,
INTCLKa, INTCLKb Internal clock, PC
LK, PCLKb, PCLKd1 External toggle signal, S
1 to Sm switch, STB data strobe signal.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5B015 HH01 HH03 JJ24 KB36 KB84                       KB89 NN03 NN04 QQ18                 5B060 CC03 CC04                 5M024 AA04 AA49 AA72 BB27 BB33                       BB34 DD83 DD90 GG01 JJ02                       JJ04 JJ12 JJ32 JJ34 JJ36                       JJ40 PP01 PP07 PP10

Claims (10)

[Claims] 1. A semiconductor memory device mounted in a system composed of a plurality of devices that share an external clock signal, the semiconductor memory device including a pulse for instructing a data output cycle, which is different from the external clock signal. A semiconductor memory comprising: a clock generation circuit that receives a discontinuous period control signal and generates an internal clock having a period based on the pulse; and an internal circuit that executes a data output process in synchronization with the internal clock. apparatus. 2. The internal circuit generates a data strobe signal for indicating the data output cycle from the semiconductor memory device based on the internal clock signal, and the data strobe signal is output to the outside. The
The semiconductor memory device according to claim 1. 3. A semiconductor memory device mounted in a system composed of a plurality of devices that share an external clock signal, the semiconductor memory device including a pulse for instructing a data input period, which is different from the external clock signal. A semiconductor memory device comprising: a clock generation circuit that receives a cycle control signal and generates an internal clock having a cycle based on the pulse; and an internal circuit that executes a data input process in synchronization with the internal clock. 4. The first and second internal circuits for receiving a plurality of bits of input data.
Input buffer and the first to nth (n: n) for sequentially performing the data input process for one bit of the input data received by the first or second input buffer in a stepwise manner.
Natural number) n pipeline processing units, the first and second input buffers operate complementarily at a timing in response to the cycle control signal, and each of the n pipeline processing units. 4. The semiconductor memory device according to claim 3, wherein said semiconductor memory device executes a predetermined operation at a timing based on said internal clock. 5. The clock generation circuit delays the first to n-th first sub clocks obtained by delaying the internal clock by a predetermined time and an inverted clock of the internal clock by a predetermined time. The obtained 1st to nth second subclocks are further generated, and the ith pipeline processing unit (i: natural number of 1 to n) is set to the ith 1st and 2nd subclocks. And the predetermined time is 1/2 of the minimum cycle of the internal clock.
The semiconductor memory device according to claim 4, wherein the semiconductor memory device is set to be smaller than the above. 6. The clock generation circuit delays the cycle control signal stepwise by a first delay time to output a plurality of delay signals, and each of the plurality of delay signals. And a phase comparison unit for comparing the phase of the cycle control signal, based on the comparison result in the phase comparison unit, a determination unit for detecting the pulse width of the pulse, the cycle control signal and the internal A selector that receives a clock signal, outputs the internal clock signal after the generation of the internal clock signal, and outputs the cycle control signal in other periods, and in response to an instruction from the determination unit, 2. A second delay unit that delays the output of the selector by a second delay time corresponding to the pulse width to generate the internal clock.
Or the semiconductor memory device described in 3. 7. The cycle control signal includes two or more pulses, and the phase comparator compares rising edges or falling edges of the delay signals and the cycle control signal. The semiconductor memory device described. 8. The cycle control signal includes one or more pulses, and the phase comparator compares the rising edge and the falling edge of each delay signal and the cycle control signal. Semiconductor memory device. 9. A semiconductor integrated circuit device mounted in a system composed of a plurality of devices that share a clock signal, the other one of the plurality of devices being used when outputting data.
A clock for receiving a non-continuous first cycle control signal different from the clock signal, which is input together with a data output request from one of the two, and for generating an internal clock having a cycle based on the first cycle control signal signal. A generation circuit; and an internal circuit that executes a data output process in synchronization with the internal clock when outputting the data, wherein the internal circuit outputs the requested data in accordance with the cycle of the internal clock, and A semiconductor integrated circuit device which outputs a data strobe signal for indicating a data output cycle. 10. The clock generation circuit, when inputting data, receives a data input request from another one of the plurality of devices and is inputted with a discontinuous second cycle different from the clock signal. Receiving a control signal, generating an internal clock having a cycle based on the second cycle control signal signal, the internal circuit executing data input processing in synchronization with the internal clock when outputting the data. 10. The semiconductor integrated circuit device according to claim 9.