JP2007215164A - Solid-state imaging apparatus, and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus which can prevent a situation where a charge injection from a semiconductor substrate occurs at a time of charge storage to a photodiode. <P>SOLUTION: The solid-state imaging apparatus 30 includes a solid-state imaging element 40 and a driving pulse control unit 50. The solid-state imaging element 40 includes a semiconductor substrate 47, a plurality of photodiodes 41 formed on the semiconductor substrate 47 in two-dimensional shape, and a vertical CCD 43 formed by arranging at least one read-out gate for reading out an accumulated charge and non-read-out gate that does not read-out a charge for each photodiode 41. The driving pulse control unit 50 applies a driving pulse by which a LOW voltage state of a waiting is changed to a MIDDLE voltage state to the read-out gates in order and applies a driving pulse for maintaining the LOW voltage state to at least one of the non-read-out gates adjacent to the last read-out gate in a change order during a period from a beginning to an end in the change order. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device such as a CCD image sensor and a driving method thereof, and more particularly to a technique for countermeasures against white scratches during long-second accumulation.

  In recent years, the solid-state imaging device has been increased in the number of pixels to 8 million pixels or the like, and it has become possible to shoot a still image like a silver salt or a moving image. By the way, a frame interline transfer solid-state imaging device (hereinafter referred to as FITCCD) has been developed as a solid-state imaging device with very little so-called smear phenomenon.

  Hereinafter, the configuration of a conventional FITCCD and a method for driving the FITCCD will be described with reference to the drawings.

FIG. 16 is an enlarged view showing a part of the FITCCD.
First, the configuration of the FITCCD will be described.

  In FIG. 16, a solid-state imaging device 100 includes a photodiode 101 arranged two-dimensionally on a semiconductor substrate (not shown), a vertical CCD 102 for transferring signal charges accumulated in the photodiode 101 in the vertical direction, , An accumulation area (not shown) for accumulating signal charges transferred by the vertical CCD 102, a horizontal CCD (not shown) for transferring charges accumulated in the accumulation area in the horizontal direction, and transferred by the horizontal CCD. And an output unit (not shown) for detecting and outputting the signal charges and a drain unit (not shown) for discharging unnecessary charges.

  The vertical CCD 102 includes a channel region, transfer electrodes (hereinafter also referred to as “read gates”) 105 a, 105 b, 105 c, and 105 d that function as read electrodes for reading signal charges from the photodiode 101, and the photodiode 101. Transfer electrodes (hereinafter also referred to as “non-read gates”) 104a, 104b, 104c, and 104d that do not have a function as a read electrode for reading signal charges from.

Next, a conventional driving method will be described with reference to a voltage waveform diagram shown in FIG.
In FIG. 17, φ1 is a voltage pulse applied to read gates 105a and 105c, φ2 is a voltage pulse applied to non-read gates 104b and 104d, and φ3 is applied to read gates 105b and 105d, respectively. And φ4 is a voltage pulse applied to each of the non-read gates 104a and 104c.

  In the conventional driving method, in the period t4 when charges are not read out in the vertical period, for example, in the period t4 when charges are accumulated in the photodiode 101, the voltage pulses φ1 and φ3 become L level and the voltage pulses φ2 and φ4 are H levels. It is a level. That is, in the conventional driving method, in the period t4 when charges are not read in the vertical period, for example, in the period t4 when charges are accumulated in the photodiode 101, the voltage pulses φ1 and φ3 are set to the L level, and the charge reading period t2 The polarity is opposite to that of the H level.

As a result, the potential of the overlapping portion of read gates 105a, 105b, 105c, and 105d becomes non-depleted when a voltage pulse L level is applied, and holes are accumulated immediately below the overlapping portion of read gates 105a, 105b, 105c, and 105d. . For this reason, the occurrence of dark current is extremely reduced when the L level is applied. Therefore, the generation of dark current at the overlapping portion of the photodiode 101 and the read gates 105a, 105b, 105c, and 105d is remarkably reduced, and the quality of the reproduced image is improved.
Japanese Patent No. 2851631

  However, in the conventional driving method, when holes are accumulated directly under the readout gate to prevent an increase in dark current, if the holes are accumulated too much, the potential of the semiconductor substrate becomes unstable, and the reverse of unnecessary charges from the semiconductor substrate to the photodiode. Injection tends to occur.

  That is, in a long-second accumulation mode (hereinafter also referred to as a long-time accumulation mode) in which charges are accumulated in a photodiode for two or more vertical periods, the potential of the semiconductor substrate is shifted due to accumulated holes, and only white defects are generated. In addition, the charge accumulated in the photodiode is hindered from being read out, and unnecessary charge is also injected into the channel of the vertical CCD, thereby disturbing the transfer of the read out charge.

In particular, such a problem becomes conspicuous in a situation in which miniaturization advances and electric field concentration easily occurs.
Accordingly, the present invention provides a solid-state imaging device and a driving method thereof that can prevent a situation in which the potential of the semiconductor substrate becomes unstable and charge injection from the semiconductor substrate occurs during charge accumulation in the photodiode. For the purpose.

  In order to achieve the above object, in the solid-state imaging device according to the present invention, a semiconductor substrate, a plurality of photodiodes formed two-dimensionally on the semiconductor substrate, and each photodiode is accumulated. A solid-state imaging device having a vertical CCD formed by arranging at least one readout gate for reading out charges and a non-readout gate that does not read out charges, and for each of the readout gate and the non-readout gate Drive pulse control means for controlling the solid-state imaging device by applying a drive pulse at a predetermined timing, and the drive pulse control means for each readout gate from a standby LOW voltage state to a MIDDLE voltage A drive pulse for changing the state is sequentially applied, and a non-read gate adjacent to the last read gate in the order of the change is applied. For at least one of the, during the period from the first in the order of the change to the end, and applying a driving pulse to maintain a LOW voltage state.

  As a result, the holes accumulated when the read gate is in the LOW voltage state are opened, and the released holes are smoothly and sequentially distributed in the direction of the non-read gate. Therefore, the semiconductor substrate potential can be kept stable even when the holes are opened, and the situation where charge injection from the semiconductor substrate occurs can be prevented. In addition, white scratches due to charges generated during hole movement can be prevented. In particular, even when driving to lower the Vsub of the semiconductor substrate during the charge accumulation of the photodiode, the semiconductor substrate is stable, so that the injection problem does not occur even if the Vsub is lowered.

  In the solid-state imaging device according to the present invention, a semiconductor substrate, a plurality of photodiodes formed two-dimensionally on the semiconductor substrate, and readout for reading out the accumulated charge for each of the photodiodes A solid-state imaging device having a vertical CCD formed by disposing at least one gate and a non-read gate that does not read charges, and is driven at a predetermined timing with respect to each of the read gate and the non-read gate Drive pulse control means for controlling the solid-state imaging device by applying a pulse, and the solid-state imaging device reads out the charges accumulated in all the photodiodes to the vertical CCD by N reading operations. The driving pulse control means can be configured to output the MIDDLE voltage from the standby LOW voltage state to the N read gates. A drive pulse for changing the state is sequentially applied, and at least one of the non-read gates adjacent to any of the (N−1) -th and N-th read gates in the order of change, N in the order of change. A drive pulse for setting the LOW voltage state may be applied between the −1st and the Nth.

  This also releases the accumulated holes when the read gate is in the LOW voltage state, and the released holes are smoothly and sequentially distributed in the direction of the non-read gate. Therefore, the semiconductor substrate potential can be kept stable even when the holes are opened, and the situation where charge injection from the semiconductor substrate occurs can be prevented. In addition, white scratches due to charges generated during hole movement can be prevented. In particular, even when driving to lower the Vsub of the semiconductor substrate during the charge accumulation of the photodiode, the semiconductor substrate is stable, so that the injection problem does not occur even if the Vsub is lowered.

  In the solid-state imaging device according to the present invention, a semiconductor substrate, a plurality of photodiodes formed two-dimensionally on the semiconductor substrate, and readout for reading out the accumulated charge for each of the photodiodes A solid-state imaging device having a vertical CCD formed by disposing at least one gate and a non-read gate that does not read charges, and is driven at a predetermined timing with respect to each of the read gate and the non-read gate Drive pulse control means for controlling the solid-state imaging device by applying a pulse, and the drive pulse control means drives the read gates to simultaneously change from a standby LOW voltage state to a MIDDLE voltage state. It is also possible to apply a pulse.

  As a result, since the holes are opened before gathering under one read gate, the released holes are smoothly and sequentially distributed in the direction of the non-read gate. Therefore, the semiconductor substrate potential can be kept stable even when the holes are opened, and the situation where charge injection from the semiconductor substrate occurs can be prevented. In addition, white scratches due to charges generated during hole movement can be prevented.

  In the solid-state imaging device according to the present invention, the drive pulse control unit may further change the drive pulse for the read gate from the standby LOW voltage state to the MIDDLE voltage state for each non-read gate. At the same time, a drive pulse for changing from the MIDDLE voltage state to the LOW voltage state can be applied.

  As a result, the released holes are more smoothly and sequentially distributed in the direction of the non-read gate. Therefore, the semiconductor substrate potential can be kept stable even when the holes are opened, and the situation where charge injection from the semiconductor substrate occurs can be prevented. In addition, white scratches due to charges generated during hole movement can be prevented.

  In the solid-state imaging device according to the present invention, the solid-state imaging device can read out the charges accumulated in all the photodiodes by N reading operations to the vertical CCD, and the drive pulse control means includes: Further, at the start of the transfer operation of one field or one frame, as a connection operation for connection to the transfer, all of the gates are compared with a continuous gate consisting of N read gates and at least N non-read gates. A drive pulse for changing each gate to the MIDDLE voltage state in order from the state of the LOW voltage is applied.

  As a result, a pulse whose voltage state changes at different timings is applied to each gate, and unnecessary charges are diffused to prevent the occurrence of charge injection from the semiconductor substrate. Therefore, it is possible to prevent white scratches due to charges generated during hole movement.

  In the solid-state imaging device according to the present invention, the drive pulse control means performs the connecting operation at (a) the start of the first field transfer or (b) at the start of the high-speed transfer of the vertical CCD. It can also be.

  This suppresses unnecessary reverse charge injection before the start of vertical transfer, thereby avoiding the occurrence of white flaws.

  In the solid-state imaging device according to the present invention, the drive pulse control unit further changes the overflow barrier to a high level before the end of the exposure period, and accumulates signal charges up to the barrier height of the readout gate. And a second bias modulation for changing the height of the overflow barrier to a low level after the exposure period ends and before the charge discharge of the vertical CCD, and after the exposure period ends and before the second bias modulation. It is also possible to perform the operation.

Thereby, blooming can be prevented.
In the solid-state imaging device according to the present invention, a semiconductor substrate, a plurality of photodiodes formed two-dimensionally on the semiconductor substrate, and readout for reading out the accumulated charge for each of the photodiodes A solid-state imaging device having a vertical CCD formed by disposing at least one gate and a non-read gate that does not read charges, and is driven at a predetermined timing with respect to each of the read gate and the non-read gate Drive pulse control means for controlling the solid-state imaging device by applying a pulse, and the solid-state imaging device reads out the charges accumulated in all the photodiodes to the vertical CCD by N reading operations. Further, the drive pulse control means can further perform transfer at the start of the transfer operation of one field or one frame. As a connecting operation for switching, a continuous gate consisting of N read gates and at least N non-read gates changes all gates from a LOW voltage state to a MIDDLE voltage state in turn. A drive pulse to be applied is applied.

  Also by this, a pulse whose voltage state changes at different timings is applied to each gate, and unnecessary charges are diffused to prevent the occurrence of charge injection from the semiconductor substrate. Therefore, it is possible to prevent white scratches due to charges generated during hole movement.

  Note that the present invention can be realized not only as such a solid-state imaging device but also as a driving method using steps characteristic of the solid-state imaging device, or by performing these steps in a computer. It can also be realized as a program to be executed. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM or a transmission medium such as the Internet. Furthermore, it can also be configured as a camera equipped with such a solid-state imaging device.

  As is apparent from the above description, according to the solid-state imaging device according to the present invention, the accumulated holes are opened when the read gate is in the LOW voltage state, and the released holes are smoothly and sequentially dispersed in the direction of the non-read gate. Is done. Therefore, in the hole accumulation state, the semiconductor substrate potential becomes unstable, and it is possible to prevent a situation where charge injection from the semiconductor substrate occurs. In addition, white scratches due to charges generated during hole movement can be prevented. In particular, even when driving to lower the Vsub of the semiconductor substrate during charge accumulation of the photodiode, the semiconductor substrate is stable, so that there is no problem of implantation even if the Vsub is lowered.

  Therefore, the present invention prevents the occurrence of white flaws, and the practical value of the present invention of the present application in which digital cameras have become widespread is extremely high.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram illustrating a configuration of a camera using the solid-state imaging device according to the present embodiment.

  As shown in FIG. 1, a camera 1 includes a lens 10 that forms an optical image of a subject on an image sensor, a mirror that performs optical processing of the optical image that has passed through the lens 10, and an optical system such as a mechanical shutter (mechanical shutter). 20, a solid-state imaging device 30 according to the present invention, a signal processing unit 60, a digital signal processor (hereinafter also referred to as “DSP”) 70, and the like.

The solid-state imaging device 30 includes a solid-state imaging device 40 and a drive pulse control unit 50.
The solid-state imaging device 40 is realized by a CCD image sensor or the like, and outputs a pixel signal corresponding to the amount of received light.

  The drive pulse controller 50 drives the solid-state image sensor 40 by generating various drive pulses at various timings with respect to the solid-state image sensor 40 in accordance with instructions from the DSP 70.

  The signal processing unit 60 includes a CDS (Correlated Double Sampling) circuit 61 that takes a difference between a field-through signal output from the solid-state imaging device 40 and an output signal, and an OB (Optical Black) level output from the CDS circuit 61. An OB clamp circuit 62 that detects a signal, a GCA (Gain Control Amplifier) 63 that takes a difference between the OB level and the signal level of the effective pixel, and adjusts the gain of the difference, and an analog signal output from the GCA 63 is converted into a digital signal. ADC (Analog-to-Digital Converter) 64 and the like to be converted into

  The DSP 70 performs signal processing on the digital signal output from the ADC 64 and controls the drive pulse controller 50.

FIG. 2 is a block diagram showing a configuration of the solid-state imaging device 40 shown in FIG.
As shown in FIG. 2, the solid-state imaging device 40 is an interline transfer (IT) type CCD image sensor, and includes a semiconductor substrate 47 and a plurality of photodiodes 41 two-dimensionally arranged on the semiconductor substrate 47. , A plurality of read gate units 42, a plurality of vertical CCDs 43, a horizontal CCD 45, an output amplifier 46, a substrate bias voltage generation circuit 80, and a transistor Q1. Also shown in the figure are a transistor Q2, resistors R1 to R3, and a capacitor C as a circuit for modulating a bias voltage (hereinafter also referred to as a substrate bias) Vsub of the semiconductor substrate 47 of the solid-state imaging device. .

  By controlling the substrate bias Vsub, a decrease in the saturation signal charge amount Qs at the time of frame reading is anticipated, and the decrease is increased in advance. Here, frame reading is a method in which the mechanical shutter (not shown) of the optical system 20 is closed after the exposure time has elapsed, and the signal charges of the odd lines and the signal charges of the even lines are read in field units. It is often used when acquiring images.

  In FIG. 2, a plurality of photodiodes 41 are two-dimensionally arranged to form an imaging area 44. Each photodiode 41 converts incident light into a signal charge corresponding to the amount of light and accumulates it. Each photodiode 41 is composed of, for example, a PN junction photodiode. The signal charges accumulated in the photodiodes 41 forming a vertical column are read out to the vertical CCD 43 by applying a read pulse XSG to the read gate unit 42.

  The vertical CCD 43 is provided for each vertical column of the photodiodes 41, and vertically transfers the signal charges read from each photodiode 41 through the read gate unit 42 to the horizontal CCD 45. In the case of an IT-type solid-state imaging device, each vertical CCD 43 is repeatedly provided with vertical transfer gate electrodes for transfer driving by, for example, six-phase vertical transfer clocks φV1 to φV6 as in the case of FIG. The signal charges read from are sequentially transferred in the vertical direction. As a result, signal charges for one scanning line (one line) are output from the plurality of vertical CCDs 43 to the horizontal CCD 45 in the horizontal blanking period. Of the six-phase vertical transfer clocks φV1 to φV6, φV2, φV4, and φV6 of the second phase, the fourth phase, and the sixth phase can take two values of a low level and a middle level for vertical transfer. On the other hand, since the vertical transfer gate electrodes corresponding to the first phase, the third layer, and the fifth phase also serve as the read gate electrode of the read gate unit 42, the vertical transfer clocks φV1, φV3, and φV5 are It can take three values: low level, middle level and high level. This third high-level pulse becomes a read pulse XSG given to the read gate section 42.

  When the vertical CCD 43 is configured to be driven to transfer by the vertical transfer clocks φV1 to φV8, the second phase, the fourth phase, the sixth phase, and the eighth phase φV2 of the eight-phase vertical transfer clocks φV1 to φV8. , .Phi.V4, .phi.V6, and V8 are applied to the non-read gate, and vertical transfer clocks .phi.V1, .phi.V3, .phi.V5, and .phi.V7 are applied to the read gate.

  The horizontal CCD 45 sequentially transfers the charges for one line transferred from the plurality of vertical CCDs 43 in the horizontal blanking period in one horizontal scanning period, and outputs them through the output amplifier 46. The horizontal CCD 45 is driven to transfer by, for example, two-phase horizontal transfer clocks φH 1 and φH 2, and the signal charges for one line transferred from the plurality of vertical CCDs 43 are sequentially moved in the horizontal direction in the horizontal scanning period after the horizontal blanking period. Forward to.

  The output amplifier 46 sequentially converts the signal charges horizontally transferred by the horizontal CCD 45 into voltage signals and outputs them.

  The substrate bias voltage generation circuit 80 generates a substrate bias voltage Vsub and applies it to the semiconductor substrate 47 via the transistor Q1. This substrate bias Vsub is set to a first bias voltage when the transistor Q2 is off and to a lower second bias voltage when the transistor Q2 is on under the control of the VsubCont signal.

  The solid-state image sensor 40 is formed on a semiconductor substrate (hereinafter also simply referred to as a substrate) 47. Various timing signals such as a substrate shutter pulse φSUB for sweeping signal charges accumulated in the photodiode 41 to the semiconductor substrate 47 are applied to the semiconductor substrate 47. The substrate shutter function by the substrate shutter pulse φSUB is also called an electronic shutter.

  FIG. 3 is a cross-sectional view showing the structure in the substrate depth direction around the photodiode 41 and the vertical CCD 43.

  In the figure, for example, a P-type well region 91 is formed on the surface of an N-type semiconductor substrate 47. An N-type signal charge storage region 92 is formed on the surface of the P-type well region 91, and a P + -type hole storage region 93 is further formed thereon to constitute the photodiode 41.

  The amount of signal charge e accumulated in the photodiode 41 is determined by the height of the potential barrier of the overflow barrier OFB formed of the P-type well region 91. The overflow barrier OFB determines the saturation signal charge amount Qs accumulated in the photodiode 41. When the accumulated charge amount exceeds the saturation signal charge amount Qs, the excess charge exceeds the potential barrier. Sweeped out to the semiconductor substrate 47 side.

  In this way, a photodiode 41 having a so-called vertical overflow drain structure is formed.

  In the lateral direction of the photodiode 41, an N-type signal charge transfer region 95 and a P + -type channel stopper region 96 are formed via a portion of the P-type well region 91 that constitutes the read gate portion 42. Under the signal charge transfer region 95, a P + type impurity diffusion region 97 for preventing the smear component from being mixed is formed. Further, a vertical CCD 43 is configured above the signal charge transfer region 95 by disposing a transfer electrode 99 made of, for example, polycrystalline silicon. In the transfer electrode 99, the portion located above the P-type well region 91 also serves as the gate electrode of the read gate portion 42.

  A substrate bias Vsub that determines the amount of signal charges accumulated in the photodiode 41 (that is, determines the potential of the overflow barrier OFB) is applied to the semiconductor substrate 47.

FIG. 4 is a diagram showing the potential distribution of the photodiode 41 in the substrate depth direction.
The amount of the signal charge e accumulated in the photodiode 41 is determined by the height of the potential barrier of the overflow barrier OFB. That is, the overflow barrier OFB determines the saturation signal charge amount Qs accumulated in the photodiode 41. When the accumulated charge amount exceeds the saturation signal charge amount Qs, the excess charge is swept out to the semiconductor substrate 47 side beyond the potential barrier. The potential of the overflow barrier OFB in such a vertical overflow drain structure can be controlled by the overflow drain bias, that is, the substrate bias Vsub. That is, the height of the barrier can be controlled by the substrate bias Vsub.

  The drive pulse control unit 50 instructs the DSP 70 to store charges in the photodiode 41 for a time of 2 vertical periods or more (for example, 8 seconds). When the mechanical shutter of the optical system 20 is opened, the drive pulse control unit 50 stores long seconds. Run the mode. Next, when the instructed time elapses and the mechanical shutter is closed, the drive pulse control unit 50 ends the execution of the long-second accumulation mode, transfers only the vertical CCD 43, and sweeps out the channel noise of the vertical CCD 43. The vertical CCD sweep mode is executed. Next, when the execution of the vertical CCD sweep mode is completed, the drive pulse controller 50 causes the vertical CCD 43 to read out the charges accumulated in all the photodiodes 41, and the read charges from the vertical CCD 43 to the accumulation unit. 49, transferred from the storage unit 49 to the horizontal CCD 45, and output via the output amplifier 46.

  Next, processing for white scratch countermeasures in the long-second accumulation mode performed in the drive pulse controller 50 will be described.

  Here, the general timing in the long-second accumulation mode will be described before the processing for white scratch countermeasures in the long-second accumulation mode performed in the drive pulse control unit 50 according to the present application.

FIG. 5 is a diagram showing a general timing in the long second accumulation mode.
FIGS. 5A to 5F show the six-phase drive pulses φV1 to φV6, respectively, and FIG. 5G shows the SUB pulse.

  At a general timing in the long-second accumulation mode, the drive pulse controller 50 first outputs a SUB pulse during the change point 60T to 116T in a certain horizontal period. For the drive pulse φV1, the drive pulse control unit 50 changes to the middle level between the change points 150T to 240T and between the change points 330T to 540T. For the drive pulse φV2, the drive pulse control unit 50 changes to a low level during the change points 300T to 390T. For the drive pulse φV3, the drive pulse control unit 50 changes to the middle level between the change points 120T to 360T and between the change points 450T to 570T. The drive pulse controller 50 changes the drive pulse φV4 to a low level during the change points 420T to 510T. For the drive pulse φV5, the drive pulse control unit 50 changes to the middle level between the change points 210T to 480T. For the drive pulse φV6, the drive pulse control unit 50 changes to a low level during the change points 180T to 270T.

  Next, such general timing and the timing in the long-second accumulation mode according to the present application will be compared and described.

  6 and 7 are diagrams showing a difference between white scratch fields by comparing a general timing with a timing according to the present application. Here, the white scratch level may be different for each of the photodiodes read by the read gates of φV1, φV3, and φV5, and this will be referred to as a difference between white scratch fields.

  FIG. 6A is a diagram showing the general timing of FIG. 5 described above. At this time, the injection limit substrate voltage injected from the semiconductor substrate to the photodiode is 2.53 V or less.

  With respect to the driving pulse, φV1, φV3, φV5 are maintained at a low level, φV2, φV4, and φV6 are maintained at a middle level, and a standby state is maintained in a state where holes are accumulated immediately below each readout gate that is at a low level.

  When the drive pulse φV3 is changed to the middle level at the change point 120T, the holes accumulated immediately below the read gate to which the drive pulse φV3 is applied are released, and the direction of the non-read gate to which the drive pulses φV2 and φV4 are applied is released. To be distributed.

  Next, when the drive pulse φV1 is changed to the middle level at the change point 150T, the holes accumulated immediately below the read gate to which the drive pulse φV1 is applied are released, and the non-read gate to which the drive pulses φV2 and φV6 are applied. Distributed in the direction of

Next, at the change point 180T, the drive pulse φV6 is changed to a low level.
Next, when the drive pulse φV5 is changed to the middle level at the change point 210T, the holes accumulated immediately below the read gate to which the drive pulse φV5 is applied are released, and the non-read gate to which the drive pulses φV4 and φV6 are applied. To be distributed in the direction of. However, holes are already dispersed both near the non-read gate to which the drive pulses φV4 and φV6 are applied. In addition, since the non-read gate to which the drive pulse φV6 is applied has little time elapsed since being set to the low level, the dispersed holes are still accumulated. Therefore, the holes accumulated immediately below the read gate to which the drive pulse φV5 is applied are not easily dispersed.

  Further, when the movement of the hole suddenly occurs during the opening of the hole, electrons generated due to the influence of impact ions or the like are accumulated as noise in the photodiode, resulting in a white defect.

  FIG. 6B is a diagram showing the relationship between this general timing and the number of scratches. As shown in the figure, the drive pulse φV5 is changed to the middle level, and the number of scratches at the time is greatly increased.

  In contrast, FIG. 6C is a diagram showing the first timing in the long second accumulation mode according to the present application. At this time, the injection limit substrate voltage injected from the semiconductor substrate into the photodiode is 2.53 V or less, indicating that the potential of the semiconductor substrate is as stable as the conventional one.

  That is, as shown in FIG. 6 (c), the drive pulse control unit 50 for the drive pulses φV1, φV3, and φV5, between the change points 120T to 180T, between the change points 240T to 300T, and between the change points 360T to 360T. During 420T and between change points 480T to 540T, the middle level is changed simultaneously. Regarding the drive pulses φV2, φV4, and φV6, the drive pulse controller 50 reverses the drive pulses φV1, φV3, and φV5, changes between the change points 120T to 180T, the change points 240T to 300T, and the change points 360T to 420T. And change to a low level between the change points 480T to 540T. Such simultaneous driving is also referred to as “pumping driving”.

  During other periods, the drive pulses are kept in a state where φV1, φV3, φV5 are kept at the low level, φV2, φV4, and φV6 are kept at the middle level, and holes are accumulated immediately below each read gate that is at the low level. Yes.

  According to the pumping drive by such driving pulses φV1, φV3, and φV5, holes are released before gathering under one readout gate, so that the released holes are smoothly and sequentially dispersed in the direction of the non-read gate. Is done. Therefore, the semiconductor substrate potential can be kept stable even when the holes are opened, and the situation where charge injection from the semiconductor substrate occurs can be prevented. In addition, white scratches due to charges generated during hole movement can be prevented.

  Further, according to the pumping drive by the drive pulses φV2, φV4, and φV6, the released holes are more smoothly and sequentially distributed in the direction of the non-read gate. Therefore, the semiconductor substrate potential can be kept stable even when the holes are opened, and the situation where charge injection from the semiconductor substrate occurs can be prevented. In addition, white scratches due to charges generated during hole movement can be prevented.

  FIG. 6D shows the relationship between the pumping drive timing and the number of scratches. As shown in the figure, it can be seen that the drive pulses φV1, φV3, and φV5 are changed to the middle level, and the number of scratches at the time is greatly reduced.

  FIG. 7A is a diagram showing the second timing in the long second accumulation mode according to the present application. At this time, the injection limit substrate voltage injected from the semiconductor substrate into the photodiode is 2.53 V or less, indicating that the potential of the semiconductor substrate is as stable as the conventional one.

  As shown in FIG. 7A, the drive pulse controller 50 changes the drive pulse φV6 to a low level during the change points 120T to 270T. For the drive pulse φV1, the drive pulse control unit 50 changes to the middle level between the change points 180T to 240T and between the change points 330T to 540T. For the drive pulse φV2, the drive pulse control unit 50 changes to a low level during the change points 300T to 390T. For the drive pulse φV3, the drive pulse control unit 50 changes to the middle level between the change points 150T to 360T and between the change points 450T to 510T. The drive pulse controller 50 changes the drive pulse φV4 to a low level during the change points 420T to 510T. For the drive pulse φV5, the drive pulse control unit 50 changes to the middle level between the change points 210T to 480T.

  That is, the driving pulse φV6 is changed to a low level, and thereafter, the driving pulses φV3, φV1, and φV5 are sequentially changed to a middle level, which is largely different from the general driving method shown in FIG.

  During other periods, the drive pulses are kept in a state where φV1, φV3, φV5 are kept at the low level, φV2, φV4, and φV6 are kept at the middle level, and holes are accumulated immediately below each read gate that is at the low level. Yes.

  According to such driving, the non-read gate to which the drive pulse φV6 is applied has a long time since being set to the low level, so that the holes accumulated immediately below the gate are in a stable state and at the low level. In some cases, a hole is easily moved. Therefore, when the middle level voltage is applied to the drive pulse φV5, the holes accumulated immediately below the gate at the low level are likely to move to the adjacent φV6 gate and are very easily dispersed.

  As a result, the holes accumulated when the read gate is in the LOW voltage state are opened, and the released holes are smoothly and sequentially distributed in the direction of the non-read gate. Therefore, the semiconductor substrate potential can be kept stable even when the holes are opened, and the situation where charge injection from the semiconductor substrate occurs can be prevented. In addition, white scratches due to charges generated during hole movement can be prevented. In particular, even when driving to lower the Vsub of the semiconductor substrate during charge accumulation of the photodiode, the semiconductor substrate is stable, so that there is no problem of implantation even if the Vsub is lowered.

  FIG. 7B is a diagram showing the relationship between the timing of the second drive and the number of scratches. As shown in the figure, it can be seen that the drive pulses φV1, φV3, and φV5 are changed to the middle level, and the number of scratches at the time is greatly reduced.

Next, the difference driving dependency between white scratch fields will be examined.
FIG. 8 and FIG. 9 are diagrams showing the timing indicating the difference drive dependency between white flaw fields and the relationship with the number of flaws.

  FIG. 8A is a diagram showing the timing of pumping driving corresponding to FIG. 6C, and FIG. 8B is a diagram showing the relationship with the number of scratches at that timing. Here, the period of change is extended as compared with FIG. That is, as shown in FIG. 8A, the drive pulse control unit 50 for the drive pulses φV1, φV3, and φV5, between the change points 120T to 312T, between the change points 504T to 696T, and between the change points 888T to 888T. During 1086T and between change points 1272T to 1464T, the middle level is changed simultaneously. Regarding the drive pulses φV2, φV4, and φV6, the drive pulse controller 50 reverses the drive pulses φV1, φV3, and φV5, between the change points 120T to 312T, between the change points 504T to 696T, and between the change points 888T to 1086T. And change to a low level between change points 1272T to 1464T.

  During other periods, the drive pulses are kept in a state where φV1, φV3, φV5 are kept at the low level, φV2, φV4, and φV6 are kept at the middle level, and holes are accumulated immediately below each read gate that is at the low level. Yes.

  White scratches can also be reduced by such pumping drive that extends the period of change. However, as a result of extending the period of the change, the accumulation of holes becomes larger than the pumping drive shown in FIG. 6C, and the number of white scratches increases. Therefore, white scratches are reduced by shortening the period of change for driving pulses φV1, φV3, φV5 from low level to middle level and for driving pulses φV2, φV4, φV6 from middle level to low level. Can be made.

  FIG. 8C is a diagram showing timing similar to pumping driving, and FIG. 8D is a diagram showing the relationship with the number of scratches at that timing.

  At timing similar to this pumping drive, as shown in FIG. 8C, the drive pulse control unit 50 for the drive pulses φV1 and φV5 is between the change points 120T to 312T and between the change points 888T to 1086T. The drive pulse φV3 is changed to the middle level between the change points 504T to 696T and between the change points 1272T to 1464T. Regarding the drive pulses φV2 and φV6, the drive pulse controller 50 simultaneously changes to the low level between the change points 120T to 312T and between the change points 888T to 1086T, in contrast to the drive pulses φV1 and φV5, and the drive pulse φV4 Is changed to a low level between the change points 504T to 696T and between the change points 1272T to 1464T.

  During other periods, the drive pulses are kept in a state where φV1, φV3, φV5 are kept at the low level, φV2, φV4, and φV6 are kept at the middle level, and holes are accumulated immediately below each read gate that is at the low level. Yes.

  Even with such a drive similar to the pumping drive, as shown in FIG. 8D, white scratches can be reduced as in the case of the pumping drive shown in FIG.

  FIG. 9A is a diagram showing another timing similar to pumping driving, and FIG. 9B is a diagram showing the relationship with the number of scratches at that timing.

  At a timing similar to this pumping drive, as shown in FIG. 8A, the drive pulse control unit 50 changes between the change points 888T to 1086T for the drive pulse φV1 and changes from the change point 504T to about the drive pulse φV3. During 696T, the drive pulse φV5 is changed to a low level during the change points 120T to 312T. Further, the drive pulse control unit 50 has a middle level between the change points 888T to 1086T for the drive pulse φV2, between the change points 504T to 696T for the drive pulse φV4, and between the change points 120T to 312T for the drive pulse φV6. To change each.

  During other periods, the drive pulses are kept in a state where φV1, φV3, φV5 are kept at the low level, φV2, φV4, and φV6 are kept at the middle level, and holes are accumulated immediately below each read gate that is at the low level. Yes.

  Even with such another driving similar to the pumping drive, as shown in FIG. 9B, white scratches can be reduced as in the case of the pumping drive shown in FIG. 8A.

  FIG. 9C is a diagram showing still another timing similar to pumping driving, and FIG. 9D is a diagram showing the relationship with the number of scratches at that timing.

  At a timing similar to this pumping drive, as shown in FIG. 9C, the drive pulse control unit 50 for the drive pulse φV1, during the change points 120T to 312T and between the change points 888T to 1086T, The drive pulse φV3 is changed to the middle level between the change points 504T to 696T and the change points 888T to 1080T, and the drive pulse φV5 is changed to the middle level between the change points 120T to 312T and the change points 504T to 696T. Further, the drive pulse control unit 50 applies only between the change points 888T to 1086T for the drive pulse φV2, only between the change points 504T to 696T for the drive pulse φV4, and between the change points 120T to 312T for the drive pulse φV6. Just change each to the middle level.

  During other periods, the drive pulses are kept in a state where φV1, φV3, φV5 are kept at the low level, φV2, φV4, and φV6 are kept at the middle level, and holes are accumulated immediately below each read gate that is at the low level. Yes.

  That is, with respect to the pair of even-numbered phase and odd-numbered phase, the corresponding reverse level pulse drive is omitted, and the drive pulse is applied to only one of them.

  According to the driving in which the driving pulse is applied to only one of them, it is understood that the hole diffusion is inhibited and the white scratches increase as shown in FIG.

  Therefore, as a result of various drive studies, in addition to the case of the pumping drive shown in FIG. 8 (a), the case of the drive similar to the pumping drive shown in FIG. 8 (c) and FIG. 9 (a), that is, For a pair of even-numbered phase and odd-numbered phase, a drive pulse for simultaneously changing from a standby LOW voltage state to a MIDDLE voltage state is applied to the read gate, and for a non-read gate, the read gate The white scratch can be reduced by applying a drive pulse for changing from the MIDDLE voltage state to the LOW voltage state at the same time as the drive pulse for the is changed from the standby LOW voltage state to the MIDDLE voltage state.

  Further, white scratches can also be obtained by shortening the period of change for the drive pulses φV1, φV3, φV5 from the low level to the middle level, and for the drive pulses φV2, φV4, φV6 from the middle level to the low level. Can be reduced.

  Next, in the case of sequentially driving as shown in FIG. 7A, the non-read gate adjacent to the last gate (φV5 gate in FIG. 7) in which the read gate waiting at the low level changes to the middle level. FIG. 7 shows the result of studying the case where the change point of φV6 gate is shifted.

  In the following, the dependency of the position of the change point at which V8 in 8-phase driving first changes from the middle level to the low level will be examined. The position of the change point at which V8, which is the last phase in the 8-phase drive, first changes from the middle level to the low level is also referred to as the position of the first change point.

  FIG. 10 is a diagram illustrating the dependency of the position of the first change point. In particular, FIG. 10A is a diagram showing a normal timing corresponding to FIG. 10C, and FIG. 10B is a unit for shifting the position of the first change point with reference to V8 in FIG. 10A. FIG. 10C is a diagram showing level change events of the drive pulses φV1, φV3, φV5, and φV7 applied to the read gate, and FIG. 10D is a diagram showing the position of the first change point. It is a figure which shows the relationship between a shift unit and the number of flaws.

  Here, in the conventional V-level change pattern during long-second accumulation, the position (MtoL) of the first change point of V8 is shifted back and forth, and the change in the difference between white flaw fields was verified.

  As a result of the verification, after the V1 level change timing, white scratches tended to increase when the V7 level change timing peaked in the VSG7 read field, that is, when the shift direction was +. After that, it turns and decreases to a certain level, but does not return to the original level and the inter-field difference is not resolved.

  On the contrary, when the shift direction is-, it can be seen that white scratches decrease as the shift is made to the change point of φV1, the change point of φV3, and the change point of φV5. That is, according to the third driving in which the driving pulse φV8 is set to the low level at the two changing points of the driving pulses φV7 and φV1, white scratches are reduced.

  That is, in addition to the driving shown in FIG. 7A, a driving pulse for changing from the standby LOW voltage state to the MIDDLE voltage state is sequentially applied to N read gates, and N−1 in the order of this change. At least one of the non-read gates adjacent to any of the Nth and Nth read gates is provided with a drive pulse for setting a LOW voltage state between the (N−1) th and the Nth in the order of this change. By applying the white scratches, white scratches can be drastically reduced.

  Here, as described so far, white scratches on the photodiode are drastically reduced by sequential driving as shown in FIG. 7A and pumping driving as shown in FIG. 6C. However, unnecessary charges may be injected into the vertical CCD channel as noise due to hole accumulation and hole diffusion movement. For this reason, as described above, when the drive pulse control unit 50 ends the execution of the long-second accumulation mode, the drive pulse control unit 50 executes the vertical CCD sweep mode in which only the vertical CCD 43 is transferred and driven and the channel noise of the vertical CCD 43 is swept away. Thereafter, the charges accumulated in all the photodiodes 41 are read out by the vertical CCD 43. Therefore, only charges without white defects can be transferred from the vertical CCD 43 to the horizontal CCD 45 and output via the output amplifier 46.

  In addition, when the driving according to the present application is used, the above-described vertical CCD sweep mode may be further effective. That is, in the case of the drive shown in FIG. 6A, the noise electrons accumulated in the non-read gate are sequentially transferred even during the long second accumulation mode period. Is not driven to transfer noise electrons completely even in the sequential drive as shown in FIG. 7A or the pumping drive as shown in FIG. 6C, so that the noise electrons that are not completely transferred in the vertical CCD sweep mode. By sweeping out the signal, a signal output with less noise can be obtained.

  In the case of the drive in FIG. 7A, the φV6 gate changes from the middle level to the low level while the adjacent gate is in the low level state, so that the noise electrons immediately below are transferred in the original transfer direction. It ’s not that hard. Also, in the case of the driving shown in FIG. 6C, adjacent gates simultaneously change to opposite levels, so that the noise electrons are not always transferred in the original transfer direction. Therefore, by performing the vertical CCD sweep mode in addition to the driving of the present application, the effect of reducing white scratches, the effect of stabilizing the substrate potential, and the effect of reducing noise are combined.

  In the above-described embodiment, the drive pulses φV1 to φV6 (φV7, φV8) are applied to the read gate and the non-read gate in that order, but the same effect can be obtained even if the gate order is changed. Can do.

  In the above embodiment, the example of 3: 1 interlace or 4: 1 interlace is mainly described. However, the same effect can be obtained with other configurations.

  Furthermore, although φV2, φV4, and φV6 are simultaneously set to the reverse level during the pumping driving of φV1, φV3, and φV5, only φV2, φV4, and φV6 adjacent to φV1, φV3, and φV5 that are pumping driven may be set to the reverse level.

  In the above embodiment, the IT solid-state imaging device is used. However, a solid-state imaging device such as a frame interline transfer (FIT) system having a storage unit disposed between the vertical CCD 43 and the horizontal CCD 45 is used. May be implemented. In the case of the FIT type solid-state image pickup device, the vertical transfer can be driven differently in the image pickup area and the storage unit. Even if not, the effect of reducing white scratches and the effect of stabilizing the substrate potential can be obtained.

  The same applies to a solid-state imaging device having three or more transfer gates for one photodiode, such as a progress-type solid-state imaging device.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. In the second embodiment, in addition to the drive timing in the first embodiment, or separately from the drive timing in the first embodiment, the charge is read out to the vertical CCD at a new drive timing. In other words, if the solid-state imaging device can read out the charges accumulated in all the photodiodes to the vertical CCD by N reading operations, it can be transferred at the start of the transfer operation of one field or one frame. As a “connecting operation”, each of the 2N gates is sequentially switched from the state in which the 2N gates are LOW voltage to the continuous 2N gates including N read gates and N non-read gates (that is, A drive pulse is applied to shift to the MIDDLE voltage state (shifting the timing).

  That is, in the present embodiment, a function of performing a connection operation during the connection period is added to the solid-state imaging device and camera described in Embodiment 1. Here, the connection period refers to the period from the completion of field transfer to the start of field transfer or the start of the first field transfer. In the connection period, the vertical CCD is in a standby state, and all of the drive pulses φV1 to φV6 are conventionally at a low level. However, in this embodiment, all the drive pulses φV1 to φV6 are immediately before the start of transfer. The LOW voltage state is changed to the MIDDLE voltage state in order.

  The configuration of the camera and the solid-state imaging device in the present embodiment is the same as that shown in FIGS. 16 and 17, except that a function for performing the above-described connecting operation is added. Hereinafter, the description of the same points will be omitted, and different points will be mainly described.

  FIG. 11 is a diagram showing an operation sequence from the long second accumulation mode to a plurality of field transfers.

  The figure shows the timing of the vertical synchronization signal VD, CCD drive mode, and drive pulse. The vertical synchronization signal VD corresponds to a connection period between various CCD drive modes. In the figure, the CCD drive mode returns to the monitor mode after the monitor mode, after the long second accumulation mode, the still mode (dummy field), and the still mode (1st field to 3rd field). The CCD output data outputs an image signal corresponding to the CCD driving mode such as thinning out output or frame output.

  Here, a period α in the figure represents a connection period at the start of the first field transfer among the connection periods. The period β represents the timing of the connection operation executed within the connection period α. In FIG. 11, the first field is a dummy field, but the present invention does not necessarily require transfer of such a dummy field.

  FIG. 12 is a sequence diagram showing details of drive timing in the connection period α in FIG. This figure shows the timing of the substrate bias voltage SUB applied to the horizontal synchronization signal HD, the V system indicating the driving pulses of φV1 to φV6, the mechanical shutter, and the semiconductor substrate.

  In this figure, the horizontal synchronization signal HD shows the timing after the first horizontal synchronization pulse in the field transfer. As shown in the V-system timing in this figure, the period β in FIG. 11 corresponds to the first horizontal synchronization pulse period. In the present embodiment, the connecting operation is executed during this period. As can be seen from this figure, in this embodiment, the connecting operation is performed (a) at the start of the first field transfer, or (b) at the start of the high-speed transfer of the vertical CCD. As a result, the reverse injection of unnecessary charges is suppressed before the vertical transfer is started, and the occurrence of white scratches is avoided.

  As can be seen from the timing of the mechanical shutter and the substrate bias voltage SUB in this drawing, the first substrate bias modulation is performed during the exposure period, and the second substrate bias modulation is performed after the end of the exposure period and after the joining operation. Made.

  FIG. 13 is a diagram showing V-system operation timing (that is, details of the connecting operation) executed in the vicinity of the period β shown in FIG. In the figure, the timing of φSUB is also shown. Here, “T” is the period of the horizontal drive clock.

  As can be seen from this figure, in the connecting operation, the drive pulses applied to the read gate and the non-read gate are shifted from the LOW voltage state to the MIDDLE voltage state by sequentially shifting the timing. As a result, a pulse whose voltage state changes at different timings is applied to each gate, and unnecessary charges are diffused to prevent the occurrence of charge injection from the semiconductor substrate. Therefore, white scratches due to charges generated during hole movement can be prevented.

  FIG. 14 is a time chart showing the detailed timing of the substrate bias modulation. This figure shows the SUB waveform indicating the substrate bias voltage (Vsub in FIG. 17) applied to the semiconductor substrate, the SUB modulation timing indicating the VsubCont signal in FIG. 17, the operation timing of the mechanical shutter, and the opening / closing timing of the mechanical shutter. .

  In the figure, the period from time t3 to t5 in the SUB waveform indicates the first bias modulation, and the period from t6 to the beginning of the period t8 indicates the second bias modulation. The first bias modulation changes the overflow barrier to a high level before the end of the exposure period and accumulates signal charges up to the barrier height of the read gate. This increases the linearity of the saturation signal charge amount of the photodiode. The second bias modulation changes the height of the overflow barrier low after the exposure period ends and before the vertical CCD transfer starts.

  As described above, in the present embodiment, the first bias modulation for changing the overflow barrier to a high level before the end of the exposure period and accumulating the signal charges up to the barrier height of the readout gate, and after the end of the exposure period and in the vertical direction. The second bias modulation is performed to change the height of the overflow barrier to a low level before discharging the CCD charge. This prevents signal charges from the photodiode from spilling into the vertical CCD (blooming).

  As shown in FIG. 14, the P-type well region 91 of the semiconductor substrate can be stabilized by performing the connecting operation before the second bias modulation.

  FIG. 15 is a diagram illustrating the transfer step time dependency of the injection suppression SUB. Here, “injection suppression SUB (V)” indicating the vertical axis is a voltage (V) for suppressing reverse injection of unnecessary charges from the semiconductor substrate to the photodiode. That is, the vertical axis represents a voltage necessary for suppressing the generation of unnecessary charges, and the lower the voltage, the less unnecessary charges are generated (good characteristics). The “transfer step time” on the horizontal axis indicates the time difference (rise time difference) between the rise timings of the drive pulses applied to the read gate and the non-read gate in the “connection operation”. Here, the horizontal drive It is shown as a multiple of the clock period (T: for example, 31.75 ns). In the drawing, the horizontal axis placed at the position of the injection suppression SUB of about 2.7 V is one voltage reference level indicating that the generation of unnecessary charges is small.

  As can be seen from this figure, in order to suppress the generation of unnecessary charges below the voltage reference level, it is preferable to use a “connection operation” having a transfer step time longer than a certain transfer step time. In other words, all the drive pulses applied to the read gate and the non-read gate are not required by starting with a time interval greater than a certain reference time when all of the drive pulses are sequentially raised from the LOW voltage state to the MIDDLE voltage state. Generation of small charges can be suppressed below a certain standard.

  For example, in FIG. 14, the transfer step of the normal operation is 30T, but it can be seen that the transfer step time is longer than this in the connection operation.

  Note that the relationship between the transfer step time shown in this embodiment and the voltage for suppressing the generation of unnecessary charges varies depending on the size of the device and the diffusion process conditions. Although not limited to all, as the transfer step time becomes longer, the P-type well region 91 of the semiconductor substrate acts in a more stable direction, and the voltage that suppresses the generation of unnecessary charges tends to decrease. Is the same.

  In the present embodiment, the same applies to a solid-state imaging device having three or more transfer gates for one photodiode, such as a progress-type solid-state imaging device.

  The solid-state imaging device of the present invention can be applied to high-quality digital cameras, video cameras, and the like.

It is a figure which shows the structure of the camera using the solid-state imaging device which concerns on this Embodiment. It is a block diagram which shows the structure of the solid-state image sensor 40 shown by FIG. 2 is a cross-sectional view showing a structure in the substrate depth direction around a photodiode 41 and a vertical CCD 43. FIG. 6 is a diagram showing a potential distribution of a photodiode 41 in a substrate depth direction. FIG. It is a figure which shows the general timing at the time of a long-seconds accumulation mode. It is a figure which compares the difference between white scratch fields by comparing a general timing with the timing according to the present application. It is a figure which compares the difference between white scratch fields by comparing a general timing with the timing according to the present application. It is a figure which shows the relationship between the timing which shows the difference drive dependence between white flaw fields, and the number of flaws. It is a figure which shows the relationship between the timing which shows the difference drive dependence between white flaw fields, and the number of flaws. It is a figure which shows the dependence of the position of the first change point of V8 in 8-phase drive. It is a figure which shows the operation | movement sequence until it performs field transfer of multiple times from long-seconds accumulation mode. Details in the connection period α in FIG. 11 are sequence diagrams showing drive timing. It is a figure which shows the V-system operation | movement timing performed in the period (beta) vicinity shown by FIG. It is a time chart which shows the detailed timing of a substrate bias modulation. It is a figure which shows the transfer step time dependence of injection | pouring suppression SUB. It is the figure which expanded and showed the one part area | region of FITCCD. It is a voltage waveform diagram for demonstrating the conventional drive method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Camera 30 Solid-state imaging device 40 Solid-state image sensor 41 Photodiode 42 Read-out gate part 43 Vertical CCD
45 Horizontal CCD
46 Output Amplifier 47 Semiconductor Substrate 49 Storage Unit 50 Drive Pulse Control Unit 60 Signal Processing Unit

Claims (11)

A semiconductor substrate; a plurality of photodiodes formed two-dimensionally on the semiconductor substrate; and a readout gate for reading out the accumulated charge and a non-readout gate that does not read out the charge for each of the photodiodes. A solid-state imaging device having vertical CCDs formed by being arranged one by one;
Drive pulse control means for controlling the solid-state imaging device by applying a drive pulse at a predetermined timing to each of the read gate and the non-read gate;
The drive pulse control means includes
A driving pulse for changing from a standby LOW voltage state to a MIDDLE voltage state is sequentially applied to each of the read gates,
Applying a drive pulse that maintains a LOW voltage state to at least one of the non-read gates adjacent to the last read gate in the order of change, from the beginning to the end in the order of change. A solid-state imaging device. At least a semiconductor substrate, a plurality of photodiodes formed two-dimensionally on the semiconductor substrate, and a read gate for reading the accumulated charge and a non-read gate that does not read the charge for each of the photodiodes A solid-state imaging device having vertical CCDs formed by being arranged one by one;
Drive pulse control means for controlling the solid-state imaging device by applying a drive pulse at a predetermined timing to each of the read gate and the non-read gate;
The solid-state imaging device can read out the charges accumulated in all the photodiodes by N reading operations to the vertical CCD,
The drive pulse control means includes
A drive pulse for changing from a standby LOW voltage state to a MIDDLE voltage state is sequentially applied to N read gates,
For at least one of the N−1th and Nth read gates adjacent to any of the N−1th read gates in the order of change, between N−1th to Nth in the order of change, A solid-state imaging device characterized by applying a driving pulse for setting a LOW voltage state. At least a semiconductor substrate, a plurality of photodiodes formed two-dimensionally on the semiconductor substrate, and a read gate for reading the accumulated charge and a non-read gate that does not read the charge for each of the photodiodes A solid-state imaging device having vertical CCDs formed by being arranged one by one;
Drive pulse control means for controlling the solid-state imaging device by applying a drive pulse at a predetermined timing to each of the read gate and the non-read gate;
The drive pulse control means includes
A drive pulse for simultaneously changing from a standby LOW voltage state to a MIDDLE voltage state is applied to each of the readout gates. The drive pulse control means further changes, for each of the non-read gates, the drive pulse for the read gate from the standby LOW voltage state to the MIDDLE voltage state, and simultaneously changes from the MIDDLE voltage state to the LOW voltage state. The solid-state imaging device according to claim 3, wherein a driving pulse is applied. The solid-state imaging device can read out the charges accumulated in all the photodiodes by N reading operations to the vertical CCD,
The drive pulse control means further includes
At the start of the transfer operation of one field or one frame, as a connecting operation for connection to the transfer, all of the gates are LOW with respect to consecutive gates composed of N read gates and at least N non-read gates. The solid-state imaging device according to any one of claims 1 to 3, wherein a driving pulse for changing each gate to a MIDDLE voltage state in order from a voltage state is applied. 6. The solid-state imaging device according to claim 5, wherein the drive pulse control means performs the connecting operation at (a) at the start of the first field transfer or (b) at the start of high-speed transfer of the vertical CCD. The drive pulse control means further includes a first bias modulation that changes the overflow barrier to a high level before the end of the exposure period and accumulates signal charges up to the barrier height of the readout gate, and after the end of the exposure period and the vertical CCD. Performing the second bias modulation to change the height of the overflow barrier to a low level before discharging the charge,
The solid-state imaging device according to claim 5, wherein the connecting operation is performed after the exposure period and before the second bias modulation. At least a semiconductor substrate, a plurality of photodiodes formed two-dimensionally on the semiconductor substrate, and a read gate for reading the accumulated charge and a non-read gate that does not read the charge for each of the photodiodes A solid-state imaging device having vertical CCDs formed by being arranged one by one;
Drive pulse control means for controlling the solid-state imaging device by applying a drive pulse at a predetermined timing to each of the read gate and the non-read gate;
The solid-state imaging device can read out the charges accumulated in all the photodiodes by N reading operations to the vertical CCD,
The drive pulse control means further includes
At the start of the transfer operation of one field or one frame, as a connecting operation for connection to the transfer, all of the gates are LOW with respect to consecutive gates composed of N read gates and at least N non-read gates. A solid-state imaging device characterized by applying a driving pulse for changing each gate from a voltage state to a MIDDLE voltage state in order. A semiconductor substrate, and a plurality of photodiodes formed two-dimensionally on the semiconductor substrate;
A solid-state imaging device having a vertical CCD formed by disposing at least one readout gate for reading out accumulated charges and a non-readout gate for not reading out charges for each of the photodiodes; A driving method in a solid-state imaging device, comprising driving pulse control means for controlling the solid-state imaging device by applying a driving pulse to each of the reading gate and the non-reading gate at a predetermined timing,
A long-second accumulation mode in which electric charges are accumulated in each of the photodiodes for two or more vertical periods;
Including a driving step of reading out the charges accumulated in the long-second accumulation mode from each of the photodiodes to the vertical CCD, vertically transferring the charges, and outputting the charges.
4. The solid-state imaging device driving method according to claim 1, wherein the driving of either one of claim 1 and claim 3 is performed in the long-second accumulation mode. At least a semiconductor substrate, a plurality of photodiodes formed two-dimensionally on the semiconductor substrate, and a read gate for reading the accumulated charge and a non-read gate that does not read the charge for each of the photodiodes Control the solid-state imaging device by applying a driving pulse at a predetermined timing to each of the readout gate and the non-reading gate, and a solid-state imaging device having a vertical CCD formed by arranging one by one A driving method in a solid-state imaging device comprising driving pulse control means for
A long-second accumulation mode in which electric charges are accumulated in each of the photodiodes for two or more vertical periods;
A vertical CCD sweep mode in which only the vertical CCD is driven to transfer before reading out the electric charge accumulated in the long-second accumulation mode;
Including a driving step of reading out the charges accumulated in the long-second accumulation mode from each of the photodiodes to the vertical CCD, vertically transferring the charges, and outputting the charges.
4. The solid-state imaging device driving method according to claim 1, wherein the driving of either one of claim 1 and claim 3 is performed in the long-second accumulation mode.   A camera provided with the solid-state imaging device according to claim 1.

Images