JP2007214363A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can solve a problem by an insufficient adhesive force with a bonding wire or with cracking generation even if a probe needle of a measuring device is erected on a pad electrode to measure an electronic circuit or the like, and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: In the semiconductor device externally connected to a pad electrode by wire bonding, the pad electrode is formed on a substrate having an electronic circuit formed thereon, a protective film covering the substrate and having an opening to expose the pad electrode is formed on the substrate, and a metallic layer is formed on the upper layer of the pad electrode in the opening of the protective film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device used by being connected to a mounting substrate by wire bonding and a manufacturing method thereof.

  A wire bonding method is widely used as a connection method for transmitting signals between an integrated circuit formed on a silicon substrate in a semiconductor and the outside.

  By the way, the semiconductor device is cut out into individual chips, packaged and shipped as a product, but before that, measurement and evaluation are performed for operation confirmation, characteristic confirmation or selection in a wafer state.

For example, as shown in FIG. 8A, a pad electrode made of aluminum or the like laminated with a barrier metal 111 on a semiconductor substrate 110 on which an electronic circuit (not shown) is formed so as to be connected to the electronic circuit. 112 is formed.
The surface of the semiconductor substrate 110 is covered with a protective film 113, and an opening 113a through which the pad electrode 112 is exposed is formed in the protective film.
A measurement (not shown) is performed on the pad electrode 112 connected to the electronic circuit in order to perform measurement and evaluation for operation confirmation, characteristic confirmation or selection of the electronic circuit with respect to the semiconductor device having the above-described configuration. The probe needle 120 connected to the apparatus is raised and electrically connected to establish electrical continuity with the measuring apparatus.

  At this time, in order to ensure contact between the pad electrode 112 and the probe needle 120, an appropriate load is applied to the probe needle, but the load may cause a horizontal displacement in the contact position of the probe needle 120. In this case, as a result, irregularities 112a are formed on the surface of the pad electrode 112, or burrs are generated.

  When the tip of the wire 122 is bonded to the surface of the pad electrode 112 as shown in FIG. 8B with the irregularities 112a and burrs generated on the pad electrode 112 as described above, the aluminum film constituting the pad electrode 112 is formed. FIG. 8C shows a connection state between the pad electrode 112 and the bonding wire 122 due to insufficient elasticity due to insufficient film thickness, cracks in the lower interlayer insulating film, and the like. As shown in the figure, a void V is generated between the two, resulting in insufficient interdiffusion between the aluminum phase of the pad electrode and the gold phase of the bonding wire 122, resulting in bonding failure.

  As described above, when wire bonding connection is performed after the probe needle is raised on the aluminum pad electrode and the operation of the electronic circuit is confirmed by the conventional method, the pad electrode made of aluminum is bonded at the time of bonding by the burr. Problems such as insufficient adhesion, insufficient adhesion due to insufficient interdiffusion of the aluminum / gold phase due to thinning of the aluminum film, and cracks in the lower interlayer film due to insufficient elasticity due to thinning of the aluminum film may occur.

As a countermeasure, Patent Document 1 discloses a method of removing a deformed layer after measurement using a pad as a laminated structure.
In Patent Document 1, it is possible to achieve stable bonding by removing the damaged layer after measurement and taking out a smooth surface on the premise that wrinkles or the like occur. Thinning may occur, and the thickness of the aluminum film needs to be several hundreds nm or more for both bonding and needle stand, leading to an increase in manufacturing cost.
Japanese Patent Laid-Open No. 2004-296643

  An object of the present invention is to provide a semiconductor device capable of suppressing the problem of insufficient adhesion to a bonding wire and the occurrence of cracks even when a probe needle of a measuring device is provided on a pad electrode for measuring an electronic circuit, etc. It is to provide a manufacturing method.

  In order to solve the above problems, a semiconductor device according to the present invention is a semiconductor device having a pad electrode and connected to the outside by wire bonding at the pad electrode, and a substrate on which an electronic circuit is formed, and the substrate The pad electrode formed on the substrate, a protective film formed to cover the substrate and having an opening exposing the pad electrode, and an upper layer of the pad electrode in the opening of the protective film. And a metal layer.

  The semiconductor device of the present invention described above is a semiconductor device connected to the outside by wire bonding at the pad electrode, wherein the pad electrode is formed on the substrate on which the electronic circuit is formed, and the pad electrode is covered with the substrate. A protective film having an exposed opening is formed, and a metal layer is formed over the pad electrode in the opening of the protective film.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a pad electrode and connected to the outside by wire bonding at the pad electrode, Forming the pad electrode on the formed substrate; forming the protective film having an opening that covers the substrate and exposing the pad electrode; and the pad electrode in the opening of the protective film. Forming a metal-containing resin layer on the upper layer, and firing the metal-containing resin layer to form a metal layer.

  The above-described method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device connected to the outside by wire bonding at a pad electrode. First, a pad electrode is formed on a substrate on which an electronic circuit is formed. Next, a protective film having an opening exposing the pad electrode is formed by covering the substrate. Next, a metal-containing resin layer is formed on the pad electrode in the opening of the protective film, and baked to form a metal layer.

  In the semiconductor device of the present invention, the metal layer is provided on the upper layer of the pad electrode. Even if the probe needle of the measuring device is raised on the pad electrode for measuring an electronic circuit, the unevenness generated in the pad electrode Is repaired by the metal layer, and the problem of insufficient adhesion to the bonding wire and the occurrence of cracks can be suppressed.

  In the method of manufacturing a semiconductor device according to the present invention, even if the probe needle of the measuring device is placed on the pad electrode for measuring an electronic circuit, the unevenness generated in the metal layer is repaired by the metal layer, and the bonding wire It is possible to easily manufacture a semiconductor device capable of suppressing the problem of insufficient adhesion and cracking.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a schematic cross-sectional view of a semiconductor device according to this embodiment.
For example, a pad electrode 12 is formed on a semiconductor substrate 10 on which an electronic circuit (not shown) is formed and laminated with a barrier metal 11 so as to be connected to the electronic circuit.
The surface of the semiconductor substrate 10 is covered with a protective film 13, and an opening 13a through which the pad electrode 12 is exposed is formed in the protective film.
Further, a metal layer 14 is formed on the pad electrode 12 in the opening 13 a of the protective film 13.

For example, the metal layer 14 is a gold layer or a gold alloy layer, and the pad electrode 12 is an aluminum layer or an aluminum alloy layer.
Usually, at this stage, a probe needle is applied to check the operation of the electronic circuit, and irregularities occur in the pad electrode.

For example, the alloy layer 15 is formed by interdiffusion of aluminum, which is an element constituting the pad electrode 12, and gold, which is an element which constitutes the metal layer 14, at the interface between the pad electrode 12 and the metal layer 14. Yes.
Here, the surface of the pad electrode 12 had irregularities and burrs due to the probe needle being applied to confirm the operation of the electronic circuit, but the metal layer 14 was formed on the upper layer of the pad electrode 12. The surface is flattened.

The semiconductor device of the present embodiment includes the pad electrode 12 and is used by being connected to the outside via the wire 22 by wire bonding in the pad electrode 12.
Since it is flattened by the metal layer 14 as described above, a void is formed in the wire bonding as in the conventional example even when the probe needle of the measuring device is placed on the pad electrode for measurement of an electronic circuit or the like. In this case, high adhesion to the wire 22 can be ensured and the elasticity can be increased, so that the problem of crack generation during wire bonding can be suppressed.

A method for manufacturing the semiconductor device of the present embodiment will be described.
First, as shown in FIG. 2 (a), for example, a semiconductor substrate 10 in a wafer state on which an electronic circuit (not shown) is formed is laminated with a barrier metal 11 so as to be connected to the above-described electronic circuit. The pad electrode 12 made of, for example, is formed.
Next, for example, the protective film 13 is formed on the surface of the semiconductor substrate 10, and the opening 13a exposing the pad electrode 12 portion is formed.

  Next, for example, in order to perform measurement and evaluation for operation confirmation, characteristic confirmation or selection of the electronic circuit on the wafer-state semiconductor device having the above-described configuration, the pad electrode 12 connected to the electronic circuit is applied to the pad electrode 12 connected to the electronic circuit. Then, the probe needle 20 connected to a measurement device (not shown) is raised and electrically connected to establish electrical continuity with the measurement device.

  At this time, in order to ensure contact between the pad electrode 12 and the probe needle 20, an appropriate load is applied to the probe needle, and the load may cause a horizontal displacement in the contact position of the probe needle 20. In this case, as a result, irregularities 12a are formed on the surface of the pad electrode 12, or burrs are generated.

  Next, as shown in FIG. 2B, for example, a resin (gold-containing resin) containing gold nanoparticles or other metal-containing resin is applied onto the pad electrode 12 by an inkjet method or supplied from the dispenser 21; A metal-containing resin layer 14p such as a gold-containing resin is formed.

As the gold-containing resin containing the above gold nanoparticles, the particle size of the nanoparticles is, for example, 5 to 10 nm, the resin composition is mainly composed of a thermosetting resin, the solvent contains a nonpolar solvent, and the viscosity is, for example, 100 cp. That's it.
Said metal containing resin can be baked at the temperature of 150-200 degreeC, for example. If necessary, baking is performed at 150 to 250 ° C. In addition to a metal-containing resin containing gold nanoparticles, a metal-containing resin containing silver nanoparticles can be used.
For example, the NP series of Harima Chemicals Co., Ltd. can be used.

In the above, for example, the depth in the opening 13a of the protective film 13 is about 1 μm, and it is necessary to form the metal-containing resin so as not to overflow from the opening 13a. The thickness is about 1 μm or less.
In addition, for example, a metal layer is formed from the metal-containing resin layer 14p in the next step, but a certain thickness is required as the metal layer in order to flatten the unevenness of the pad electrode surface as described above and ensure elasticity. In consideration of these, it is preferable to supply and apply 0.1 to 10 pL of resin per pad, although it depends on the opening area of the pad.

Next, as illustrated in FIG. 2C, for example, organic components such as a solvent are removed by heat treatment, and the metal-containing resin layer 14 p is baked to form the metal layer 14. Here, for example, baking is performed at a temperature of 150 to 250 ° C.
For example, in the above baking step, the elements constituting the pad electrode 12 and the metal layer 14 are formed at the interface between the pad electrode 12 and the metal layer 14 by mutual diffusion of the elements constituting the pad electrode 12 and the elements constituting the metal layer 14. An alloy layer 15 of the elements constituting is formed. Thereby, the adhesion strength between the pad electrode 12 and the metal layer 14 can be ensured.
By forming the metal layer 14 on the pad electrode 12 in this way, it is possible to flatten the irregularities on the surface of the pad electrode, and it is possible to secure a film thickness of 1 μm or more between the pad electrode and the metal layer. It is possible to ensure the elasticity required at times.

For example, it is preferable to form a gold layer or a gold alloy layer as the metal layer 14.
Further, it is preferable to form an aluminum layer or an aluminum alloy layer as the pad electrode 12.

In the above baking process, in order to achieve a sufficiently low resistance of the metal layer, for example, to cause a necessary and sufficient reaction between gold and aluminum, first heat treatment: 130 to 150 ° C., 60 minutes, second heat treatment: 180 It is preferable to perform the treatment at ˜200 ° C. for 30 to 60 minutes.
Further, in order to suppress defects due to the subsequent heat history and increase the reliability, a barrier metal can be formed at the interface in order to suppress alloying of the pad electrode and the gold of the metal layer. For example, TiN, TaN, Ti, Ta, W, CoWP, etc. can be used. As an adverse effect of alloying suppression, there is an increase in resistance. As a countermeasure, it is more preferable to perform the second heat treatment at 200 to 250 ° C. for 30 to 60 minutes.

  In the semiconductor device manufacturing method of the present embodiment, the pad electrode 12 is flattened by the metal layer 14, so that even if the probe needle of the measuring device is placed on the pad electrode for measurement of an electronic circuit, No void is formed at the time of wire bonding as in the conventional example, high adhesion to the wire 22 can be secured, and the elasticity can be increased, so that the problem of crack generation at the time of wire bonding can be suppressed.

Second Embodiment FIG. 3 is a sectional view of a semiconductor device according to this embodiment.
For example, a first insulating layer 30 such as silicon oxide is formed on a semiconductor substrate on which an electronic circuit such as a transistor (not shown) is formed, and a wiring groove or the like is formed in the first insulating layer 30. Two wirings 32 are embedded and formed.
A second insulating layer 33 such as silicon nitride and a third insulating layer 34 such as silicon oxide are formed on the first insulating layer 30.
A contact hole 34 a is formed in the second insulating layer 33 and the third insulating layer 34, and the barrier metal 35 is formed so as to cover the inside of the contact hole 34 a and connect to the electronic circuit via the first wiring 31. As a result, a conductive layer 36 in which the contact plug and the pad electrode are integrated is formed.
The surface of the third insulating layer 34 is covered with a protective film 37, and the protective film 37 has an opening 37 a that exposes the conductive layer 36 that becomes a pad electrode.
Further, a metal layer 38 is formed in an upper layer of the conductive layer 36 serving as a pad electrode in the opening 37 a of the protective film 37.

  For example, the metal layer 38 is a gold layer or a gold alloy layer, and the conductive layer 36 serving as a pad electrode is an aluminum layer or an aluminum alloy layer.

Further, for example, aluminum, which is an element constituting the conductive layer 36 serving as the pad electrode, and gold, which is an element constituting the metal layer 14, diffuse to each other at the interface between the conductive layer 36 serving as the pad electrode and the metal layer 38. Thus, an alloy layer 39 is formed.
Here, the surface of the conductive layer 36 that becomes the pad electrode had irregularities and burrs due to the probe needles being applied to check the operation of the electronic circuit, but the upper layer of the conductive layer 36 that became the pad electrode. Since the metal layer 38 is formed on the surface, the surface is flattened.

The semiconductor device according to the present embodiment includes the conductive layer 36 serving as a pad electrode, and is used by being connected to the outside via a wire 42 by wire bonding in the pad electrode.
Since it is flattened by the metal layer 38 as described above, even if the probe needle of the measuring device is placed on the pad electrode for measurement of an electronic circuit, a void is formed in the wire bonding as in the conventional example. In this case, high adhesion to the wire 42 can be ensured and the elasticity can be increased, so that the problem of crack generation during wire bonding can be suppressed.

A method for manufacturing the semiconductor device of the present embodiment will be described.
First, as shown in FIG. 4A, for example, a first insulating layer 30 is formed on a semiconductor substrate in a wafer state on which an electronic circuit (not shown) is formed, and the first insulating layer 30 is first processed by a damascene wiring process. The wiring 31 and the second wiring 32 are formed to be embedded, and a second insulating layer 33 and a third insulating layer 34 for the purpose of Cu barrier are sequentially deposited thereon.
Next, for example, a resist film is patterned by a photolithography method, an etching process such as RIE (reactive ion etching) is performed to form a contact hole 34a for pad electrode connection, and the barrier metal 35 is formed by a sputtering method or the like. A conductive layer such as aluminum is formed by stacking, and patterning is performed to form a conductive layer 36 to be a pad electrode.
Next, a protective film 37 is formed over the third insulating layer 34, a resist film is patterned by photolithography, and an etching process such as RIE is performed to form an opening 37a that exposes the pad electrode portion.

Next, as shown in FIG. 4 (b), in order to perform measurement and evaluation for the operation check, characteristic check or selection of the electronic circuit on the semiconductor device in the wafer state having the above configuration, A probe needle 40 connected to a measuring device (not shown) is electrically connected to the conductive layer 36 serving as the connected pad electrode, and is electrically connected to the measuring device.
At this time, irregularities 36a are generated on the surface of the conductive layer 36 to be a pad electrode, or burrs are generated.

  Next, as shown in FIG. 5A, for example, a resin (gold-containing resin) containing gold nanoparticles or other metal-containing resin is applied onto the conductive layer 36 to be a pad electrode by an inkjet method or a dispenser 41. And a metal-containing resin layer 38p such as a gold-containing resin is formed.

Next, as shown in FIG. 5B, for example, organic components such as a solvent are removed by heat treatment, and the metal-containing resin layer 38p is baked to form the metal layer 38. Here, for example, baking is performed at a temperature of 150 to 250 ° C.
In the above firing step, an alloy layer 39 is formed at the interface between the conductive layer 36 serving as the pad electrode and the metal layer 38 by mutual diffusion of the elements configuring the conductive layer 36 serving as the pad electrode and the element configuring the metal layer 38. To do. Thereby, the adhesion strength between the conductive layer 36 to be the pad electrode and the metal layer 38 can be secured.
By forming the metal layer 38 on the conductive layer 36 to be the pad electrode in this manner, the unevenness of the pad electrode surface can be flattened, and a film thickness of 1 μm or more is secured between the pad electrode and the metal layer. This makes it possible to ensure the elasticity required for wire bonding.

  In the semiconductor device manufacturing method of the present embodiment described above, the conductive layer 36 that becomes the pad electrode is flattened by the metal layer 38. Therefore, the probe needle of the measuring device is placed on the pad electrode for measurement of an electronic circuit or the like. Even when the wire bonding is performed, no voids are formed as in the conventional example at the time of wire bonding, and high adhesion to the wire 42 can be secured and the elasticity can be increased, so that the problem of cracking at the time of wire bonding can be suppressed. .

Third Embodiment FIG. 6 is a sectional view of a semiconductor device according to this embodiment.
For example, a first insulating layer 30 such as silicon oxide is formed on a semiconductor substrate on which an electronic circuit such as a transistor (not shown) is formed, and a wiring groove or the like is formed in the first insulating layer 30, for example, copper or copper alloy The first wiring 31 and the second wiring 32 made of are embedded and formed.
A barrier metal 35 made of CoWP or the like for preventing copper diffusion is formed on the surfaces of the first wiring 31 and the second wiring 32.
A second insulating layer 33 such as silicon nitride and a third insulating layer 34 such as silicon oxide are formed on the first insulating layer 30.
Here, the first wiring 31 corresponds to a pad electrode, and the third insulating layer corresponds to a protective film.

The third insulating layer 34 is formed with an opening 34a that exposes the first wiring 31 serving as a pad electrode.
Further, a metal layer 38 is formed in an upper layer of the first wiring 31 serving as a pad electrode in the opening 34 a of the third insulating layer 34.
For example, the metal layer 38 is a gold layer or a gold alloy layer.

  Here, when the probe needle is applied to the surface of the first wiring 31 that becomes the pad electrode for confirming the operation of the electronic circuit, irregularities and burrs are generated, but the first wiring 31 that becomes the pad electrode. Since the metal layer 38 is formed on the upper layer, the surface is flattened.

The semiconductor device according to the present embodiment includes the first wiring 31 serving as the pad electrode, and is used by being connected to the outside via the wire 42 by wire bonding at the pad electrode.
Since it is flattened by the metal layer 38 as described above, even if the probe needle of the measuring device is placed on the pad electrode for measurement of an electronic circuit, a void is formed in the wire bonding as in the conventional example. In this case, high adhesion to the wire 42 can be ensured and the elasticity can be increased, so that the problem of crack generation during wire bonding can be suppressed.

A method for manufacturing the semiconductor device of the present embodiment will be described.
First, as shown in FIG. 7A, for example, a first insulating layer 30 is formed on a semiconductor substrate in a wafer state on which an electronic circuit (not shown) is formed, and copper or the like is formed on the first insulating layer 30 by a damascene wiring process. The first wiring 31 and the second wiring 32 made of are embedded and formed, and a barrier metal 35 such as CoWP for the purpose of Cu barrier is formed thereon.
Next, for example, a second insulating layer 33 and a third insulating layer 34 are sequentially deposited on the first insulating layer 30, a resist film is formed by photolithography, and etching such as RIE (reactive ion etching) is performed. Processing is performed to form an opening 34a that exposes the first wiring 31 to be a pad electrode.

  Next, in order to perform measurement and evaluation for operation confirmation, characteristic confirmation or selection of the electronic circuit for the semiconductor device in a wafer state having the above-described configuration, a first electrode that becomes a pad electrode connected to the electronic circuit is provided. A probe needle connected to a measurement device (not shown) is connected to the wiring 31 and electrically connected to establish electrical continuity with the measurement device.

  Next, as shown in FIG. 7B, for example, a resin containing gold nanoparticles (gold-containing material) is formed on the upper layer of the first wiring 31 serving as a pad electrode in the opening 34a via a barrier metal 35. Resin) or other metal-containing resin is applied by an inkjet method or supplied from a dispenser to form a metal-containing resin layer 38p such as a gold-containing resin.

Next, as shown in FIG. 7C, organic components such as a solvent are removed by heat treatment, for example, and the metal-containing resin layer 38p is baked to form the metal layer 38. Here, for example, baking is performed at a temperature of 150 to 250 ° C.
Thus, by forming the metal layer 38 on the first wiring 31 that becomes the pad electrode, it is possible to flatten the irregularities on the surface of the pad electrode, and the pad electrode and the metal layer have a film thickness of 1 μm or more. The elasticity required for wire bonding can be ensured.

  In the semiconductor device manufacturing method of the present embodiment described above, the first wiring 31 that becomes the pad electrode is flattened by the metal layer 38, so that the probe needle of the measuring device is held on the pad electrode for measurement of an electronic circuit or the like. Even if it is performed, no voids are formed during wire bonding, high adhesion to the wire 42 can be ensured, and elasticity can be increased, so the problem of cracking during wire bonding is suppressed. it can.

According to each of the above-described embodiments, it is possible to form a good wire bonding to a pad that has been bent or scraped by performing a probe stand.
In addition, contact defects caused by void formation due to excessive progress of interdiffusion between gold and aluminum, which has been a problem in reliability in the past, can now be performed sufficiently because it is possible to carry out sufficient interdiffusion before bonding. The possibility is reduced.
In addition, the elasticity of the pad portion required in wire bonding was not sufficient to have a single layer of wiring on the silicon substrate, but by applying the method of the present invention, the metal layer on the pad electrode A sufficient film thickness can be secured, and bonding is possible even when one layer of wiring is provided on the silicon substrate.
Further, the thickness of the aluminum film before bonding can be reduced, so that the aluminum layer constituting the pad electrode can be reduced, and the etching process window can be expanded when the pad electrode is exposed or the fuse window is opened.

The present invention is not limited to the above description.
Although the embodiments have been described above, the wiring forming method, the interlayer film forming method, the wiring metal species, and the interlayer film types are not limited to the above in the present invention.
For example, as a wiring forming method, a dual damascene method in which a contact layer and a wiring layer are continuously formed may be used instead of a normal damascene method.
When aluminum tungsten is used as the metal element constituting the wiring, it can be formed by performing normal photolithography and plasma etching.
As for the method for forming the insulating film between layers, in addition to the CVD method, application and baking treatment by spin coating method or printing and baking treatment may be used.
The metal element constituting the wiring may be mainly copper, an alloy of copper and another metal, or aluminum, tungsten, silver, gold, or platinum as described above.
As the barrier metal layer, in addition to tantalum, titanium, molybdenum or the like, or a nitride film or an oxide film thereof may be used.
As an insulating film between layers, silicon nitride can be used for the lower layer portion of the wiring, a low dielectric constant SiOC film can be further formed thereon, and a silicon oxide film can be further formed thereon. There is a purpose of polishing. For example, SiC or SiNC can be used instead of silicon nitride. Instead of SiOC, Methylsilsesquioxane (MSQ), Hydrogensilsesquioxane (HSQ), porous film, SiOF film, low dielectric constant organic film may be used, and SiOF film may be used instead of silicon oxide film.
In the above example, one layer is exemplified as the wiring, but two or more layers may be used.
The silicon substrate may be a P-type, N-type, or SOI (Silicon on Insulator) substrate.
Although the photolithography method is used as the patterning formation method, an electron beam or an X-ray may be used. In addition to the plasma etching method, wet etching using a chemical solution, plasma etching, or wet etching using a chemical solution may be used.
Although the example of aluminum was given as an example of the metal of the pad electrode according to the present invention, aluminum alloy may be used in addition to aluminum.
The gold-containing resin layer may be formed by a dispensing method instead of the ink jet method.
The metal layer may be silver or copper instead of gold.
In addition, various modifications can be made without departing from the scope of the present invention.

The semiconductor device of the present invention can be applied to a semiconductor device connected to the outside by wire bonding.
The method for manufacturing a semiconductor device of the present invention can be applied to a method for manufacturing a semiconductor device connected to the outside by wire bonding.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention. FIG. 2A to FIG. 2C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 4A and FIG. 4B are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the second embodiment of the present invention. FIG. 5A and FIG. 5B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 7A to FIG. 7C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 8A to FIG. 8C are cross-sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to a conventional example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Barrier metal, 12 ... Pad electrode, 12a ... Concavity and convexity, 13 ... Protective film, 13a ... Opening part, 14 ... Metal layer, 15 ... Alloy layer, 20 ... Probe needle, 21 ... Dispenser, 22 ... Wire 30, first insulating layer, 31, first wiring, 32, second wiring, 33, second insulating layer, 34, third insulating layer, 34 a, opening (contact hole), 35, barrier metal, 36 ... Conductive layer, 37 ... Protective film, 37a ... Opening, 38 ... Metal layer, 39 ... Alloy layer, 40 ... Probe needle, 41 ... Dispenser, 42 ... Wire, V ... Void

Claims (16)

A semiconductor device having a pad electrode and connected to the outside by wire bonding at the pad electrode,
A substrate on which an electronic circuit is formed;
The pad electrode formed on the substrate;
A protective film formed to cover the substrate and having an opening for exposing the pad electrode;
And a metal layer formed as an upper layer of the pad electrode in the opening of the protective film. The semiconductor device according to claim 1, wherein an alloyed layer of an element constituting the pad electrode and an element constituting the metal layer is formed at an interface between the pad electrode and the metal layer. The semiconductor device according to claim 1, wherein the metal layer is a gold layer or a gold alloy layer. The semiconductor device according to claim 1, wherein the pad electrode is an aluminum layer or an aluminum alloy layer. The semiconductor device according to claim 1, wherein the pad electrode is a copper layer or a copper alloy layer. The semiconductor device according to claim 5, wherein a barrier metal layer is formed between the pad electrode and the metal layer. The semiconductor device according to claim 6, wherein the barrier metal layer includes cobalt and tungsten. A method of manufacturing a semiconductor device having a pad electrode and connected to the outside by wire bonding at the pad electrode,
Forming the pad electrode on a substrate on which an electronic circuit is formed;
Covering the substrate and forming a protective film having an opening exposing the pad electrode;
Forming a metal-containing resin layer on the pad electrode in the opening of the protective film;
And a step of firing the metal-containing resin layer to form a metal layer. The method for manufacturing a semiconductor device according to claim 8, wherein in the step of baking the metal-containing resin layer to form the metal layer, baking is performed at a temperature of 150 to 250 ° C. The method for manufacturing a semiconductor device according to claim 8, wherein in the step of forming the metal-containing resin layer, the metal-containing resin layer is formed by an inkjet method. In the step of firing the metal-containing resin layer to form a metal layer, an alloyed layer of an element constituting the pad electrode and an element constituting the metal layer is formed at the interface between the pad electrode and the metal layer. The method of manufacturing a semiconductor device according to claim 8. The method for manufacturing a semiconductor device according to claim 8, wherein a gold layer or a gold alloy layer is formed as the metal layer. The method for manufacturing a semiconductor device according to claim 8, wherein an aluminum layer or an aluminum alloy layer is formed as the pad electrode. The method for manufacturing a semiconductor device according to claim 8, wherein a copper layer or a copper alloy layer is formed as the pad electrode. The method for manufacturing a semiconductor device according to claim 14, further comprising a step of forming a barrier metal layer on an upper layer of the pad electrode after the step of forming the pad electrode and before the step of forming the metal-containing resin layer. . The method for manufacturing a semiconductor device according to claim 15, wherein a layer containing cobalt and tungsten is formed as the barrier metal layer.

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